CN100388481C - Integrate circuit chip structure - Google Patents
Integrate circuit chip structure Download PDFInfo
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- CN100388481C CN100388481C CNB2003101226859A CN200310122685A CN100388481C CN 100388481 C CN100388481 C CN 100388481C CN B2003101226859 A CNB2003101226859 A CN B2003101226859A CN 200310122685 A CN200310122685 A CN 200310122685A CN 100388481 C CN100388481 C CN 100388481C
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- scribe line
- metal antenna
- layer metal
- integrated circuit
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Abstract
The present invention discloses an integrate circuit chip structure. Metal antennae are arranged in scribing grooves around a chip. The metal antennae in the scribing grooves around the chip have a plurality of layers which are electrically connected with a silicon wafer substrate through a contact hole plug. The present invention starts from a mechanism of generating plasma damage, and reduces inhomogeneous electric potential of the surface of a silicon wafer because of inhomogeneous plasma bodies in the making process of the back procedure of a semi-conductor device by installing the metal antennae in the scribing grooves around the chip. Simultaneously, the existence of the metal antennae makes the electric potential of the silicon wafer substrate adjusted. Consequently, the intensity of an electric field of a dielectric layer in the chip is largely reduced for achieving the purpose of effectively reducing the plasma damage. The metal antennae of the present invention do not occupy the effective area of the chip and have the advantages of convenient implementation and simple structure. The design difficulty of a mask plate can not be increased.
Description
Technical field
The present invention relates to ic manufacturing technology, particularly relate to a kind of integrated circuit chip structure that reduces plasma damage.
Background technology
Plasma technique is widely used in many professional domains now, is especially bringing into play irreplaceable effect in semiconductor integrated circuit (IC) is made.
For example, after accelerating to ion more than hundreds of electronvolt, bombardment solid target, make target atom break away from the surface, this phenomenon is called as sputter (Sputtering), the particle that sputters out is deposited as film on substrate, this sputtering technology is widely used in the deposition of the metallic film in the IC manufacturing now.
In plasma, high-octane electronics interrupts the gas molecule key, produces a large amount of active groups.These active groups constantly are adsorbed on substrate surface, surface chemical reaction takes place finally grow the film that one deck has new chemical constitution at substrate surface, Here it is is widely used in plasma enhanced CVD (Plasma Enhanced Chemical VaporDeposition, the PECVD) technology that IC makes.
Active group in the plasma directly and chemical reaction takes place the atom (molecule) of substrate surface, the generation escaping gas is constantly overflowed from the surface, substrate surface can be etched gradually, and the bombardment effect meeting of plasma intermediate ion simultaneously promotes directed etching reaction to take place.This lithographic method is called reactive ion etching, and (Reactive Ion Etching, RIE), RIE has become the requisite technology of microfabrication in the IC manufacturing.
At present, utilized " Sputtering " " PECVD " technologies such as " Dry Etch " of plasma technique to be widely used in the IC manufacturing.But because plasma self characteristics (having a large amount of groups active, that be in excitation state in the plasma), these technologies also can be brought plasma damage (Plasma Damage) to silicon wafer.The grid oxygen of MOS transistor is punctured, and drift etc. takes place in the characterisitic parameter of MOS transistor.Along with the arrival in ULSI epoch, plasma damage more and more becomes " killer " of IC acceptance rate, is inevitable problem during IC makes.
The method that reduces plasma damage during current I C produces mainly contains following several: the first, optimize the plasma process menu.Because the extensive property of semiconductor production, board quantity is many, and model is different, difference between the different platform is very big for the state influence of plasma, this just causes the process menu of optimization portable poor, and along with entering the ULSI epoch, the effect of this method becomes more and more limited.The second, the silicon wafer that is subjected to plasma damage is carried out N
2-H
2Thermal annealing under the atmosphere (Annealing) recovers the damage in the silicon wafer.Hydrogen atom enters silicon wafer the influence of IC reliability be can not be ignored in the annealing process, and for reliability requirement more strict today, the method that reduces plasma damage by annealing is worthless.The 3rd, the silicon wafer that is subjected to plasma damage is carried out ultraviolet light (UV) irradiation, utilize the damage in the high-energy photon recovery silicon wafer.For the serious wafer of damage, this method effect is very limited, also is difficult to guarantee not introduce new defective in irradiation process simultaneously.The 4th; during circuit design; add protective circuit at the device place that needs protection; though this method can reduce plasma damage; but protective circuit has taken effective chip area, has reduced the device density of chip, in addition; the existence of protective circuit has increased circuit complexity (may cause the increase of leakage current), and this method seldom adopts in the product therefore big in integrated level, that strictness is controlled to leakage current.In a word, the method for existing reduction plasma damage all exists deficiency separately, and effect is also very limited.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of integrated circuit chip structure, can reduce because the electromotive force of the inhomogeneous silicon wafer surface that brings of plasma is inhomogeneous, the electromotive force of silicon wafer substrate is adjusted, effectively reduced road processing procedure ionic medium infringement odds behind the semiconductor device.
For solving the problems of the technologies described above, integrated circuit chip structure of the present invention is provided with metal antenna in the scribe line around the chip.
Metal antenna around the described chip in the scribe line is a multilayer, realizes being electrically connected by contact hole plug and silicon wafer substrate.
Owing to adopt said structure, in each metal level (Metal layer), all in the scribe line around the chip, place the corresponding metal antenna, the local potential that the existence of metal antenna has changed silicon wafer surface and substrate distributes, thereby reaches the purpose that reduces road processing procedure ionic medium infringement behind the semiconductor device.
Description of drawings
Fig. 1 is the inhomogeneous plasmas schematic diagram;
Fig. 2 is inhomogeneous plasmas and silicon wafer interaction schematic diagram;
Fig. 3 is two rectangular arranged of the present invention and is banded metal antenna position view in the scribe line around the chip;
Fig. 4 is that the present invention is banded metal antenna position view in the scribe line around the chip;
Fig. 5 is that metal antenna of the present invention is for silicon wafer influence of electric potential schematic diagram;
Fig. 6 is that the part that the double layer of metal antenna is set in the scribe line around the chip of the present invention is overlooked, sectional schematic diagram.
Embodiment
Plasma is inhomogeneous to be one of basic reason that causes plasma damage.As shown in Figure 1, plasma externally shows electric neutrality generally, but then may have electron stream I in the part
e -With ion flow I
Ion +Imbalance, thereby cause the imbalance of silicon wafer surface Potential Distributing.As shown in Figure 2, MOS transistor 1 grid potential is V
G 1, MOS transistor 2 grid potentials are V
G 2When | V
G 2-V
G 1| when arriving to a certain degree greatly, the grid oxygen of MOS transistor will be breakdown, perhaps produces defective in grid oxygen, and plasma damage promptly takes place.
The method that in the past reduced plasma damage is conceived to improve the uniformity of plasma, in any case but, the inhomogeneous of plasma part can't be eliminated fully, another thinking is, anneal or the UV irradiation for the silicon wafer that is subjected to plasma damage, attempt to reduce the influence of plasma damage for device property, not only effect is limited for these class methods, and can not be ignored for the influence of chip reliability.And adopt the method that increases protective circuit, owing to take chip real estate, increase circuit complexity, its application is very limited.
Shown in Fig. 3～6, integrated circuit chip structure of the present invention is: in each metal level (Metallayer), all in the scribe line around the chip 10 corresponding metal antenna 1 is set.The local potential that the existence of metal antenna 1 has changed silicon wafer surface and substrate distributes (referring to Fig. 5), thereby reaches the purpose that reduces road processing procedure ionic medium infringement behind the semiconductor device, and a large amount of experimental results have proved validity of the present invention.
Each layer metal antenna 1 around the described chip 10 in the scribe line is multilayer, and realizes being electrically connected by contact hole plug 4 and silicon wafer substrate.
In Fig. 3～6 1 are that metal antenna, 2 is that top-level metallic, 3 is that ground floor metal, 4 is that contact hole plug, 5 is that passivation layer, 6 is that film between ground floor, 7 is that film between the second layer, 8 is that field oxygen, 9 is that transistor part, 10 is that chip, 11 is that scribe line spacing, 12 is N
+/ P
+The injection region.
Each layer metal antenna 1 in the described scribe line is one and is ribbon, is positioned at chip 10 1 avris or another avris at scribe line center, and the width of described ribbon metal antenna 1 is 1/6～1/20 of a scribe line.Perhaps each layer metal antenna in the scribe line 1 is two and is ribbon, is positioned at 10 liang of avris of chip at scribe line center, and the width sum of described two rule strip metal figures is 1/6～1/20 of a scribe line.
Described each multiple layer metal antenna 1 also can be two rectangular arranged and is ribbon, is positioned at 10 liang of avris of chip at scribe line center.The width sum of described rectangle is 1/4～1/10 of a scribe line width, and the breadth length ratio of described rectangle is 0.1～1, and the spacing of described rectangle is 0.2～2 with the ratio of rectangle width, as shown in Figure 4.Perhaps each layer metal antenna 1 also can be a rectangular arranged and is ribbon, be positioned at chip 10 1 avris or another avris at scribe line center, the width of described rectangle is 1/6～1/20 of a scribe line width, the breadth length ratio of described rectangle is 0.1～1, and the spacing of described rectangle is 0.2～2 with the ratio of rectangle width.
In addition, the length of each layer metal antenna 1 in the described scribe line can equal chip length, and perhaps each layer metal antenna 1 constitutes an annular metal antenna 1 around chip 10.
As Fig. 2, shown in Figure 5, the existence of metal antenna 1 in the scribe line around the chip 10, share the electric charge that plasma gathers at silicon wafer surface, thereby effectively reduced the electromotive force of MOS transistor grid: | V
G 1*|＜| V
G 1|, | V
G 2*|＜| V
G 2|, on the other hand, the electromotive force (V of silicon wafer substrate has been adjusted in the existence of metal antenna 1
m 1, V
m 2), the electrical potential difference that finally makes grid oxygen be born reduces greatly: | V
G 1-V
G 1*|＜| V
G 1|, | V
G 2-V
G 2*|＜| V
G 2|, thereby reduced plasma damage.
The present invention is simple in structure, and effect is obvious.Because metal antenna 1 is arranged in chip 10 scribe line on every side, do not take the effective area of chip 10, therefore can not influence the device density of chip 10.From design point of view, because the form of metal antenna 1 is fixed in the scribe line, only need the metal antenna 1 that designs is embedded in the domain (Metal Layer Layout) of formal product, therefore can not increase the difficulty of design.In addition, owing to directly do not link to each other, can not bring adverse effect to chip 10 characteristics with chip 10 interior circuit.
The invention will be further described below in conjunction with a specific embodiment.
The domain of design chips 10 each layer metal (Metal Layer Layout), the metal antenna that designs is embedded in the domain of formal product, be arranged at around the chip 10 in the scribe line side near chip 10, the physical dimension of metal antenna 1 is according to the size of chip 10 and scribe line and appropriate change.
For example, as shown in Figure 3, place two rectangular arranged and be banded metal antenna 1 in the scribe line around each chip 10, the ratio of the wide length of rectangle is 1, and rectangle width sum is 1/4 of a scribe line.
Revise original contact hole (Contact ﹠amp; Via) domain makes each layer metal antenna 1 interconnect by contact hole plug 4, and realizes being electrically connected with silicon wafer substrate.Revise original passivation layer 5 domains (Cover Mask), guarantee to make after passivation layer 5 etchings around the chip 10 metal antenna 1 part in the scribe line to expose (promptly definition metal antenna 1 part is OPEN in passivation layer 5 domains) → be Design Rule Checking (Design Rule Check of domain, DRC), guarantee not violate design rule part (DRC clean), layout data (GDS data) is transferred Mask Shop, plate-making, flow after the acquisition mask.
Claims (10)
1. an integrated circuit chip structure is characterized in that: in the scribe line around the chip metal antenna is set.
2. integrated circuit chip structure according to claim 1 is characterized in that: the metal antenna around the described chip in the scribe line is a multilayer, realizes being electrically connected by contact hole plug and silicon wafer substrate.
3. integrated circuit chip structure according to claim 1 and 2, it is characterized in that: each layer metal antenna in the described scribe line is one and is ribbon, be positioned at chip one avris or another avris at scribe line center, the width of described ribbon metal antenna is 1/6～1/20 of a scribe line.
4. integrated circuit chip structure according to claim 3 is characterized in that: the length of each layer metal antenna in the described scribe line equals chip length, and perhaps each layer metal antenna constitutes a ring-type around chip.
5. integrated circuit chip structure according to claim 1 and 2, it is characterized in that: each layer metal antenna in the described scribe line is two and is ribbon, be positioned at chip two avris at scribe line center, the width sum of described two rule strip metal antennas is 1/6～1/20 of a scribe line.
6. integrated circuit chip structure according to claim 5 is characterized in that: the length of each layer metal antenna in the described scribe line equals chip length, and perhaps each layer metal antenna constitutes a ring-type around chip.
7. integrated circuit chip structure according to claim 1 and 2, it is characterized in that: each layer metal antenna around the described chip in the scribe line is a rectangular arranged and is ribbon, be positioned at chip one avris or another avris at scribe line center, the width of described rectangle is 1/6～1/20 of a scribe line width, the breadth length ratio of described rectangle is 0.1～1, and the spacing of described rectangle is 0.2～2 with the ratio of rectangle width.
8. integrated circuit chip structure according to claim 7 is characterized in that: the length of each layer metal antenna in the described scribe line equals chip length, and perhaps each layer metal antenna constitutes a ring-type around chip.
9. integrated circuit chip structure according to claim 1 and 2, it is characterized in that: each layer metal antenna around the described chip in the scribe line is two rectangular arranged and is ribbon, lay respectively at chip two avris at scribe line center, the width sum of described rectangle is 1/4～1/10 of a scribe line width, the breadth length ratio of described rectangle is 0.1～1, and the spacing of described rectangle is 0.2～2 with the ratio of rectangle width.
10. integrated circuit chip structure according to claim 9 is characterized in that: the length of each layer metal antenna in the described scribe line equals chip length, and perhaps each layer metal antenna constitutes a ring-type around chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101226859A CN100388481C (en) | 2003-12-24 | 2003-12-24 | Integrate circuit chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101226859A CN100388481C (en) | 2003-12-24 | 2003-12-24 | Integrate circuit chip structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1632949A CN1632949A (en) | 2005-06-29 |
| CN100388481C true CN100388481C (en) | 2008-05-14 |
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ID=34844582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101226859A Expired - Fee Related CN100388481C (en) | 2003-12-24 | 2003-12-24 | Integrate circuit chip structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100388481C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1147152A (en) * | 1995-06-22 | 1997-04-09 | 日本电气株式会社 | Input Protection Circuit for Semiconductor Devices for Improving Electrostatic Breakdown Voltage |
| US6497943B1 (en) * | 2000-02-14 | 2002-12-24 | International Business Machines Corporation | Surface metal balancing to reduce chip carrier flexing |
| US6498056B1 (en) * | 2000-10-31 | 2002-12-24 | International Business Machines Corporation | Apparatus and method for antifuse with electrostatic assist |
-
2003
- 2003-12-24 CN CNB2003101226859A patent/CN100388481C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1147152A (en) * | 1995-06-22 | 1997-04-09 | 日本电气株式会社 | Input Protection Circuit for Semiconductor Devices for Improving Electrostatic Breakdown Voltage |
| US6497943B1 (en) * | 2000-02-14 | 2002-12-24 | International Business Machines Corporation | Surface metal balancing to reduce chip carrier flexing |
| US6498056B1 (en) * | 2000-10-31 | 2002-12-24 | International Business Machines Corporation | Apparatus and method for antifuse with electrostatic assist |
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| Publication number | Publication date |
|---|---|
| CN1632949A (en) | 2005-06-29 |
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| C14 | Grant of patent or utility model | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20171228 Address after: Zuchongzhi road 201203 Shanghai Pudong New Area Zhangjiang High Tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Hua Hong NEC Electronics Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080514 |