CN100386883C - Nonvolatile memory cell, operating method thereof and nonvolatile memory - Google Patents

Abstract

A nonvolatile memory cell includes a substrate, a charge trapping layer, a control gate, a source, a drain and a shallow doped region of a first conductive state, and a pocket doped region of a second conductive state. The charge trapping layer is on the substrate, the control gate is on the charge trapping layer, and there is a dielectric layer between the substrate, the charge trapping layer and the control gate. The source and the drain are in the substrate on both sides of the charge trapping layer, respectively. The shallow doped region is located on the surface of the substrate between the source and the charge trapping layer, and the pocket doped region is located in the substrate between the drain and the charge trapping layer. Since the present invention has an asymmetric implantation structure with different conductive states, it can increase the programming speed of the memory cell, prevent interference between adjacent memory cells, and reduce the additional area occupied by the bit line selection transistor.

Description

Non-volatile storage unit, operation method thereof and non-volatile memory

technical field

The present invention relates to a non-volatile storage element, and in particular to a non-volatile storage unit in which an asymmetric doping structure is formed in the non-volatile storage unit, an operation method thereof and a non-volatile storage unit. Memory.

Background technique

Among all kinds of non-volatile memory products, it has the advantages of multiple data storage, reading, deletion and other operations, and the stored data will not disappear after power off. Read Only Memory (EEPROM) has become a memory component widely used in personal computers and electronic devices.

A typical electrically erasable and programmable read-only memory uses doped polysilicon to make a floating gate and a control gate. When the memory is programmed, the electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate layer. However, when there are defects in the tunneling oxide layer under the polysilicon floating gate layer, it is easy to cause leakage current of the component and affect the reliability of the component.

Therefore, at present, a flash storage unit for programming by hot hole injection nitride electron storage (PHINES for short) has been developed, as shown in FIG. 1 .

FIG. 1 is a cross-sectional view of a known PHINES type flash storage unit. Please refer to FIG. 130a, the drain 130b and the silicon monoxide-silicon nitride-silicon oxide layer (ONO layer) 110 between the control gate 120 and the substrate 100, wherein the silicon oxide-silicon nitride-silicon oxide layer (ONO layer) 110 It is composed of two silicon oxide layers 112 and 116 sandwiching a silicon nitride layer 114, and the silicon nitride layer 114 is used here as a charge trapping layer.

The operation method of the PHINES-type flash storage unit in Figure 1 is mainly to use local band to band tunneling hot hole (BTBT HH) for programming and to use a uniform channel F-N (channel Fowler-Nordheim) to delete.

Although the PHINES-type flash storage unit has the advantages of low power consumption, low leakage problem and simplified manufacturing process, the storage unit still has some unavoidable disadvantages. For example, a PHINES type flash memory cell can basically store one bit on the drain side and one bit on the source side. However, if one bit has been stored on the drain side, a second bit effect ( ^2nd bit effect) will be generated during the reverse read, resulting in a reverse read threshold voltage (threshold voltage, Vt) Therefore, a high read bias is required, but this leads to serious read disturb problems. Furthermore, the PHINES-type flash memory storage unit still has the problem of slow programming speed to be solved. In addition, a general PHINES type flash memory cell requires three sets of bit line selection transistors (BLT) for programming, so it has the disadvantage of large overhead effect, which reduces the density of the memory array.

Contents of the invention

The object of the present invention is to provide a non-volatile memory unit to increase the programming speed of the memory unit and prevent interference between adjacent memory units.

Another object of the present invention is to provide a non-volatile memory, which can not only increase the programming speed of memory cells, but also reduce the extra area occupied by bit line selection transistors.

Another object of the present invention is to provide a method for operating a non-volatile memory, which can avoid complex operations and further reduce the number of bit line selection transistors.

The present invention proposes a nonvolatile memory unit, including a substrate, a charge trapping layer on the substrate, a control gate on the charge trapping layer, a first gate between the substrate and the charge trapping layer a dielectric layer, a second dielectric layer between the control gate and the charge trapping layer, a source and a drain of a first conductivity state, a lightly doped region of the first conductivity state, and a pocket of the second conductivity state doped area. Wherein, the source and the drain are respectively located in the substrate on both sides of the charge trapping layer. Moreover, the lightly doped region of the first conductive state is located in the substrate between the source and the charge trapping layer, and the pocket doped region of the second conductive state is located in the substrate between the drain and the charge trapping layer. .

According to the nonvolatile memory unit described in the first embodiment of the present invention, the charge trapping layer may be a silicon nitride layer or other suitable material layers.

According to the nonvolatile memory cell according to the first embodiment of the present invention, the first conductive state is N-type and the second conductive state is P-type.

The present invention further proposes a non-volatile memory, comprising a substrate, several buried bit lines of the first conductive state located in the substrate, word lines on the substrate and across the buried bit lines , the charge trapping layer between the substrate and the word line between the buried bit lines, the first dielectric layer between the charge trapping layer and the substrate, the second dielectric layer between the word line and the charge trapping layer The electrical layer, the lightly doped region with the first conductive state and the pocket doped region with the second conductive state. Wherein, the lightly doped region is located in the substrate on one side of each buried bit line, and the pocket doped area is located in the substrate on the other side of each buried bit line.

According to the nonvolatile memory according to the second embodiment of the present invention, the above-mentioned charge trapping layer may be a silicon nitride layer or other suitable material layers.

According to the nonvolatile memory according to the second embodiment of the present invention, the above-mentioned first conductive state is N-type and the second conductive state is P-type.

The nonvolatile memory according to the second embodiment of the present invention further includes two bit line selection transistors electrically connected to the buried bit lines.

The present invention further provides a method for operating a non-volatile memory unit, wherein the non-volatile memory unit includes a first drain, a second drain, and a source of a first conductive state in a substrate. electrode, a word line on the substrate and across the first, second drain and source, the substrate between the first and second drain and source, and several charge trapping layers between the word lines , a first dielectric layer located between each charge trapping layer and the substrate, a second dielectric layer located between the word line and each charge trapping layer, a substrate located on one side of each drain and source A lightly doped region of the first conductivity state within the bottom and a pocket doped region of the second conductivity state on the other side of each drain and source. This operation method includes when performing a programming operation, applying a first bias voltage to the word line, applying a second bias voltage to the source, and the first drain is in a grounded state and the second drain is in a floating state, wherein the first drain is in a grounded state and the second drain is in a floating state. The voltage value of the first bias voltage is lower than the voltage value of the second bias voltage.

According to the operation method of the non-volatile memory unit described in the second embodiment of the present invention, it also includes when performing an erasing operation, applying a bias voltage for performing channel F-N erasing on the word line, the first drain and The source is in a grounded state, and the second drain is in a floating state.

According to the operation method of the non-volatile memory cell described in the second embodiment of the present invention, it also includes when performing a read operation, applying a third bias voltage to the word line, and applying a relatively lower voltage to the first drain than For the voltage of the third bias voltage, the source is in a grounded state, and the second drain is in a floating state.

Because the present invention applies the implantation structure of asymmetry and different conduction states to the nonvolatile memory cell for programming by injecting thermal holes into the nitrided electron storage, it can increase the implantation dose of the pocket doped region to increase programming speed without loss of read capability. Moreover, the lightly doped region of the present invention uses a lower read bias to read through a higher threshold voltage (Vt) channel, which can further prevent interference caused by programming of adjacent memory cells. In addition, the lightly doped region can also reduce the generation of channel hot electrons (CHE), thereby reducing the problem of read distribution during reverse read. Furthermore, the structure of the present invention does not require isolation lines between memory cells, thus simplifying the programming system and simplifying the circuit. In addition, since the non-volatile memory cell of the present invention only needs to control one set of bit lines during programming, the additional area occupied by the bit line selection transistor (BLT) can also be reduced. In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a cross-sectional view of a known PHINES type flash storage unit.

FIG. 2 is a schematic cross-sectional view of a non-volatile memory unit according to the first embodiment of the present invention.

FIG. 3A is a circuit diagram of a non-volatile memory according to a second embodiment of the present invention.

FIG. 3B is a schematic cross-sectional view of the non-volatile memory in part B shown in FIG. 3A .

FIG. 3C is a schematic cross-sectional view of another non-volatile memory in part B shown in FIG. 3A .

Symbol Description

10: Flash storage unit 20: Non-volatile storage unit

100, 200, 300: substrate 110: silicon oxide-silicon nitride-silicon oxide layer

112, 116: Silicon oxide layer 114: Silicon nitride layer

120, 220: control grid 130a, 230a: source

130b, 230b: drain 202, 302: lightly doped region

204, 304: pocket doped regions 212, 216, 306, 312, 316: dielectric layer

214, 314: Charge trapping layer 320: Character line

330: Buried bit line 350: Bit line select transistor

Detailed ways

According to the present invention, there is provided a non-volatile memory cell of "programming by hot hole injection nitride electron storage (abbreviated as PHINES)" and its operation method and non-volatile volatile memory.

first embodiment

FIG. 2 is a schematic cross-sectional view of a nonvolatile memory unit according to a first embodiment of the present invention. Referring to FIG. 2, the nonvolatile memory unit 20 of this embodiment includes a substrate 200, a charge trapping layer 214 on the substrate 200, a control gate 220 on the charge trapping layer 214, and a 200 and the charge trapping layer 214 between the first dielectric layer 212, the second dielectric layer 216 between the control gate 220 and the charge trapping layer 214, the source electrode 230a and the drain electrode 230b of the first conductivity state, with The lightly doped region 202 of the first conductivity state and the pocket doped region 204 of the second conductivity state, wherein the first conductivity state is, for example, N type and the second conductivity state is, for example, P type. The source 230 a and the drain 230 b are respectively located in the substrate 200 on both sides of the charge trapping layer 214 , and a channel region (not shown) is formed in the substrate 200 between the source 230 a and the drain 230 b. Moreover, the lightly doped region 202 of the first conductive state is located in the substrate 200 between the source 230a and the charge trapping layer 214, and the pocket doped region 204 of the second conductive state is located between the drain 230b and the charge trapping layer. 214 in the substrate. The substrate 202 may include conventional semiconductor materials such as silicon, and the charge trapping layer 214 may be a silicon nitride layer or other suitable material layers. The first dielectric layer 212 and the second dielectric layer 216 include, for example, a silicon oxide layer or other suitable material layers, or different material layers.

Please continue to refer to FIG. 2 , which shows the distribution profile of electrons and holes in the charge trapping layer 214 when the memory cell 20 is programmed. The operation method of the non-volatile memory cell 20 in FIG. 2 is mainly to use local band-to-band tunneling hot holes (BTBT HH) for programming and use a uniform channel F-N for erasure. In addition, the storage unit 20 of this embodiment can also be applied to a (multi-bit-per-cell) system; that is, hot holes can be used on the right side of the non-volatile storage unit 20 through interband tunneling. Various levels of starting voltage to obtain more storage states. For example, a 4-level Vt design can be fabricated with 2-bit storage states per cell. However, it can be known that the “left side” and “right side” are relative terms determined according to the configuration of the memory cells, and the terms may vary with the relative positions of the lightly doped region 202 and the pocket doped region 204. be replaced without affecting the functionality of the memory unit.

When the memory cell 20 of this embodiment is operated in the PHINES mode, the drain 230b having the pocket doped region 204 can significantly improve the inter-band tunneling hot hole programming efficiency and have faster The programming speed is high, and the source 230a with the lightly doped region 202 can suppress the generation of hot holes tunneling between energy bands. Therefore, the non-volatile memory cells of the present invention will not require known methods for inhibiting bits.

In addition, the nonvolatile memory cell 20 with an asymmetric doping structure in this embodiment can prevent punchthrough of the shallow doping region 202 by increasing the implantation dose of the pocket doping region 204, and at the same time The programming speed of the memory cells can be improved at the same time.

second embodiment

3A is a circuit diagram of a non-volatile memory according to the second embodiment of the present invention; FIG. 3B is a schematic cross-sectional view of the non-volatile memory of part B shown in FIG. 3A; FIG. 3C is a schematic diagram of the non-volatile memory shown in FIG. A cross-sectional schematic diagram of another non-volatile memory shown in part B.

Please refer to FIG. 3A and FIG. 3B first. The non-volatile memory of this embodiment is mainly composed of a substrate 300, several buried bit lines 330 of the first conductive state located in the substrate 300, and a plurality of embedded bit lines 330 in the substrate 300. The word line 320 on and across the buried bit line 330, the charge trapping layer 314 between the substrate 300 and the word line 320 between the buried bit lines 330, the charge trapping layer 314 and the substrate 300 The first dielectric layer 312, the second dielectric layer 316 between the word line 320 and the charge trapping layer 314, the lightly doped region 302 with the first conductivity state and the pocket doped region 304 with the second conductivity state , wherein the first conductive state is, for example, N type and the second conductive state is, for example, P type. The lightly doped region 304 is located in the substrate 300 on one side of each buried bit line 330 , and the pocket doped region 304 is located in the substrate 300 on the other side of each buried bit line 330 .

In addition, referring to FIG. 3B and FIG. 3C, the dielectric layer 306 can be filled between the charge trapping layer 314 and the word line 320, as shown in FIG. 3B, to isolate the two; or as shown in FIG. 3C, the charge The trapping layer 314 , the first dielectric layer 312 and the second dielectric layer 316 extend on the entire substrate 300 .

In addition, in order to operate the memory, two bit line select transistors (BLT) 350 are also shown in FIG. 3A , electrically connected to the buried bit line 330 and the word line 320 .

Please continue to refer to FIG. 3A and FIG. 3B. When it is desired to perform a programming operation on the left side of BS (ie, the source electrode of the buried bit line 330) in the figure, a first bias is applied to WL (ie, the word line 320). voltage, and a second bias voltage is applied to BS, while BDL (that is, the first drain of the buried bit line 330) is in the ground state, and BDR (that is, the second drain of the buried bit line 330 pole) is a floating state, wherein the voltage value of the first bias voltage is lower than the voltage value of the second bias voltage. At the same time, the bits to the right of BS will be suppressed because the BDR is in a floating state and has n-type lightly doped region 304 . However, it can be seen that the aforementioned “left side” and “right side” are relative terms determined according to the configuration of the memory cells, and the terms can be changed according to the relative positions of the lightly doped region 302 and the pocket doped region 304 replacement without affecting the functionality of the storage unit.

When you want to delete the memory cell, you only need to apply a bias voltage for channel F-N deletion to WL, make BDL and BS grounded, and BDR floating. As a result, the charge trapping layer 314 will be filled with electrons.

When performing a read operation, a third bias voltage can be applied to WL by the reverse read method, and a voltage relatively lower than the third bias voltage can be applied to BDL, and at the same time, the BS can be grounded, while the BDR is still floating. set state.

Table 1 below shows the voltage values of the bias voltages for the operation of the non-volatile memory in this embodiment. It can be seen from Table 1 that only two bit line selection transistors 350 are required to manipulate a set of word lines WL and a set of bit lines BS when the memory of this embodiment performs programming operations, and the bias voltage to BDL only needs to be smaller than 1.6V. can be read.

Table 1 (unit: V)

BDL BS BDR WL FN-delete 0 0 floating -20 HH-programming 0 5 floating -5 read ＜1.6 0 floating 5

In summary, the present invention is characterized in that:

1. The present invention applies an implant structure of asymmetry and different conduction states to a nonvolatile memory cell for programming by injecting thermal holes into a nitrided electron storage device, so the implantation of the pocket doped region can be increased. Dosage can be used to increase the programming speed without losing the reading ability, and the introduction of lightly doped regions can prevent the interference of adjacent memory cells due to programming.

2. The present invention adopts a lower read bias voltage through the lightly doped region in its structure, so that it can be read through a higher threshold voltage (Vt) channel. In addition, the lightly doped region can also reduce the generation of channel hot electrons (CHE), thereby reducing the problem of read distribution during reverse read.

3. The structure of the present invention does not require an isolation line to be provided between memory cells, thereby simplifying the programming system and simplifying the circuit.

4. The non-volatile memory cell of the present invention only needs to control a set of bit lines during programming, so the extra area occupied by the bit line selection transistor (BLT) can be reduced, thereby increasing the density of the storage array.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (15)

1. non-volatile memory cells is characterized in that: comprising:

One substrate;

One charge immersing layer is positioned on this substrate;

One control grid is positioned on this charge immersing layer;

One first dielectric layer is between this substrate and charge immersing layer;

One second dielectric layer is between this control grid and charge immersing layer;

The one source pole of one first conductive state and a drain electrode lay respectively in the substrate of charge immersing layer both sides;

One shallow doped region of this first conductive state of tool is in the substrate between this source electrode and charge immersing layer; And

One pocket doped region of tool one second conductive state, in this substrate between this drain electrode and charge immersing layer, wherein, the degree of depth of the second conductive state pocket doped region is set for dark than the degree of depth of the shallow doped region of first conductive state.

2. non-volatile memory cells as claimed in claim 1 is characterized in that: this charge immersing layer comprises silicon nitride layer.

3. non-volatile memory cells as claimed in claim 1 is characterized in that: this first conductive state is the N type.

4. non-volatile memory cells as claimed in claim 1 is characterized in that: this second conductive state is the P type.

5. non-volatile memory cells as claimed in claim 1 is characterized in that: also comprising a channel region, is the substrate that is positioned between this source electrode and drain electrode.

6. Nonvolatile memory is characterized in that: comprising:

One substrate;

Most bar embedded type bit line of one first conductive state are positioned at this substrate;

Many character lines are on this substrate and across these embedded type bit line;

One charge immersing layer is at this substrate between this embedded type bit line respectively and respectively between this character line;

One first dielectric layer is between this charge immersing layer and this substrate;

One second dielectric layer is respectively between this character line and this charge immersing layer;

One shallow doped region of this first conductive state of tool is positioned at respectively this substrate of a side of this embedded type bit line; And

One pocket doped region of tool one second conductive state is arranged in respectively this substrate of the opposite side of this embedded type bit line, and wherein, the degree of depth of the second conductive state pocket doped region is set for dark than the degree of depth of the shallow doped region of first conductive state.

7. Nonvolatile memory as claimed in claim 6 is characterized in that: this charge immersing layer comprises silicon nitride layer.

8. Nonvolatile memory as claimed in claim 6 is characterized in that: this first conductive state is the N type.

9. as claim 6 a described Nonvolatile memory, it is characterized in that: this second conductive state is the P type.

10. Nonvolatile memory as claimed in claim 6 is characterized in that: also comprising a channel region, is this substrate that is positioned between these embedded type bit line.

11. Nonvolatile memory as claimed in claim 6 is characterized in that: also comprise two bit line selection transistors, be electrical connected with these embedded type bit line.

12. Nonvolatile memory as claimed in claim 6 is characterized in that: this charge immersing layer, this first dielectric layer and second dielectric layer also comprise on this substrate that extends whole.

13. the method for operation of a non-volatile memory cells, it is characterized in that: this non-volatile memory cells comprises first drain electrode of first conductive state that is positioned at a substrate, second drain electrode and the one source pole, on this substrate and across this first, one character line of second drain electrode and source electrode, be positioned at this first, this substrate between second drain electrode and source electrode and the charge immersing layer between this character line, one first dielectric layer between this charge immersing layer and this substrate, one second dielectric layer between this character line and this charge immersing layer, be positioned at each this first, one shallow doped region of this first conductive state in this substrate of second drain electrode and a side of source electrode and be positioned at each first, one pocket doped region of one second conductive state of the opposite side of second drain electrode and source electrode, this method of operation comprises:

When carrying out a programming operation, apply one first bias voltage at this character line, apply one second bias voltage at this source electrode, and first drain electrode is that ground state and this second drain electrode are floating state, wherein the magnitude of voltage of this first bias voltage is lower than the magnitude of voltage of this second bias voltage.

14. the method for operation of non-volatile memory cells as claimed in claim 13 is characterized in that: also comprise:

When carrying out a deletion action, apply the bias voltage of carrying out raceway groove F-N deletion at this character line, this first drain electrode is a ground state with source electrode, and second drain electrode is floating state.

15. the method for operation of non-volatile memory cells as claimed in claim 13 is characterized in that: also comprise:

When carrying out a read operation, apply one the 3rd bias voltage at character line, apply the voltage that is lower than the 3rd bias voltage relatively in this first drain electrode, this source electrode is a ground state, and second drain electrode is floating state.

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