CN100385412C - Memory module control device - Google Patents

Abstract

A memory module control device at least has a multiplexer, an automatic detection circuit and a terminal device. Each memory slot of the system transmits a signal to the automatic detection circuit, which determines the use status of each slot and outputs a status signal to the multiplexer as a control signal. The slot outputs a signal to the input end of the multiplexer. The output end of the multiplexer is connected to the terminal device. The automatic detection circuit transmits a control signal to the multiplexer, and the multiplexer selects one of the input ends to be connected to the output end of the multiplexer. The output signal of the last slot with a memory module inserted can be automatically connected to the terminal device to form a complete transmission channel for data signals and clock pulse signals.

Description

Memory Module Control

technical field

The invention relates to a memory module device, in particular to a control device for a high-speed memory module.

Background technique

Memory is a very important component in a computer system, and currently the most widely used is a storage device called dynamic random access memory (DRAM). In recent years, DRAM technology has shown dramatic development. The density of memory elements ranges from one thousand bits (1K bits) to sixty-four million bits (64M bits) per chip, but the performance of DRAM has not improved as much as its capacity. What's more, the performance speed of the current microprocessor (micro processor) is so fast that it is difficult to match the performance between the microprocessor and the memory. Therefore, many complex and expensive memory control access systems have been developed to increase memory performance: such as synchronous random access memory caches (synchrotron random access memory caches, SRAM caches) and DRAM parallel arrays (parallel arrays of DRAMs) and other technologies.

In order to solve memory performance problems and reduce technical difficulties, Rambus has developed a chip-to-chip (chip to chip) bus technology in memory and its corresponding control interface, and defined the specifications of this memory module. This bus control technology is called direct Rambus channel (direct Rambus channel), which can connect memory chips to, for example, microprocessors, graphics processors (graphics processors), and ASICs. This channel uses only a few high-speed signals to carry all address, data, and control signals. The memory module derived from this specification and technology is called Rambus dynamic random access memory module (Rambus DRAM module) or RIMM.

As shown in FIG. 1A to FIG. 1C , they respectively depict the memory control interfaces of four-channel, two-channel and single-channel direct Rambus channels. The memory chip 10 is directly connected to a control interface 16 on a memory controller 14 via a direct Rambus channel 12 . It can be seen from the drawings that all chipsets 10 in the memory module of this technology are connected in series by one channel 12 . The data transmission rate of each channel is at least 1.6 GB bytes, so the data transmission rates in FIG. 1A to FIG. 1C are 6.4 GB bytes, 3.2 GB bytes and 1.6 GB bytes respectively. Therefore, the RIMM memory module has the advantages of high performance and low cost.

Although the RIMM memory module has the above-mentioned advantages, it requires a very high system operating frequency, which is as high as 400 MHz, to make the RIMM memory module work normally. Therefore, the terminals of the memory module must have appropriate terminators to prevent the reflection of high frequency signals.

Referring to FIG. 2A, after three RIMM memory modules 20a, 20b and 20c are inserted into the memory slots, the memory chips 22a, 22b and 22c between the modules are completely connected in series by channels 24. The module 20a is connected to the control interface 26a on the memory controller 26 by the channel 24, and the last module 20c is connected to the terminator 28 and the clock pulse generator 29 with the channel, so that the memory controller 26, the memory module and the A complete signal path is formed between the terminators 28 . However, if the slots of the memory module are not completely filled, as shown in FIG. 2B , when only one of them is plugged in, a complete signal path cannot be formed among the memory controller 26, the memory module and the terminator 28. . A known technique is to insert two dummy RIMM modules (dummy RIMM modules) 20b' and 20c' into the slots where no memory modules are inserted. There are no memory chips on the virtual RIMM modules 20b' and 20c', which only provide signal paths, so that a complete signal can be formed between the memory controller 26, the memory module 20a, the terminator 28 and the clock pulse generator 29. The channel is used to transmit the address, data and control signals of the control memory.

It can be seen from the above that, in order to solve the problem of complete signal connection in the known technology, a slot without a memory module is inserted into a replacement virtual memory module. Thus, there is a problem of occupying memory slots. In addition, if a new memory module is to be added, there will be a problem of inconvenient disassembly and assembly. In addition, using the virtual memory module will increase the cost even more.

Contents of the invention

Therefore, the object of the present invention is to provide a memory module control device, which can use the simplest method to achieve a complete signal connection between the memory module, the terminator and the clock pulse generator.

Another object of the present invention is to provide a memory module control device, which can automatically detect which memory module slot is inserted with a memory module, and automatically connect the signal path between the memory module and the terminal stand up.

To achieve the above and other objectives, the present invention provides a memory module control device, which is briefly described as follows:

The device of the invention can be used to detect the use status of the memory slot in a computer system, and automatically connect the memory module to the terminal device to form a complete signal transmission channel. The memory module control device at least includes a multiplexer, an automatic detection circuit and a terminal device. Each memory slot of the system sends a signal to the automatic detection circuit, and the circuit judges the usage status of each slot, and outputs a status signal to the multiplexer as a control signal.

Each memory slot also outputs a signal to the input of the multiplexer. The output of the multiplexer is then connected to a terminal device. A control signal sent by the auto-detection circuit to the multiplexer which selects one of the inputs to be connected to the output of the multiplexer. Therefore, the output signal of the last slot where the memory module is inserted can be automatically connected to the terminal device to form a complete transmission channel for data signals and clock pulse signals. Therefore, it is not necessary to insert a virtual memory into a slot in which a memory module is inserted.

The memory module control device of the present invention includes: a memory control device for controlling the access of at least one memory; a first, a second and a third slot, respectively having a signal input terminal and a signal output end, the signal output end of the first slot is coupled to the signal input end of the second slot, the signal output end of the second slot is coupled to the signal input end of the third slot, And the first, the second and the third slots form a serial connection structure, the signal input end of the first slot is coupled to the memory control device; a multiplexer has a first, a second and a third input terminal and an output terminal, the output terminals of the first, the second and the third slot are also respectively coupled to the first, the second and the multiplexer the third input terminal; a terminal device coupled to the output terminal of the multiplexer; and an automatic detection circuit for detecting the usage status of the first, the second and the third slots, so as to outputting a status signal to an input terminal of the multiplexer for selecting one of the signal output terminals of the first, the second and the third slots so that the output signal is transmitted to the terminal device .

The memory control device of the present invention can automatically connect the terminal device to the last memory module with a simple control circuit to form a complete signal transmission channel. Therefore, the overall cost is thus reduced, making its application products more competitive in the market.

Furthermore, since there is no need to use a virtual memory module as in the known technology, any user can easily disassemble and assemble the memory module without considering the connection of the terminal. Terminators are automatically determined by the system and should be connected to the correct location.

Description of drawings

In order to make the above objects, features, and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows.

1A to FIG. 1C are schematic diagrams of memory control interfaces of four-channel, two-channel and single-channel direct Rambus channels respectively;

FIG. 2A is a schematic diagram of connection of signal paths between a memory controller, a memory module, and a terminator;

FIG. 2B is a schematic diagram of connection of signal paths between memory controllers, memory modules and terminators by replacing memory modules with virtual memory modules in the known technology;

Fig. 3 is a preferred embodiment of the memory module control device of the present invention:

FIG. 4 is another preferred embodiment of the memory module control device of the present invention.

Detailed ways

Referring to FIG. 3 , it is a structural block diagram of a memory module control device according to the present invention.

The memory control device is a signal terminator control device suitable for direct Rambus channel DRAM (direct Rambus channel DRAM) specification or RIMM specification. It can be applied to general computer systems.

As shown in Figure 3, taking a PENTIUM II class computer as an example, its CPU has the ability to control three sets of RIMM memory modules. The access control of the memory is controlled by the memory controller 30. The memory controller 30 can transmit a plurality of signals about memory addresses, data, control signals and clock pulse signals, thereby selectively accessing the memory in the RIMM memory module. One of the memory chips performs access control. Three sets of memory modules can be respectively inserted into the first, second and third slots 32a, 32b and 32c as shown in the figure. The slots 32a, 32b and 32c respectively have signal input terminals A1-A3 and signal output terminals B1-B3. The signal output terminal B1 of the first slot 32a is coupled to the signal input terminal A2 of the second slot 32b, and the signal output terminal B2 of the second slot 32b is coupled to the signal input terminal A3 of the third slot 32c. The above-mentioned first, second and third RIMM memory slots 32 a , 32 b and 32 c form a cascaded structure (castcade), and the signal input terminal A1 of the first slot 32 a is coupled to the memory control device 30 .

The connection between the above-mentioned signal ends is connected by a bus (bus). In the present invention, a direct Rambus channel (direct Rambus channel) is used as an interface bus to transmit memory addresses, data, control signals and Majority signal of the clock pulse signal.

The multiplexer 34 has first, second and third input terminals X1, X2 and X3 and an output terminal Y. The output terminals B1 - B3 of the three sets of slots 32 a , 32 b and 32 c are respectively coupled to the first, second and third input terminals X1 , X2 and X3 of the multiplexer 34 . The terminal device 36 is coupled to the output terminal Y of the multiplexer 34 . The input terminals of the automatic detection circuit 38 are respectively coupled to the three groups of slots 32a, 32b and 32c to detect the usage status of the slots, determine whether a RIMM memory module is inserted, and output a status signal to the multiplexer 34 , used to select the signal transmitted by one of the signal output terminals B1 , B2 or B3 of the three groups of slots 32 a , 32 b and 32 c , so that the output signal can be transmitted to the terminal device 36 . The above terminal device 36 may also include a terminator and a clock pulse generator. The clock pulse generator is a circuit capable of generating high-frequency clock pulses, which can generate a working frequency up to 400MHz to drive the RIMM memory module.

The input end of the automatic detection circuit 38 can be connected to the ground end of the pin of each slot to determine whether the RIMM memory module is inserted into the slot.

When there is only one slot, such as slot 32a, when the memory is plugged in, the detection circuit 38 will detect that the slots 32b and 32c are empty, so the output status signal informs the multiplexer 34 to select the output terminal of the slot 30a. The output signal is connected to the output terminal Y, so the terminal device 36 is automatically connected to the memory module inserted in the first slot to form a complete signal path. In the same way, when two memories are inserted into the slots 32a and 32b, the multiplexer 34 selects the input terminal X2 as the connection with the output terminal Y due to the function of the detection circuit 38 . When the slots 32a, 32b and 32c are fully filled with RIMM memory modules, the input terminal X3 is connected to the output terminal Y.

From the above, the memory module control device of the present invention can automatically detect the use state of the slot through a simple circuit, so it can automatically connect the last group of memory modules to the terminal device without requiring Additional virtual memory modules are inserted above unused slots. This saves costs with the advantage of quick changeover of the memory. That is, as long as the memory module is directly plugged in, the system will automatically determine the signal output terminal on which slot the terminal device should be connected to.

The above example is an example with three memory slots, but the actual application may be applicable to a memory system with multiple slots.

The device presented in the first embodiment is convenient for the user. However, the multiplexer must switch many signals, such as memory address, data, control signal and clock pulse signal, etc. Therefore, the circuit design of the multiplexer is very complicated. Furthermore, the cost will be higher. The structure of the control device proposed in this embodiment is a structure that can simplify the multiplexer circuit. The multiplexer is only used to switch the clock pulse signal, so its internal circuit can be greatly simplified. However, a specially designed dummy RIMM module is required. The virtual memory module includes a terminator circuit and a clock loop.

Referring to FIG. 4 , it is another preferred embodiment of the memory module control device of the present invention.

As shown in the figure, still taking a PENTIUM II computer as an example, its CPU has the ability to control three sets of RIMM memory modules. The access control of the memory is controlled by the memory controller 40. The memory controller 40 can transmit most signals about the memory address, data, control signals and clock pulse signals, thereby selectively accessing one of the RIMM memory modules. A memory chip performs access control. Three sets of memory modules can be respectively inserted into the first, second and third slots 42a, 42b and 42c as shown in the figure. The slots 42a, 42b and 42c respectively have signal input terminals A1-A3 and signal output terminals B1-B3. The signal output terminal B1 of the first socket 32a is coupled to the signal input terminal A2 of the second socket 32b, and the signal output terminal B2 of the second socket 42b is coupled to the signal input terminal A3 of the third socket 42c. The above-mentioned first, second and third RIMM memory slots 42 a , 42 b and 42 c form a cascaded structure (castcade), and the signal input terminal A1 of the first slot 42 a is coupled to the memory control device 40 .

In addition, each slot also has clock pulse input terminals C1-C3 and clock pulse output terminals D1-D3, wherein the clock pulse input terminal C1 of the slot 42a is coupled to the memory controller 40 and the clock pulse output terminal D1 is coupled to Clock pulse input terminal C2 of slot 42b. The multiplexer 44 has first and second input terminals X1, X2 and an output terminal Y, the output terminal Y is coupled to the clock pulse output terminal D2 of the second slot 42b, and the first input terminal X1 is coupled to The clock pulse input terminal C3 of the third slot 42c. The first terminal device 46 is coupled to the signal output terminal B3 of the third slot 42c. The second terminal device 48 is coupled to the clock output terminal D3 of the third slot 42 c and the second input terminal X2 of the multiplexer 44 .

The automatic detection circuit 50 has first and second signal input ends E, F coupled to the second slot 42b and the third slot 42c respectively, for detecting the use status of the second and third slots 42b, 42c, A status signal is thereby output to the multiplexer 44 . When the state signal judges that a virtual memory module is inserted in the second slot 42b, the multiplexer 44 selects the second input terminal X2 to be connected to the output terminal Y; and when the state signal judges that the virtual memory module is inserted in the third slot When slot 42c is selected, the multiplexer 44 selects the first input terminal X1 to be connected to the output terminal Y. In this way, a complete clock pulse signal path of the memory module can be completed.

From the above, the memory module control device of the present invention can automatically detect the use status of the slot by using a simple circuit and a specially designed virtual memory module, so it can automatically replace the last group of virtual memory modules. group connected to the clock pulse termination device. The multiplexer only needs to select the clock pulse signal, so its internal circuit design is relatively simple. Costs can thus be saved. That is, as long as the memory module is directly inserted, and a specially designed virtual memory module is inserted at the end, the system will automatically determine which slot the clock signal output terminal of the clock terminal device should be connected to.

The above example is an example with three memory slots, but the actual application may be applicable to a memory system with multiple slots.

Therefore, the feature of the present invention is to use a simple multiplexer and an automatic detection circuit to determine which memory slot the terminal device should be connected to, without filling unused slots with virtual memory modules.

Another feature of the present invention is to use a simple multiplexer and automatic detection circuit and a specially designed virtual memory module, which can automatically detect the use status of the slot, and output the clock pulse signal of the virtual memory module Connect to a clock pulse terminator.

Another feature of the present invention is that the circuit is simple and easy to manufacture, so the cost can be reduced.

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of claims.

Claims (16)

1. memory module control device comprises:

One storage control device is in order to control the access of at least one storer;

One first, 1 second and 1 the 3rd slot, have a signal input part and a signal output part respectively, this signal output part of this first slot is couple to this signal input part of this second slot, this signal output part of this second slot is couple to this signal input part of the 3rd slot, and this first, this second with the 3rd slot form a tandem junction structure, this signal input part of this first slot then is couple to this storage control device;

One traffic pilot has one first, 1 second and 1 the 3rd input end and an output terminal, this first, this second with the output terminal of the 3rd slot also be couple to respectively this traffic pilot this first, this second with the 3rd input end;

One end device is couple to this output terminal of this traffic pilot; And

One automatic testing circuit, in order to detect this first, this second with the user mode of the 3rd slot, to export the input end of a status signal to this traffic pilot, in order to select this first, this second with one of them of this signal output part of the 3rd slot so that output signal is sent to this end device.

2. memory module control device as claimed in claim 1, wherein this end device also comprises:

One terminal organ is couple to this output terminal of this traffic pilot; And

One time clock generator is couple to this output terminal of this traffic pilot, in order to produce a frequency of operation.

3. memory module control device as claimed in claim 2, wherein this gate generator produces the high-frequency signal that a frequency is 400MHz.

4. memory module control device as claimed in claim 1, wherein this first, this second with the 3rd slot between be connected in series, between the input end of this signal output part and this traffic pilot couple and this first slot and this Memory Controller between to couple be to finish with an interface bus.

5. memory module control device as claimed in claim 4, wherein this interface bus is the bus that satisfies direct Rambus channel specifications.

6. memory module control device as claimed in claim 1, wherein this first, this second with the 3rd slot be as satisfying the memory module of direct Rambus storer specification.

7. memory module control device comprises:

One storage control device is in order to control the access of at least one storer;

One first, one second and one the 3rd slot, this is first years old, this second with the 3rd slot have a signal input part and signal output part respectively, and a time clock input end and a time clock output terminal, wherein this signal output part of this first slot is couple to this signal input part of this second slot, this signal output part of this second slot is couple to this signal input part of the 3rd slot, and this clock pulse input terminal of this first slot is couple to this clock pulse input terminal that this storage control device and this output terminal of clock pulse are couple to this second slot;

One traffic pilot has one first and one second input end and an output terminal, and this output terminal is couple to this output terminal of clock pulse of this second slot, and this first input end is couple to the clock pulse input terminal of the 3rd slot;

One first end device is couple to this signal output part of the 3rd slot;

One second end device is couple to the output terminal of clock pulse of the 3rd slot and second input end of this traffic pilot; And

One automatic testing circuit, in order to detect this second with the user mode of the 3rd slot, exporting a status signal to this traffic pilot,

When this status signal judges that a virtual memory module is inserted in this second slot, this traffic pilot just selects this second input end of this traffic pilot to be connected to this output terminal of this traffic pilot, and when this status signal judged that a virtual memory module is inserted in the 3rd slot, this traffic pilot just selected this first input end of this traffic pilot to be connected to this output terminal of this traffic pilot.

8. memory module control device as claimed in claim 7, wherein this first end device is a data bus terminal device.

9. memory module control device as claimed in claim 7, wherein this first, this second with the 3rd slot between be connected in series, and coupling between this first slot and this Memory Controller is to finish with an interface bus.

10. memory module control device as claimed in claim 9, wherein this interface bus is the bus that satisfies direct Rambus channel specifications.

11. a memory module control device comprises:

One storage control device is in order to control the access of at least one storer;

A plurality of slots, each described slot has a signal input part and a signal output part, this signal output part of this slot of previous stage is couple to this signal input part of this slot of back one-level, described slot forms a tandem junction structure, and this signal input part outstanding person of first slot in the described slot is couple to this storage control device;

One traffic pilot has a plurality of input ends and an output terminal, also man-to-man respectively each the described input end that is couple to this traffic pilot of this output terminal of each described slot;

One end device is couple to this output terminal of this traffic pilot; And

One automatic testing circuit, be couple to each described slot, in order to detect the user mode of each described slot, to export the input end of a status signal to this traffic pilot, in order to the described input end institute input signal of selecting this traffic pilot one of them, make one of them output signal of described slot be sent to this end device.

12. memory module control device as claimed in claim 11, wherein this end device also comprises:

One terminal organ is couple to this output terminal of this traffic pilot; And

One time clock generator is couple to this output terminal of this traffic pilot, in order to produce a frequency of operation.

13. memory module control device as claimed in claim 12, wherein this gate generator produces the high-frequency signal that a frequency is 400MHz.

14. memory module control device as claimed in claim 11, between the described input end of the serial connection of wherein said slot, the signal output part of described slot and this traffic pilot couple and this first slot and this Memory Controller between to couple be to finish with an interface bus.

15. memory module control device as claimed in claim 14, wherein this interface bus is the bus that satisfies direct Rambus channel specifications.

16. memory module control device as claimed in claim 11, wherein said slot are as the memory module that satisfies direct Rambus storer specification.

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