CN100384068C - Driving circuit for DC/DC converter and voltage level shifting method thereof - Google Patents

Abstract

A driving circuit for a DC/DC converter and a voltage level converting method thereof, the driving circuit comprising: an input terminal for receiving an input of a Pulse Width Modulation (PWM) signal; a first output end connected to the main switch for outputting a low-end driving signal; a second output end connected to the active switch for outputting a high-end driving signal; a first branch formed by a voltage level shift capacitor and a first buffer connected in series between the input terminal and the second output terminal; and a second branch formed by a delay circuit and a second buffer connected in series between the input terminal and the first output terminal; wherein when the input of the PWM signal rises from a low potential to a high potential, the voltage level transfer capacitor transfers the input of the PWM signal to the first buffer for turning off the active switch and then triggers the second buffer after a delay time to turn on the main switch.

Description

Driving circuit for DC/DC converter and its voltage level shifting method

technical field

The invention relates to a power supply system, in particular to a driving circuit for a DC/DC converter and a voltage level transfer method thereof.

Background technique

A high-side and low-side converter has been widely used to drive the switch bridge of bridge converters, such as active clamp feed-forward converters , half-bridge converters, and full-bridge converters. Figure 1 is a circuit diagram of a conventional active clamp feed-forward converter with a driver IC, in which the low-side switch S1 (main switch) is configured on the primary side of a transformer T, and an active clamp branch Connected in parallel to the primary side coil of the transformer T, the active clamping branch is composed of a high-side switch (active switch) S2 and a clamping capacitor C11 connected in series, wherein the low-side switch S1 and the high-side switch S2 operate complementary to each other to A switch bridge arm is formed, and a high-side and low-side driver IC1 is used to drive the switch bridge arm.

At present, the high-side driver and the low-side driver are usually integrated on one chip. Figure 2 shows a common design method. In this known driver IC, two input signals Hin and Lin are required. The signal Lin is used to trigger a PWM signal of the low-end drive circuit 3, and the other input signal Hin is an inverse signal of the PWM signal, which is used to trigger the high-end drive circuit 2. Through the control of the inverse signal of the PWM signal, the two A high-voltage-rate switch M1 and M2 can be used to achieve voltage level shifting of the high-side driver 1, however the use of high-voltage-rate switches M1 and M2 has several disadvantages; firstly, the switching losses of these switches especially at high switching frequencies are very large, and the switches M1 and M2 are packaged in the driver IC, which increases the complexity of the process. Third, these high voltage rate switches increase the cost of the driver. In addition, in order to facilitate smooth driving of the high-side switches S2 and For the low-side switch S1, it is necessary to use a dead-time setting circuit to generate two complementary signals with effective dead-time. It is well known that the ability to supply current (source current) and sink current (sink current) is An important factor in weighing a driving circuit, in most driving ICs, the ability to source and sink current is limited to slow down the turn-on and turn-off of switching components in a large power converter and reduce the efficiency of the converter, therefore, it is necessary to add an additional snubber circuit.

In view of the bottlenecks in the above-mentioned known technologies, the driving circuit for DC/DC converters of the present invention is invented, which is composed of some simple discrete circuits and integrated on one chip. The driving circuit provides a low Low-cost high-side and low-side drivers can overcome the shortcomings of the known technology. The following is a brief description of the invention.

Contents of the invention

The first object of the present invention is to drive a high-side switch and a low-side switch in a DC/DC converter through a PWM input signal.

The second object of the present invention is to shift the voltage level of the high-side driver through a simple circuit.

The third object of the present invention is to achieve an adjustable static time setting function to avoid potential cross-conduction between the high-side and low-side switches.

The fourth objective of the present invention is to achieve a sufficient capability of supplying current and sinking current to increase the switching speed of the high-side switch and the low-side switch.

A fifth object of the present invention is to provide a driving circuit for a DC/DC converter with a simple structure and a low-cost driving method.

The sixth object of the present invention is to provide a high-side and low-side driving circuit for a DC/DC converter, the driving circuit has a voltage level shift capacitor, a time delay circuit, a low-side driving buffer, and a High side drive buffer.

In order to achieve the above object, the present invention provides a driving circuit for a switch bridge arm of a DC/DC converter, the switch bridge arm includes a main switch and an active switch connected in series, the active switch and the Complementary operation of the main switches, the drive circuit consists of:

an input terminal for receiving an input of a pulse width modulation (PWM) signal;

a first output end, connected to the main switch, the first output end is used to output a low-end driving signal;

A second output terminal connected to the active switch, the second output terminal is used to output a high-side driving signal;

a first branch formed by connecting a voltage level shift capacitor and a first buffer in series between the input terminal and the second output terminal; and

A second branch is composed of a delay circuit and a second buffer connected in series between the input terminal and the first output terminal;

Wherein, when the input of the PWM signal drops from a high potential to a low potential, the input of the PWM signal is sent to the second buffer through the delay circuit to turn off the main switch, and then triggering the first buffer to turn on the active switch, and when the input of the PWM signal rises from the low potential to the high potential, the voltage level shift capacitor transmits the input of the PWM signal to the first a buffer for turning off the active switch, and then triggering the second buffer to turn on the main switch after a delay time.

The above drive circuit for a switching bridge arm of a DC/DC converter, wherein the DC/DC converter is selected from an active clamp feed-forward converter, an active clamp flyback converter, an active clamp One of a clamped feed-forward-flyback converter, a boost converter, and a boost half-bridge converter.

The above driving circuit for a switching bridge arm of a DC/DC converter, wherein the delay circuit is a rising edge delay circuit, comprising:

A switch includes an emitter terminal connected to the input terminal, a collector terminal connected to an output of the delay circuit, and a base connected to a voltage source and ground via a first resistor and a second resistor, respectively. extreme;

a capacitor coupled between the base terminal and the emitter terminal of the switch; and

A diode includes an anode terminal connected to the collector terminal and a cathode terminal connected to the emitter terminal of the switch.

The above drive circuit for a switch bridge arm of a DC/DC converter, wherein the switch is a PNP transistor.

The above driving circuit for a switching bridge arm of a DC/DC converter, wherein the second buffer includes:

an NPN transistor; and

A PNP transistor, wherein the NPN transistor and the two emitter terminals of the PNP transistor are connected to the first output terminal, and the NPN transistor and the two base terminals of the PNP transistor are connected to an output terminal of the delay circuit.

The above drive circuit for a switching bridge arm of a DC/DC converter, wherein the first buffer includes:

a terminal connected to a source terminal of the active switch;

a first diode and a second diode connected in series with each other and coupled with a capacitor between a voltage source and the terminal to jointly form a boost suppression circuit;

a first transistor comprising a collector terminal connected to one end of the capacitor, a base terminal connected to the collector terminal via a resistor, and an emitter terminal connected to a gate terminal of the active switch;

a second transistor including a base terminal connected to the voltage level shifting capacitor via a current limiting resistor, a collector terminal connected to the base terminal of the first transistor, and an emitter terminal connected to the terminal; as well as

a third diode and a fourth diode, which are connected inversely to each other between the base terminal and the emitter terminal of the first transistor, and between the base terminal and the emitter terminal of the second transistor, respectively between extremes.

In the above driving circuit for a switch arm of a DC/DC converter, the first transistor and the second transistor are both NPN transistors.

The above drive circuit for a switching bridge arm of a DC/DC converter, wherein the first buffer includes:

a first terminal connected to a source terminal of the active switch;

a first diode and a second diode, which are connected in series with each other and coupled with a first capacitor between a voltage source and the first end, jointly forming a boost suppressing circuit;

a first transistor comprising a collector emitter terminal connected to one end of the capacitor, a base terminal connected to the emitter terminal via a third diode, and a gate terminal connected to the active switch collector terminal;

a second terminal connected to a drain terminal of the active switch;

a fourth diode and a fifth diode connected in series between a cathode of the first diode and the second end;

a second capacitor, including one terminal connected to the base terminal of the first transistor and the other terminal connected to a cathode terminal of the fourth diode;

a second transistor comprising a base terminal connected to the voltage level shifting capacitor via a current limiting resistor, a collector terminal connected to the gate terminal of the active switch, and a collector terminal connected to the first terminal emission extremes; and

A sixth diode connected between the base terminal and the emitter terminal of the second transistor.

In the aforementioned driving circuit for a switching bridge arm of a DC/DC converter, the first transistor is a PNP transistor, and the second transistor is an NPN transistor.

The present invention also provides an active clamp DC/DC converter, including:

a transformer;

a main switch connected in series to the primary side of the transformer;

an active clamping branch connected in parallel to the primary side of the transformer and comprising an active switch and a clamping capacitor, the active switch is complementary to the main switch, and the active switch and the clamping capacitor are connected in series connection; and

A drive circuit, including:

an input terminal for receiving an input of a pulse width modulation (PWM) signal;

a first output end, connected to the main switch, the first output end is used to output a low-end driving signal;

A second output terminal connected to the active switch, the second output terminal is used to output a high-side driving signal;

a first branch formed by connecting a voltage level shift capacitor and a first buffer in series between the input terminal and the second output terminal; and

A second branch is composed of a delay circuit and a second buffer connected in series between the input terminal and the first output terminal;

Wherein, when the input of the PWM signal drops from a high potential to a low potential, the input of the PWM signal is sent to the second buffer through the delay circuit to turn off the main switch, and then triggering the first buffer to turn on the active switch, and when the input of the PWM signal rises from the low potential to the high potential, the voltage level shift capacitor transmits the input of the PWM signal to the first a buffer for turning off the active switch, and then triggering the second buffer to turn on the main switch after a delay time.

The present invention also provides a voltage level transfer method used in a drive circuit of a switch bridge arm of a DC/DC converter, the switch bridge arm includes a main switch and an active switch connected in series, the active switch The source switch operates complementary to the main switch. The drive circuit includes a first branch and a second branch. The first branch is connected in series to an input terminal and a second by a voltage level shift capacitor and a first buffer. Formed between the output terminals, the second branch is composed of a delay circuit and a second buffer connected in series between the input terminal and a first output terminal, the voltage level shifting method includes the following steps:

receiving an input of a PWM signal;

When the input of the PWM signal drops from a relatively high potential to a relatively low potential, the input of the PWM signal is sent to the second buffer through the delay circuit to turn off the main switch, and then trigger the a first buffer to turn on the active switch; and

When the input of the PWM signal rises from the relatively low potential to the relatively high potential, the input of the PWM signal is sent to the first buffer for turning off the active switch, and then after a delay time triggering the second buffer to turn on the main switch.

The above voltage level shifting method also includes the following steps:

receiving the input of the pulse width modulated signal at the input terminal;

outputting a low-end drive signal at the first output terminal; and

A high-end driving signal is output at the second output end.

The present invention can be understood more deeply through the following drawings and detailed description.

Description of drawings

Fig. 1 is a circuit diagram of a high-side and low-side driver IC conventionally applied to an active clamp feed-forward DC/DC converter;

Fig. 2 is the circuit diagram of the general design mode of high-end and low-end driver of the present invention;

Fig. 3 is a circuit block diagram of a preferred embodiment of a high-side and low-side drive circuit applied to an active clamp feed-forward converter of the present invention;

Fig. 4 is the circuit diagram of the rising edge delay circuit of an embodiment of the static time setting circuit of the present invention;

FIG. 5(A) is a circuit diagram of an embodiment of the high-side driving circuit of the present invention, which is used to drive the high-side switch;

FIG. 5(B) is a circuit diagram of another embodiment of the high-side drive circuit of the present invention, which is used to drive the high-side switch;

6 is an overall circuit diagram of a preferred embodiment of a high-side and low-side drive circuit applied to an active clamp feed-forward converter of the present invention;

7 is an overall circuit diagram of another preferred embodiment of the present invention applied to a high-side and low-side drive circuit of an active clamp feed-forward converter;

Fig. 8 is a circuit block diagram of a preferred embodiment of a high-side and low-side drive circuit applied to an active clamp flyback converter of the present invention;

Fig. 9 is a circuit block diagram of a preferred embodiment of a high-side and low-side drive circuit applied to an active clamp feed-forward-flyback converter of the present invention;

Fig. 10 is a circuit block diagram of a preferred embodiment of a high-side and low-side driving circuit applied to a boost converter of the present invention; and

FIG. 11 is a circuit block diagram of a preferred embodiment of the present invention applied to a high-side and low-side driving circuit of a boost half-bridge converter.

In the picture:

1 high-side driver

2 high-end drive circuit

3 low-end drive circuit

C1 voltage level shift capacitor

C11 clamp capacitor

C10, C11, C21, C31, C32 capacitors

D1, D2, D10, D31, D32 diodes

D33, D34, D36, D37, D38 diodes

Hin input signal

Lin input signal

L1, Lb inductance

M1, M2 high voltage rate switch

Q1, Q3, Q4, Q5, Q6 transistors

R10, R11, R31, R32, R33, R51 resistors

S1 low side switch

S2 high side switch

T-transformer

Vcc voltage source

Detailed ways

The drive circuit of the present invention is used to drive a switch bridge arm of a DC/DC converter, wherein the DC/DC converter can be an active clamp feedforward converter, an active clamp flyback converter, an active clamp flyback converter, active clamp feed-forward-flyback converter, a boost converter, or a boost half-bridge converter, the switching arm of the DC/DC converter consists of a main switch (a low-side switch) and a The active switch (a high-side switch) is connected in series. The active switch and the main switch operate in a complementary manner. A driving circuit applied to an active clamp feed-forward converter will be described in detail below.

Please refer to FIG. 3 , which is a circuit block diagram of a preferred embodiment of the present invention applied to a high-side and low-side driving circuit of an active clamp feed-forward converter. In this converter, a low-side switch S1 is connected in series to the primary side of a transformer T, and an active clamping branch is connected in parallel to the primary side of the transformer T. The active clamping branch includes a high-side switch S2 connected in series with each other and a clamp capacitor C11, the drive circuit 11 has three ports, the first port is a drive signal input port 1 for receiving a PWM signal, and the second port is a low-side drive output port connected to the low-side switch S1 2. The third port is a high-side drive output port 3 connected to the high-side switch S2. The drive circuit 11 has two branches, one branch is the low end between port 1 and port 2, which is composed of a rising edge delay circuit and A series circuit composed of a buffer A, and the other branch is a series circuit composed of a voltage level shifting capacitor C1 and a buffer B between ports 1 and 3 at the high end, where the low-side switch S1 and high side switch S2 operate in a complementary manner.

The basic driving principle of the driving circuit is as follows:

Assuming that the PWM signal is at a high level, and the low-side switch S1 is turned on and the high-side switch is turned off, when the PWM signal decreases to a low level, the signal is immediately sent to the buffer A through the delay circuit, and the low-side switch S1 is turned off. Buffer A is turned off, the output capacitance of the low-side switch S1 is charged by the magnetizing current, and the voltage across the low-side switch S1 rises rapidly. This voltage rise signal is immediately reflected on the buffer B and triggers the high-side driver to Turn on switch S2.

When the PWM signal becomes a high potential, the capacitor C1 transmits this signal to the buffer B and immediately triggers the buffer B to close the high-side switch S2. In order to avoid the potential mutual conduction between the switches S1 and S2, the PWM signal is delayed by the delay circuit A short time and then after closing switch S2 triggers buffer A to open switch S1.

FIG. 4 is a circuit diagram of a rising edge delay circuit of an embodiment of the static time setting circuit used in the driving circuit according to the present invention. Port 1 is connected to an input terminal of the PWM signal, port 4 is connected to a voltage source Vcc, and port 5 is connected to ground, and the PNP transistor includes an emitter terminal connected to the PWM signal, a collector terminal connected to the output of the delay circuit, and a base terminal respectively connected to the voltage source and ground via the resistor R10 and the resistor R11, the capacitor C10 is coupled between the base terminal and the emitter terminal of the transistor Q1, the anode terminal of the diode D10 is connected to the collector terminal of the transistor Q1, and The cathode terminal is connected to the emitter terminal of the transistor Q1.

When the PWM signal is low, transistor Q1 is held in the OFF state because a positive voltage is coupled across capacitor C10 and applied between the emitter and base terminals of transistor Q1. When the PWM signal goes high, capacitor C10 Then, through the discharge of resistors R10 and R11, the transistor Q1 is turned on until the positive voltage across the capacitor C10 is discharged to a negative voltage. Therefore, a short period of turn-on delay can be obtained between the output terminal and the input terminal of the delay circuit, The delay time can be set by the capacitance value of capacitor C10 and the resistance values of resistors R10 and R11. When the PWM signal drops to a low level, the signal is directly transmitted through the diode D10 without any delay function for the off time.

Figure 5(A) is a circuit diagram of an embodiment of the high-end drive circuit of the present invention, which is composed of a capacitor C1 and a buffer circuit B, the capacitor C1 can achieve the voltage level shift function, one end of the capacitor C1 is connected to the PWM input signal, and the capacitor The other end of C1 is connected to the buffer circuit B, and the port 6 of the buffer circuit B is connected to the source terminal of the switch S2, and the boost trap circuit (boost trap circuit) composed of series connected diodes D31 and D34 and capacitor C31 is coupled to Between the voltage source Vcc and the port 6, the PNP transistor Q5 includes a collector terminal connected to the first terminal of the capacitor C31, a base terminal connected to the collector terminal via a resistor R31, and a gate connected to the high-side open terminal ( gate) terminal, another PNP transistor Q6 includes a base terminal connected to the capacitor C1 via a current limiting resistor R32, a collector terminal connected to the base terminal of the transistor Q5, and an emitter terminal connected to the port 6 Diodes D32 and D33 are connected in antiparallel between the base terminals and emitter terminals of transistors Q5 and Q6 respectively. These components form a basic high-side drive circuit. When the switch S2 is in the OFF state, it is connected to port 12 and the boost suppression diode Resistor R33 between D31 provides a constant bias current to transistor Q6.

When the PWM voltage is very low and the switch S1 is in the OFF state, a high voltage appears at port 6, which keeps the transistor Q6 in the OFF state through the conduction of the diode D33, and the voltage between the gate and the source of the switch S2 can pass through Transistor Q5 is established, which can turn on switch S2. When the PWM signal turns from low potential to high potential, the signal is transmitted to the base terminal of transistor Q6 through capacitor C1 and resistor R32, and transistor Q6 is turned on immediately. Soon the switch The gate capacitance of S2 is discharged through diode D32 and transistor Q6, and transistor Q5 and switch S2 are turned off. When switch S1 is turned on, transistor Q6 is kept in the ON state by a bias current from Vcc And through diode D31, resistors R33 and R32, transistor Q6, and switch S1 in sequence, until the base terminal of transistor Q6, switch S2 is kept in the OFF state because its gate voltage is clamped at a low potential, and the voltage of capacitor C1 It is discharged to a low potential through resistor R32, transistor Q6 and switch S1. In addition, capacitor C1 and resistor R32 constitute an RC snubber of switch S2.

FIG. 5(B) is a circuit diagram of another embodiment of the high-side driving circuit of the present invention, which is used to drive the switch S2. Compared with the high-side drive circuit of Fig. 5(A), the only difference is the charging circuit of the switch S2, the resistor R31 and the diode D32 are removed, and the transistor Q5 is replaced by a PNP transistor including a capacitor connected to An emitter terminal of the first terminal of C31, a base terminal connected to the emitter terminal via a diode D36, and a collector terminal connected to the gate of the switch S2, port 7 is the drain terminal of the high-side switch S2, diodes D38 and D37 It is connected in series between the cathode terminal of the diode D31 and the terminal 7, and the capacitor C32 is connected between the base terminal of the transistor Q5 and the cathode terminal of the diode D38.

When the PWM signal is high potential and the low-side switch S1 is in the ON state, the voltage across the capacitor C32 is 0 and the diode D37 is in the OFF state due to a reverse voltage. During this period, the transistor Q5 is OFF and the transistor Q6 is ON. When the PWM signal turns to low potential, the low-side switch S1 is turned off, and the voltage of port 6 rises. When the voltage of port 6 is the same as that of port 7, the diode D37 is turned on, and the transistor Q5 flows through the capacitor C32 and the diode due to a bias current. D37 is turned on, the switch S2 is turned on, the voltage between the gate and source of the switch S2 and the voltage of the capacitor C32 are charged to Vcc, the transistor Q5 is immediately turned off, and the voltage between the gate and the source of the switch S2 is kept at Vcc, when PWM When the signal turns to a high potential, the switch S1 is turned on, and the capacitor C32 is discharged to 0 through the diodes D38 and D36. Other operations are the same as the driver in FIG. 5(A), which provides zero-voltage switching conduction to the switch S2.

Fig. 6 is an overall circuit diagram of a preferred embodiment of a high-side and low-side drive circuit applied to an active clamp feed-forward converter of the present invention, the circuit of Fig. 6 is derived from the circuit of Fig. 2, wherein the isolation delay time The circuit is replaced by the rising edge delay circuit of Figure 4, the isolation of buffer circuit A is replaced by transistors Q3 and Q4, and the isolation of buffer circuit B is replaced by the circuit of Figure 5(A).

7 is an overall circuit diagram of another preferred embodiment of the present invention applied to a high-side and low-side drive circuit of an active clamp feed-forward converter. Compared with FIG. 6, it removes the transistor Q3 and adds The resistor R51 connected in parallel to the base terminal and the emitter terminal of the transistor Q4 makes the driving circuit of FIG. 7 a simplified circuit. In addition, the anode terminal of the diode D10 is connected to the base terminal of the transistor Q4. The switch S1 is activated by the PWM signal via the transistor Q1 with a delay time, and when the PWM signal turns to a low potential, the gate capacitance of the switch S1 is discharged via the transistor Q4.

However, those skilled in the art can easily understand that the driving circuit of the present invention can also be applied to other switching bridge arm topologies of other DC/DC converters. Fig. 8 is a circuit block diagram of a preferred embodiment of the present invention applied to a high-side and low-side driving circuit of an active clamp flyback converter, and Fig. 9 is a circuit block diagram of the present invention applied to an active clamp feedforward- A circuit block diagram of a preferred embodiment of a high-side and low-side driving circuit of a flyback converter, FIG. 10 is a diagram of a preferred embodiment of the present invention applied to a high-side and low-side driving circuit of a boost converter Circuit block diagram, Fig. 11 is then the circuit block diagram of a preferred embodiment of a high-end and low-end driving circuit applied to a step-up half-bridge converter of the present invention; These changes are not used to limit the scope of the present invention's implementation, That is, all modifications made according to the concept of the present invention belong to the scope of the patent application of the present invention.

Claims (12)

1. A drive circuit for a switching bridge arm of a DC/DC converter, the switching bridge arm comprising a main switch and an active switch connected in series, the active switch operating in complement to the main switch, the The drive circuit includes: an input terminal for receiving an input of a pulse width modulation signal; a first output end, connected to the main switch, the first output end is used to output a low-end driving signal; A second output terminal connected to the active switch, the second output terminal is used to output a high-side driving signal; a first branch formed by connecting a voltage level shift capacitor and a first buffer in series between the input terminal and the second output terminal; and A second branch is composed of a delay circuit and a second buffer connected in series between the input terminal and the first output terminal; Wherein, when the input of the pulse width modulation signal drops from a high potential to a low potential, the input of the pulse width modulation signal is sent to the second buffer through the delay circuit for turning off The main switch, and then trigger the first buffer to turn on the active switch, and when the input of the PWM signal rises from the low level to the high level, the voltage level shift capacitor transmits the The input of the PWM signal to the first buffer is used to turn off the active switch, and then triggers the second buffer to turn on the main switch after a delay time. 2. The driving circuit as claimed in claim 1, wherein the DC/DC converter is selected from an active clamp feedforward converter, an active clamp flyback converter, an active clamp feedforward-flyback converter One of a gallop converter, a boost converter, and a boost half-bridge converter. 3. The driving circuit as claimed in claim 1, wherein the delay circuit is a rising edge delay circuit, comprising: A switch includes an emitter terminal connected to the input terminal, a collector terminal connected to an output of the delay circuit, and a base connected to a voltage source and ground via a first resistor and a second resistor, respectively. extreme; a capacitor coupled between the base terminal and the emitter terminal of the switch; and A diode includes an anode terminal connected to the collector terminal and a cathode terminal connected to the emitter terminal of the switch. 4. The driving circuit as claimed in claim 3, wherein the switch is a PNP transistor. 5. The driving circuit as claimed in claim 1, wherein the second buffer comprises: an NPN transistor; and A PNP transistor, wherein the NPN transistor and the two emitter terminals of the PNP transistor are connected to the first output terminal, and the NPN transistor and the two base terminals of the PNP transistor are connected to an output terminal of the delay circuit. 6. The driving circuit as claimed in claim 1, wherein the first buffer comprises: a terminal connected to a source terminal of the active switch; a first diode and a second diode connected in series with each other and coupled with a capacitor between a voltage source and the terminal to jointly form a boost suppression circuit; a first transistor comprising a collector terminal connected to one end of the capacitor, a base terminal connected to the collector terminal via a resistor, and an emitter terminal connected to a gate terminal of the active switch; a second transistor including a base terminal connected to the voltage level shifting capacitor via a current limiting resistor, a collector terminal connected to the base terminal of the first transistor, and an emitter terminal connected to the terminal; as well as a third diode and a fourth diode, which are connected inversely to each other between the base terminal and the emitter terminal of the first transistor, and between the base terminal and the emitter terminal of the second transistor, respectively between extremes. 7. The driving circuit as claimed in claim 6, wherein both the first transistor and the second transistor are NPN transistors. 8. The driving circuit as claimed in claim 1, wherein the first buffer comprises: a first terminal connected to a source terminal of the active switch; a first diode and a second diode, which are connected in series with each other and coupled with a first capacitor between a voltage source and the first end, jointly forming a boost suppressing circuit; a first transistor comprising an emitter terminal connected to one end of the capacitor, a base terminal connected to the emitter terminal via a third diode, and a collector terminal connected to a gate terminal of the active switch ; a second terminal connected to a drain terminal of the active switch; a fourth diode and a fifth diode connected in series between a cathode of the first diode and the second end; a second capacitor, including one terminal connected to the base terminal of the first transistor and the other terminal connected to a cathode terminal of the fourth diode; a second transistor comprising a base terminal connected to the voltage level shifting capacitor via a current limiting resistor, a collector terminal connected to the gate terminal of the active switch, and a collector terminal connected to the first terminal emission extremes; and A sixth diode connected between the base terminal and the emitter terminal of the second transistor. 9. The driving circuit as claimed in claim 8, wherein the first transistor is a PNP transistor, and the second transistor is an NPN transistor. 10. An active clamp DC/DC converter comprising: a transformer; a main switch connected in series to the primary side of the transformer; an active clamping branch connected in parallel to the primary side of the transformer and comprising an active switch and a clamping capacitor, the active switch is complementary to the main switch, and the active switch and the clamping capacitor are connected in series connection; and A drive circuit, including: an input terminal for receiving an input of a pulse width modulation signal; a first output end, connected to the main switch, the first output end is used to output a low-end driving signal; A second output terminal connected to the active switch, the second output terminal is used to output a high-side driving signal; a first branch formed by connecting a voltage level shift capacitor and a first buffer in series between the input terminal and the second output terminal; and A second branch is composed of a delay circuit and a second buffer connected in series between the input terminal and the first output terminal; Wherein, when the input of the pulse width modulation signal drops from a high potential to a low potential, the input of the pulse width modulation signal is sent to the second buffer through the delay circuit for turning off The main switch, and then trigger the first buffer to turn on the active switch, and when the input of the PWM signal rises from the low level to the high level, the voltage level shift capacitor transmits the The input of the PWM signal to the first buffer is used to turn off the active switch, and then triggers the second buffer to turn on the main switch after a delay time. 11. A voltage level shifting method used in a drive circuit of a switch bridge arm of a DC/DC converter, the switch bridge arm comprising a main switch and an active switch connected in series, the active switch Complementary operation with the main switch, the drive circuit includes a first branch and a second branch, the first branch is connected in series to an input terminal and a second output terminal by a voltage level shift capacitor and a first buffer The second branch is composed of a delay circuit and a second buffer connected in series between the input terminal and a first output terminal. The voltage level shifting method includes the following steps: receiving an input of a pulse width modulated signal; When the input of the PWM signal drops from a relatively high potential to a relatively low potential, the input of the PWM signal is sent to the second buffer through the delay circuit to turn off the main switch, and then trigger the first buffer to turn on the active switch; and when the input of the pulse width modulation signal rises from the relatively low potential to the relatively high potential, transmitting the input of the pulse width modulation signal to the first buffer for turning off the active switch, and Then trigger the second buffer to turn on the main switch after a delay time. 12. The voltage level shifting method as claimed in claim 11, further comprising the steps of: receiving the input of the pulse width modulated signal at the input terminal; outputting a low-end drive signal at the first output terminal; and A high-end driving signal is output at the second output terminal.

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