CN100382280C - Wafer Dicing Method - Google Patents

Abstract

The present invention provides a wafer cutting method. First, a device wafer is provided, and the device wafer includes a substrate layer and a device layer in order from bottom to top. Then, a first mask pattern is used to remove the device layer that is not protected by the first mask pattern. Then, an intermediate layer is formed on the surface of the device layer, and the surface of the intermediate layer is attached to a carrier wafer. Then, a second mask pattern is used to remove the substrate layer that is not protected by the second mask pattern. Finally, the intermediate layer is separated from the carrier wafer, and the substrate layer is attached to an expansion film, and the intermediate layer is removed at the same time.

Description

Wafer Dicing Method

technical field

The invention relates to a wafer cutting method, in particular to a wafer cutting method which can directly perform automatic expansion and crystal picking after the wafer is cut.

Background technique

After the wafer has undergone dozens to hundreds of semiconductor processes to produce multiple integrated circuits or micro-electromechanical structures arranged in an array, the wafer will be cut into multiple dies by dicing process for subsequent packaging process, and then produce a chip (chip) that can be electrically connected to a circuit board.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a known cutting process using a cutting machine. As shown in FIG. 1 , the device wafer 10 to be diced is attached to an expansion film 12 , such as an adhesive tape, and the expansion film 12 is simultaneously adhered to a supporting frame 14 , thereby fixing the position of the device wafer 10 . After the dicing machine completes the alignment of the device wafer 10 , it uses the dicing knife 16 to cut the device wafer 10 into a plurality of dies 18 according to a preset scribe line. Wherein, after forming a plurality of dies 18 , the wafer expansion process can be performed depending on the line width of the dicing line, that is, the distance between the dies 18 is enlarged by stretching the expansion film 12 , so as to facilitate the subsequent die picking process.

The above-mentioned method of using the dicing knife 16 of the dicing machine to perform the cutting process is the most widely used cutting method at present. However, when the number of dies disposed on the surface of the device wafer 10 is too large, the method of using the dicing knife 16 to perform the cutting process will be seriously reduced. Throughput. In addition, since the dicing knife 16 has a certain width, the dicing process using the dicing knife 16 is likely to cause chipping at the edge of the die 18 as the line width of the semiconductor process gradually decreases and the integration level of the wafer increases. Therefore, the method of performing the cutting process by etching is another choice of the current cutting process.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a known cutting process using etching. As shown in Figure 2, at first, a device wafer 30 is provided, and the device wafer 30 is attached on a support carrier 34 by using an adhesive layer 32, and the surface of the device wafer 30 includes a light beam for defining a scribe line pattern. A resist pattern 36 is formed. An anisotropic etching process is then performed to remove the device wafer 30 not covered by the photoresist pattern 36 until the device wafer 30 is etched through to form a plurality of dies 38 .

Another method in the prior art utilizes etching to carry out the cutting process, which can reduce the line width of the dicing line and increase the number of die configurations on the surface of the device wafer 30. However, since the support carrier 34 is a rigid object, such as a carrier wafer, When the line width of the dicing line becomes narrower, the subsequent crystal picking process cannot be carried out smoothly after the dicing process is completed, so the aforementioned chip expansion process cannot be used to directly stretch the adhesive layer 32 to make the die 38 Increased spacing. In this case, the current known method is to remove the photoresist pattern 36 on the surface of the die 38, and remove the adhesive layer 32 to separate the die 38 from the supporting carrier 34, and then pick up the die manually. In this way, the production capacity will be seriously affected, and the good rate may be reduced due to damage to the die 38 due to human factors.

In view of this, the applicant intends to provide a wafer dicing method, which can be applied to dicing and the subsequent automatic wafer expansion and crystal picking process, so as to achieve the purpose of production automation, thereby improving productivity and yield.

Contents of the invention

Therefore, the main purpose of the present invention is to provide a wafer dicing method to overcome the unsolvable problems of the known techniques.

According to a preferred embodiment of the present invention, a wafer dicing method is provided. First, a device wafer is provided, and the device wafer sequentially includes a substrate layer and a device layer from bottom to top. Subsequently, a first mask pattern is formed on the surface of the device layer, and the first mask pattern includes a plurality of first openings exposing part of the surface of the device layer, while removing parts not protected by the first mask pattern the device layer. Then remove the first mask pattern, and form an intermediate layer on the surface of the device layer. Then attach the surface of the intermediate layer on a carrier wafer, and form a second mask pattern on the surface of the substrate layer, the second mask pattern includes a plurality of second openings, and the second openings The position of corresponds to the position of the first opening. Then remove the substrate layer not protected by the second mask pattern, and then remove the second mask pattern. Finally, the intermediate layer is separated from the carrier chip, and the substrate layer is attached to an expansion film, and the intermediate layer is removed at the same time.

Because the wafer cutting method of the present invention uses the intermediate layer to attach the device wafer to the carrier wafer, and performs an anisotropic etching process by the substrate layer, and then transfers the device wafer to the expansion film to facilitate subsequent automatic wafer expansion and picking. The crystallization process is carried out, and the intermediate layer is removed by a dry process, so that the device layer will not be polluted and the expansion film will not be damaged.

In order to enable your examiner to further understand the characteristics and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary description, and are not intended to limit the present invention.

Description of drawings

FIG. 1 is a schematic diagram of a known cutting process using a cutting machine.

FIG. 2 is a schematic diagram of a known cutting process using etching.

3 to 13 are schematic diagrams of a wafer cutting method according to a preferred embodiment of the present invention.

Description of main component symbols

10 Device Wafer 12 Expansion Film

14 Support frame 16 Cutting knife

18 dies 30 device wafers

32 Adhesive layer 34 Supporting vehicle

36 photoresist pattern 38 die

50 Device wafer 52 Substrate layer

54 insulation layer 56 device layer

58 first mask pattern 60 first opening

62 Middle layer 64 Adhesive layer

66 Carrier Wafer 68 Second Mask Pattern

70 Second opening 72 Third opening

74 Expansion Membrane 76 Supporting Frame

Detailed ways

Please refer to Figure 3 to Figure 13. 3 to 13 are schematic diagrams of a wafer cutting method according to a preferred embodiment of the present invention. As shown in FIG. 3 , a device wafer 50 is first provided, and the device wafer 50 includes a substrate layer 52, an insulating layer 54, and a device layer 56 in sequence from bottom to top, wherein the device layer 56 includes a plurality of packages to be cut. device (not shown). In addition, in this embodiment, the device wafer 50 is a silicon-on-insulator (SOI) wafer, but the application of the present invention is not limited thereto, and the device wafer 50 can also be a general semiconductor wafer.

As shown in FIG. 4, a first mask pattern 58 is then formed on the surface of the device layer 56, and the first mask pattern 58 includes a plurality of first openings 60 exposing part of the surface of the device layer 56, wherein the first mask pattern The mold pattern 58 can be a photoresist pattern or other materials that are often used as a hard mask, and the exposed position of the first opening 60 is the position of the predetermined dicing line of the device wafer 50 .

As shown in FIG. 5 , an anisotropic etching process, such as a plasma etching process, is performed to remove the device layer 56 and the insulating layer 54 not protected by the first mask pattern 58 . As shown in FIG. 6 , the first mask pattern 58 is then removed, and an intermediate layer 62 is formed on the surface of the device layer 56 . The intermediate layer 62 serves as a medium for subsequently fixing the device wafer 50 to a carrier wafer, and at the same time protects the device wafer 50 . In addition, since the intermediate layer 62 must be removed in subsequent processes, it is better to choose a material that is easy to remove. In this embodiment, the material of the intermediate layer 62 is selected from benzocyclobutene (BCB), polyimide (polyimide), epoxy resin (epoxy), photoresist and dry film (dry film) etc., and formed on the surface of the device layer 56 by means of coating or sticking at the same time.

As shown in FIG. 7 , an adhesive layer 64 is used to fix the intermediate layer 62 on a surface of a chip carrier 66 . In this embodiment, the adhesive layer 64 is selected from thermal separation tape or ultraviolet tape, etc., wherein the thermal separation tape can be removed by heating, and the ultraviolet tape can be removed by irradiating ultraviolet rays. In addition, the adhesive layer 64 can also use other materials. And use other methods that will not cause damage to the device layer 56 and the intermediate layer 62 to be removed, not limited to the materials listed in this embodiment. The carrier wafer 66 can be selected from general semiconductor wafers, glass wafers or quartz wafers, etc., wherein it is worth noting that if the adhesive layer 64 is made of ultraviolet tape, then the carrier chip 66 needs to use a glass wafer or a quartz wafer with light-transmitting properties, so as to facilitate the follow-up process. Adhesive layer 64 removal. In addition, the method of the present invention may also perform a wafer thinning process at this time to reduce the substrate layer 52 to a proper thickness.

As shown in FIG. 8 , a second mask pattern 68 is formed on the surface of the substrate layer 52 . The second mask pattern 68 includes a plurality of second openings 70 , and the positions of the second openings 70 correspond to the positions of the first openings (not shown). The second mask pattern 68 can be a photoresist pattern or other materials commonly used as a hard mask. It is also worth noting that, as the device types of the device layer 56 are different, the pattern of the second mask pattern 68 can also be adjusted to produce a desired structure. For example, if the device to be cut is a piezoresistive pressure sensing element, the second mask pattern 68 further includes a third opening 72, thereby making a base of the piezoresistive pressure sensing element (stand).

As shown in FIG. 9 , an anisotropic etching process, such as a plasma etching process, is performed to remove the unprotected substrate layer 52 by the second mask pattern 68 . As shown in FIG. 10, the second mask pattern 68 is removed.

As shown in FIG. 11 , the adhesive layer 64 is removed to separate the intermediate layer 62 from the handle wafer 66 . The method of removing the adhesive layer 64 is different depending on the material of the adhesive layer 64 . For example, when the adhesive layer 64 is a heat release tape, the temperature is raised above the separation temperature of the heat release tape by means of heating; The adhesive layer 64 is removed by irradiating ultraviolet rays.

As shown in FIG. 12 , the substrate layer 52 is then attached to an expansion film 74 , and the expansion film 74 is fixed on a support frame 76 . As shown in Figure 13, the intermediate layer 62 is removed from the surface of the device layer 56, wherein the removal of the intermediate layer 62 depends on the material properties and effects, and different methods are used to remove it, and in order to prevent the device layer 56 from being polluted, remove The method for removing the intermediate layer 62 is preferably a dry process, such as using an oxygen plasma cleaning process or a supercritical carbon dioxide cleaning process. According to the wafer dicing method of the present invention, after the substrate layer 52 is attached to the expansion film 74 , the expansion film 74 can be directly used for automatic wafer expansion and crystal picking processes.

As can be seen from the above, the wafer dicing method of the present invention uses the intermediate layer to attach the device wafer to the carrier wafer, so as to perform anisotropic etching process from the substrate layer, and then transfer the device wafer to the expansion film, so as to facilitate subsequent automatic wafer expansion. With the progress of the crystal picking process, the intermediate layer is removed by a dry process at the same time, so that the device layer will not be polluted and the expansion film will not be damaged. In addition, many micro-electromechanical devices, such as pressure sensors (pressure sensor), infrared sensors (IR sensor) and micro-electromechanical microphones (MEMS microphone), etc., all have a suspended structure, and the wafer cutting method of the present invention can easily It is produced when the substrate layer is anisotropically etched. In contrast, the known technology cannot carry out the wafer expansion process after the cutting process is carried out by etching, but must rely on manual methods to pick up the crystal, which greatly affects the process time and production yield. Therefore, the wafer dicing method of the present invention can effectively increase production capacity and reduce the risk of chip damage caused by manual wafer picking.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (16)

1. A wafer cutting method, comprising: A device wafer is provided, and the device wafer sequentially includes a substrate layer and a device layer from bottom to top; forming a first mask pattern on the surface of the device layer, and the first mask pattern includes a plurality of first openings exposing part of the surface of the device layer; removing the device layer not protected by the first mask pattern; removing the first mask pattern, and forming an intermediate layer on the surface of the device layer; attaching the surface of the intermediate layer to a carrier wafer; forming a second mask pattern on the surface of the substrate layer, the second mask pattern includes a plurality of second openings, and the positions of the plurality of second openings correspond to the positions of the first openings; removing the substrate layer not protected by the second mask pattern; removing the second mask pattern; separating the intermediate layer from the handle wafer; and The substrate layer is attached to an expansion film, and the intermediate layer is removed. 2. The method of claim 1, wherein the step of attaching the substrate layer to the expanded membrane is performed prior to the step of removing the intermediate layer. 3. The method of claim 1, wherein the intermediate layer is attached to the carrier wafer by an adhesive layer. 4. The method as claimed in claim 3, wherein the adhesive layer is a thermal release tape. 5. The method of claim 3, wherein the adhesive layer is an ultraviolet tape. 6. The method of claim 1, wherein the step of removing the device layer not protected by the first mask pattern is performed by an anisotropic etching process. 7. The method of claim 6, wherein the anisotropic etching process is a plasma etching process. 8. The method of claim 1, wherein the step of removing the substrate layer not protected by the second mask pattern is achieved by an anisotropic etching process. 9. The method of claim 8, wherein the anisotropic etching process is a plasma etching process. 10. The method of claim 1, wherein the second mask pattern further comprises a plurality of third openings, and the positions of the third openings do not correspond to the positions of the first openings. 11. The method of claim 1, wherein the device wafer further comprises an insulating layer disposed between the substrate layer and the device layer. 12. The method of claim 11, further comprising removing the insulating layer not protected by the first mask pattern at the same time as the step of removing the device layer not protected by the first mask pattern. 13. The method as claimed in claim 1, wherein the material of the intermediate layer is selected from the group consisting of benzocyclobutene, polyimide, epoxy resin, photoresist and dry film. 14. The method of claim 1, wherein the step of removing the intermediate layer is performed by a dry process. 15. The method of claim 14, wherein the dry process is an oxygen plasma cleaning process. 16. The method of claim 14, wherein the dry process is a supercritical carbon dioxide cleaning process.

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