CN100380682C - Contact portion of semiconductor device and manufacturing method thereof, thin film transistor array panel for display device including contact portion and manufacturing method thereof - Google Patents

Abstract

A gate wiring including a gate line, a gate electrode and a gate pad and extending in a lateral direction is formed on the substrate. A gate insulating layer is subsequently formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. A conductive material is deposited and patterned to form data wiring including data lines intersecting the gate lines, source electrodes, drain electrodes, and data pads. A first insulating layer made of silicon nitride is deposited on the substrate, and a second insulating layer made of photosensitive organic insulating material is coated on the first insulating layer. The second insulating layer is patterned to form a convex-concave pattern and a first contact hole opposite to the drain electrode exposing the first insulating layer on a surface thereof. Subsequently, the first insulating layer and the gate insulating layer are patterned together by photolithography using a photoresist pattern to form contact holes exposing the drain electrode, the gate pad, and the data pad, respectively. Next, indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned to form light-transmitting electrodes, sub-gate pads, and sub-gate pads connected to drain electrodes, gate pads, and data pads, respectively. data pad. Finally, a reflective conductive material is deposited on the light-transmitting electrode and patterned to form a reflective film with corresponding holes in the pixel area.

Description

Contact portion of semiconductor device and manufacturing method thereof, thin film transistor array panel for display device including contact portion and manufacturing method thereof

technical field

The invention relates to a contact structure of a semiconductor device and a manufacturing method thereof, a thin film transistor array plate for a display device including a contact structure and a manufacturing method thereof.

Background technique

Generally, a semiconductor device has multilayer wiring interposed between interlayer insulating layers. The interlayer insulating layer is preferably made of a material with a low dielectric constant in order to minimize the interference between signals flowing through different wirings, and through the contact hole provided at the interlayer insulating layer, different wiring layers that transmit the same signal are electrically connected to each other.

The interlayer insulating layer includes an organic insulating layer having a low dielectric constant, which is generally formed by spin coating. When the underlying structure of the organic layer has a steep height difference, the organic layer has a stepped height, which causes the organic material to be localized on specific areas during spin coating. For liquid crystal displays (LCDs), especially for reflective LCDs that display images by reflecting external light and transflective LCDs that operate in both reflective and transmissive modes, this degrades display characteristics.

Currently, LCDs are one of the most widely used flat panel displays. The LCD, which includes two panels having electrodes and a liquid crystal layer interposed therebetween, controls light transmittance through the liquid crystal layer by applying a voltage to the electrodes so that liquid crystal molecules in the liquid crystal layer rearrange. Among these LCDs, the most frequently used one provides at least one electrode on each panel and includes a thin film transistor (TFT) that switches a voltage applied to the electrode.

In general, a panel (TFT array panel) with TFTs includes signal wiring including gate lines transmitting scan signals, data lines transmitting image signals, and gate lines transmitting scan signals from external devices to the gate lines in addition to the TFTs. Gate pads and data pads that transfer image signals from external devices to data lines. The TFT array panel further includes pixel electrodes electrically connected to the TFTs and located in corresponding pixel regions defined by intersections of the gate lines and the data lines.

A pixel electrode of a reflective LCD or a transflective LCD includes a conductive reflective film, which preferably has protrusions for increasing reflection efficiency to improve display performance. The reflective film protrusions are formed by disposing an uneven organic insulating layer under the reflective film.

However, the stepped height of the organic insulating layer due to the steep level difference of the underlying structure gives a poor profile of the unevenness of the organic insulating layer, thus causing non-uniformity of the projection of the reflective film to generate strain.

Contents of the invention

The technical problem to be solved by the present invention is to provide a contact structure of a semiconductor device for improving the shape of an organic insulating layer and a manufacturing method thereof, a TFT array plate including a contact structure and a manufacturing method thereof.

Another technical problem to be solved by the present invention is to simplify the manufacturing method of the TFT array board.

In order to solve these problems, the present invention forms an organic insulating layer pattern exposing the insulating layer, and then forms a contact hole exposing wiring at the exposed portion of the insulating layer. When forming the organic insulating layer, there is no level difference due to the contact hole of the insulating layer.

In detail, the method for manufacturing a contact structure of a semiconductor device according to the present invention includes: forming a first wiring on a substrate, and then forming a first insulating layer covering the first wiring. Next, an organic insulating material is deposited on the first insulating layer and patterned to form a second insulating layer having a first contact hole exposing a portion of the first insulating layer corresponding to the first wiring. Next, a portion of the first insulating layer exposed through the first contact hole is patterned by photolithography using a photoresist pattern to form a second contact hole exposing the first wiring, and then a contact hole through the second contact hole is formed. The second wiring connected to the first wiring.

Preferably, the first insulating layer includes silicon nitride or silicon dioxide, and the second wiring includes a reflective conductive material. The second contact hole preferably exposes a boundary of the first contact hole.

At this time, it is preferable that the second insulating layer has an uneven pattern on its surface.

The above-mentioned method of manufacturing a semiconductor device is also applicable to a method of manufacturing a thin film transistor array panel for a liquid crystal display.

In more detail, in the method of manufacturing a TFT array panel for LCD according to the present invention, a gate wiring including a gate line and a gate electrode connected to the gate line is formed on an insulating substrate, and then a gate insulating layer is deposited . Next, a semiconductor layer and data wiring are formed. The data wiring includes a data line crossing the gate line to define a pixel area, a source electrode connected to the data line and disposed near the gate electrode, and a drain electrode disposed opposite to the source electrode with respect to the gate electrode. A first insulating layer is deposited, and an organic insulating material is spin-coated on the first insulating layer. The organic insulating material is patterned to form a second insulating layer having a first contact hole exposing a portion of the first insulating layer opposite to the drain electrode. Subsequently, the exposed portion of the first insulating layer is patterned by photolithography using a photoresist pattern to form a second contact hole exposing the drain electrode together with the first contact hole. A pixel electrode connected to the drain electrode through the first and second contact holes is formed.

The pixel electrode may include a light-transmitting conductive electrode or a reflective conductive film. When the pixel electrode has a reflective film, it is preferable that the second insulating layer has a concave-convex pattern on a surface thereof. When the pixel electrode has both a light-transmitting electrode and a reflective film, it is preferable that the reflective film has holes in the pixel region.

The data wiring and the semiconductor layer may be simultaneously formed by photolithography using a photoresist pattern having a position-dependent thickness.

The gate wiring may further include a gate pad connected to one end of the gate line, the data wiring may further include a data pad connected to one end of the data line, and the first insulating layer or gate insulating layer There may be a third contact hole exposing the gate pad or the data pad. The thin film transistor array panel may further include a sub-pad electrically connected to the gate pad or the data pad through a third contact hole, wherein the sub-pad is made of the same layer as the pixel electrode.

A method of manufacturing a semiconductor device, the method comprising forming a first wiring on a substrate; depositing a first insulating layer covering the first wiring; forming a second insulating layer on the first insulating layer; patterning the second insulating layer to form a first contact hole exposing the first insulating layer opposite to the first wiring; patterning the first insulating layer by photolithography using a photoresist pattern forming a second contact hole exposing the first wiring and the first contact hole; and forming a second wiring connected to the first wiring through the first and second contact holes.

A semiconductor device including: a substrate; a first wiring formed on the substrate; a first insulating layer covering the first wiring and having a first contact patterned by photolithography so as to expose the first wiring a hole; a second insulating layer formed on the first insulating layer and having a second contact hole patterned by photolithography so as to expose a boundary of the first contact hole and a flat upper surface of the first insulating layer; and a second wiring formed on the second insulating layer and connected to the first wiring through the first and second contact holes, wherein a surface width of the first insulating layer exposed through the second contact hole Equal to or greater than 0.1 microns.

Description of drawings

1A to 1C are cross-sectional views of a contact structure of a semiconductor device according to an embodiment of the present invention, which sequentially illustrate a method of manufacturing the semiconductor device;

2 is a layout diagram of a TFT array plate for a transflective LCD according to an embodiment of the present invention;

Fig. 3 is a sectional view along line III-III' of Fig. 2;

4A, 5A, 6A, 7A, 8A and 9A are layout diagrams of a TFT array plate for a transflective LCD in an intermediate step of its manufacturing method according to an embodiment of the present invention;

Fig. 4B is a cross-sectional view along line IVB-IVB' of Fig. 4A;

Figure 5B is a cross-sectional view along line V-V' of Figure 5A and illustrates the subsequent steps of the steps shown in Figure 4B;

Figure 6B is a cross-sectional view along line VIB-VIB' of Figure 6A and illustrates a subsequent step to the step shown in Figure 5B;

Figure 7B is a cross-sectional view along line VIIB-VIIB' of Figure 7A and illustrates the subsequent steps of the steps shown in Figure 6B;

Figure 8B is a cross-sectional view of Figure 8A along the line VIIIB-VIIIB' and illustrates the subsequent steps of the steps shown in Figure 7B;

Figure 9B is a cross-sectional view of Figure 9A along the line IXB-IXB' and illustrates subsequent steps of the steps shown in Figure 8B;

10 is a layout diagram of a reflective LCD TFT array plate according to a second embodiment of the present invention;

Fig. 11 is a cross-sectional view of the TFT array plate shown in Fig. 10 along line XI-XI';

12 is a layout diagram of a TFT array panel for LCD according to a third embodiment of the present invention;

Fig. 13 is a sectional view of the TFT array plate shown in Fig. 12 along line XII-XII';

14 is a layout diagram of a TFT array panel for LCD according to a fourth embodiment of the present invention;

Figures 15 and 16 are cross-sectional views of the TFT array plate shown in Figure 14 along the XV-XV' line and the XVI-XVI' line;

17A is a layout view of a TFT array panel in a first step of its manufacturing method according to a fourth embodiment of the present invention;

Fig. 17B and 17C are the sectional views along XVIIB-XVIIB' and XVIIC-XVIIC' line of Fig. 17A respectively;

18A and 18B are respectively the sectional views of Fig. 17A along XVIIB-XVIIB' and XVIIC-XVIIC' lines, and respectively illustrate the subsequent steps of the steps shown in Fig. 17B and 17C;

19A is a layout diagram of a TFT array plate in the subsequent steps of the steps shown in FIGS. 18A and 18B;

Fig. 19B and 19C are the sectional views along XIXB-XIXB' and XIXC-XIXC' line of Fig. 19A respectively;

Figures 20A, 21A and 22A and Figures 20B, 21B and 22B are the corresponding cross-sectional views of Figure 19A along lines XIXB-XIXB' and XIXC-XIXC', respectively, and illustrate subsequent steps of the steps shown in Figures 19B and 19C, respectively;

23A is a layout diagram of a TFT array plate in a subsequent step of the steps shown in FIGS. 22A and 22B;

Fig. 23B and 23C are the sectional views of Fig. 23A along XXIIIB-XXIIIB' and XXIIIC-XXIIIC' lines respectively;

24A is a layout diagram of a TFT array plate in a subsequent step of the steps shown in FIGS. 23B and 23C; and

Figures 24B and 24C are cross-sectional views of Figure 24A along lines XXIVB-XXIVB' and XXIVC-XXIVC', respectively, and illustrate the sequence of steps subsequent to the steps shown in Figures 23B and 23C, respectively.

Detailed ways

Now, a contact structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention, a TFT array plate including a contact structure and a method of manufacturing the same will be described with reference to the accompanying drawings, so that those skilled in the art can easily implement the present invention.

First, a method for manufacturing a contact structure of a semiconductor device according to an embodiment of the present invention will be described.

Generally, a semiconductor device has multilayer wiring interposed between interlayer insulating layers. The interlayer insulating layer is preferably made of a material with a low dielectric constant in order to minimize interference between signals flowing in different wirings, and to electrically connect different wiring layers transmitting the same signal to each other through a contact hole provided at the interlayer insulating layer. connect.

The interlayer insulator preferably includes an insulating layer preferably made of silicon nitride or silicon dioxide, and an organic layer made of an organic insulating material having a low dielectric constant. The insulating layer is preferably formed by chemical vapor deposition (CVD), while the organic layer is preferably formed by spin coating. According to an embodiment of the present invention, the insulating layer is patterned after forming the organic layer on the insulating layer, so as to improve the step height of the organic layer caused by the depth of the contact hole preliminarily arranged on the insulating layer, and the After the insulating layer is patterned to form the contact holes, the underlying wiring is exposed when the organic layer is coated, which allows the organic material to be localized on specific areas during the spin-coating process.

1A to 1C are cross-sectional views of a contact structure of a semiconductor device according to an embodiment of the present invention, which sequentially illustrate steps of a method of manufacturing the semiconductor device.

In a method of manufacturing a contact structure of a semiconductor device according to an embodiment of the present invention, first, as shown in FIG. 1A , a first insulating layer 310 preferably made of silicon nitride or silicon dioxide is deposited on it with The first wiring 200 is on the substrate 100 . A second insulating layer 320 preferably made of an organic insulating material having a low dielectric constant is coated on the first insulating layer 310 to form the interlayer insulator 300 . Subsequently, the second insulating layer 320 is patterned by photolithography using a mask to form a first contact hole 330 exposing a portion of the lower insulating layer 310 on the first wiring 200 .

Further, as shown in FIG. 1B , using a photoresist pattern 400 having a hole inside the first contact hole 330 , the exposed portion of the first insulating layer 310 is patterned by photolithography to form a second contact hole 340 .

Finally, as shown in FIG. 1C, after removing the photoresist pattern 400, a conductive material is deposited on the second insulating layer 320, and it is patterned by photolithography using a mask to form a contact through the first and second contacts. The holes 330 and 340 are the second wiring 500 electrically connected to the first wiring 200 .

Since the first contact hole 330 exposes the upper surface of the first insulating layer 310, the resulting contact structure of the semiconductor device according to this embodiment of the present invention includes sidewalls having a stepped structure without undercuts.

The manufacturing method of the contact structure of the semiconductor device according to this embodiment of the present invention eliminates the localized distribution of the organic material on the specific area caused by the height difference during the spin-coating process, and the method is to spin-coat the first insulating layer 310 before patterning The second insulating layer 320 made of an organic insulating material.

Meanwhile, the manufacturing method of the contact structure of a semiconductor device according to this embodiment of the present invention is applicable to a TFT array panel for LCD and its manufacturing method.

First, a transflective LCD according to a first embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3. FIG.

2 is a layout view of a TFT array panel of a transflective LCD according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of FIG. 2 along line III-III'.

Gate wiring is formed on the insulating substrate 10 . The gate wiring includes a single layer preferably made of silver, silver alloy, aluminum, and aluminum alloy having low resistivity, or includes a multilayer including the single layer.

The gate wiring includes: a plurality of gate lines 22 substantially extending laterally; a plurality of gate pads 24 connected to one end of the gate lines 22, which are used to receive gate signals from external devices and The electrode signal is transmitted to the gate line 22; and the gate electrodes 26 of the plurality of TFTs of the TFTs connected to the gate line 22. The gate wiring may overlap the subsequently formed pixel electrodes 82 and 86 to form a storage capacitor, or may include a plurality of storage electrodes applied with a predetermined voltage, such as a common electrode voltage from an external power source (which is controlled by applied to the common electrode of the upper panel and hereinafter referred to as "common voltage") so that the storage electrode overlaps the pixel electrodes 82 and 86 described later to form a storage capacitor for improving the charge storage capability of the pixel.

A gate insulating layer 30 preferably made of silicon nitride and formed on the substrate 10 covers the gate wirings 22 , 24 and 26 .

A semiconductor layer 40 preferably made of amorphous silicon is formed on the gate insulating layer 30 opposite to the gate electrode 24, and an ohmic contact layer made of silicide or n+ hydrogenated amorphous silicon heavily doped with n-type impurities 55 and 56 are formed on the semiconductor layer 40 .

Data wiring is formed on the ohmic contact layers 55 and 56 and the gate insulating layer 30 . The data wiring includes a conductive layer preferably made of a conductive material with low resistivity, such as aluminum and silver. The gate wiring includes: a plurality of data lines 62 substantially extending longitudinally and intersecting with the gate lines 22 to define a pixel area, connected to the data lines 62 and extending to a portion 55 of the ohmic contact layers 54 and 56 A plurality of source electrodes 65, connected to one end of the data line 62, a plurality of data pads 68 for receiving image signals from an external device, and separated from the source electrodes 65 and disposed opposite to the source electrode 53 with respect to the gate electrode 26 A plurality of drain electrodes 66 on another portion 56 of ohmic contact layers 54 and 56 .

A first insulating layer 70 preferably made of silicon nitride is formed on the data wirings 62, 65, 66, and 68 and portions of the semiconductor layer 40 not covered by the data wirings 62, 65, 66, and 68, and on the second A second insulating layer 90 is formed on the first insulating layer 70 . The second insulating layer 90 is preferably made of a photosensitive organic material with good planarity. The upper surface of the second insulating layer 90 has a flat pattern in order to maximize the reflection efficiency of the reflective film 86 formed later. In the pad region with the gate pad 24 and the data pad 68 , the second insulating layer 90 is removed while still remaining the first insulating layer 70 . This structure removes the organic insulating material on the pad area and is therefore advantageously suitable for chip on glass (COG) type LCDs, where scan signals and image signals are transmitted to the gate pad 24 and the gate pad 24, respectively. A plurality of gate driving integrated circuits (ICs) and a plurality of data driving ICs of the data pad 68 are directly mounted on the TFT array board.

A plurality of contact holes 76 and 78 respectively exposing the drain electrode 66 and the data pad 68 are provided on the first insulating layer 70, and are provided on the gate insulating layer 30 and the first insulating layer 90 to expose the gate A plurality of contact holes 74 of pad 24 . The second insulating layer 90 has a plurality of contact holes 96 exposing the drain electrode 66 , an edge of the contact hole 76 of the first insulating layer exposing the drain electrode 66 , and a flat surface of the first insulating layer 70 .

A plurality of translucent electrodes 82 are formed on the second insulating layer 90 . The translucent electrode 82 is basically disposed in the pixel region, and is electrically connected to the drain electrode 66 through the contact holes 76 and 96 .

A reflective film 86 having a hole 85 is formed on each translucent electrode 82 . In the pixel region P, the region T defined by the hole 85 is called a transmissive region, and the remaining region R is called a reflective region.

The translucent electrode 82 is preferably made of a translucent conductive material such as indium zinc oxide (IZO) and indium tin oxide (ITO), while the reflective film 86 is preferably made of reflective aluminum, aluminum alloy, Made of silver and silver alloy. Each reflective film 86 preferably includes a contact auxiliary layer disposed on the contact surface with the translucent electrode 82 to ensure good contact characteristics between the reflective film 86 and the translucent electrode 82, and the contact auxiliary layer preferably Made of molybdenum, molybdenum alloys, chromium, titanium or tantalum.

In addition, a plurality of sub-gate pads 84 and a plurality of sub-data pads 88 are formed on the first insulating layer 70 . The sub-gate pad 84 and the sub-data pad 88 are connected to the gate and data pads 24 and 68 through the contact holes 74 and 78, respectively. Although the sub-gate and data pads 84 and 88 are not required, they are preferred to protect the gate and data pads 24 and 68 . The sub-gates and data pads 84 and 88 are preferably formed from the same layer of the light-transmitting electrode 82 or the reflective film 86 .

A method of manufacturing a TFT array panel for a transflective type LCD according to a first embodiment of the present invention will now be described with reference to FIGS. 4A to 9B and FIGS. 2 and 3 .

As shown in FIGS. 4A and 4B , a conductive material having a low resistivity is deposited on a glass substrate 10 and patterned by photolithography using a mask to form a gate wiring extending substantially laterally, the gate wiring including A plurality of gate lines 22 , a plurality of gate electrodes 26 and a plurality of gate pads 24 .

Next, as shown in FIGS. 5A and 5B, after sequentially depositing three layers including a gate insulating layer made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50, using The mask patterns the doped amorphous silicon layer 50 and the semiconductor layer 40 to form the semiconductor layer 40 and the ohmic contact layer 50 opposite to the gate electrode 24 on the gate insulating layer 30 .

Subsequently, as shown in FIGS. 6A and 6B, a conductive layer for data wiring is deposited and patterned by photolithography using a mask to form a data wiring, which includes a plurality of data lines 65 crossing the gate lines 22, A plurality of source electrodes 65 connected to the data line 65 and extending to the gate electrode 26, a plurality of data pads 68 connected to one end of the data line 62, and a plurality of data pads 68 separated from the source electrode 65 and related to the gate electrode 26 and the source electrode 65 opposite the drain electrode 66 .

Thereafter, the portion of the doped amorphous silicon pattern 50 not covered by the data wirings 62, 65, 66, and 68 is etched to separate the doped amorphous silicon layer pattern 50 into two portions facing each other with respect to the gate electrode 26. 55 and 56 so as to expose the portion of the semiconductor pattern 40 between the two doped amorphous silicon layers 55 and 56 portions. An oxygen plasma treatment is preferably performed in order to stabilize the exposed surface of the semiconductor layer 40 .

As shown in FIGS. 7A and 7B, silicon nitride is deposited by CVD to form a first insulating layer 70, and a photosensitive organic material with good planarity is coated on the first insulating layer 70 before patterning the first insulating layer 70. so as to form the second insulating layer 90. Spin-coating the second insulating layer 90 before patterning the first insulating layer 70 according to this embodiment of the present invention prevents the localized distribution of the organic material on a specific area because there is no The height difference caused by 70.

Thereafter, the second insulating layer 90 is patterned by photolithography using a mask to form a plurality of contact holes 96 exposing portions of the first insulating layer 70 opposite to the drain electrode 66, and at the same time An uneven pattern forms on the surface. Next, a portion of the second insulating layer 90 at the pad region provided with the gate pad 24 and the data pad 68 is removed so as to expose the first insulating layer 70 .

Subsequently, as shown in FIGS. 8A and 8B, the first insulating layer 70 and the gate insulating layer 30 are patterned by photolithography using a photoresist pattern 1000 to form a plurality of exposed gate pads 24, drain electrodes 66, respectively. and contact holes 74 , 76 and 78 of data pad 68 . The contact hole 76 of the first insulating layer 70 exposing the drain electrode 66 is provided inside the contact hole 96 of the second insulating layer 90 so as to expose the edge and the flat surface of the first insulating layer 70, and thus make the contact structure have an Stepped shape with undercut. Preferably, the width of the exposed surface of the first insulating layer 70 at the contact formation is 0.1 micron or greater.

Next, as shown in FIGS. 9A and 9B , deposit ITO or IZO and pattern it with a mask to form a plurality of light-transmitting electrodes 82 connected to the drain electrode 66 through the contact holes 76 and 96, and a plurality of through contact holes. 74 is a sub-gate pad 84 connected to the gate pad 24 , and a plurality of sub-data pads 88 are connected to the data pad 68 through contact holes 78 .

Finally, as shown in FIGS. 2 and 3 , a reflective conductive material including silver or aluminum having reflective ability is deposited and patterned by photolithography using a mask to form a plurality of reflective films 86 on the corresponding light-transmitting electrodes 82. . At this time, each reflective film 86 preferably includes a contact assisting layer made of a material having good contact characteristics with other materials in order to improve contact characteristics with the light-transmitting 82 electrode.

According to the first embodiment of the present invention, the second insulating layer 90 is spin-coated before patterning the first insulating layer 70, which prevents the local distribution of the organic material on a specific area, because there is no Due to the height difference caused by the first insulating layer 70 , a consistent convex-concave pattern is obtained on the second insulating layer 90 . Accordingly, the protrusions of the reflective film 86 following the convex-concave pattern of the second insulating layer 90 are formed uniformly, and this prevents defects on screen display images.

Since the first insulating layer 70 is patterned after the organic insulating material is removed from the pad region in forming the second insulating layer 90, the manufacturing method of the TFT array panel according to the embodiment of the present invention completely prevents the organic Insulation material remains on pad area. Therefore, the TFT array panel manufactured by this method is advantageously particularly applicable to COG type LCDs in which a plurality of gate drive ICs and A plurality of data driving ICs are directly provided on the TFT array board.

Meanwhile, the manufacturing method according to the first embodiment of the present invention is applicable to a manufacturing method of a TFT array panel for a reflective LCD.

A TFT array panel for a reflective LCD according to a second embodiment of the present invention will now be described in detail with reference to FIGS. 10 and 11. FIG.

As shown in FIGS. 10 and 11, the configuration is almost the same as that according to the first embodiment.

However, unlike the first embodiment, the plurality of reflective films 86 are directly disposed on the second insulating layer 90 and are directly electrically connected to the plurality of drain electrodes 66 through the plurality of contact holes 76 and 96 . In addition, the reflective film 86 occupies the entire pixel area.

The manufacturing method of the TFT array panel for reflective LCD according to the second embodiment of the present invention is almost the same as that of the first embodiment until the step of forming a plurality of contact holes 74 , 76 and 78 on the first insulating layer 70 .

However, in the first embodiment, after the contact holes 74, 76 and 78 exposing the plurality of drain electrodes 66, the plurality of gate pads 24 and the plurality of data pads 68 are formed in the first insulating layer 70, by A reflective conductive material is immediately deposited and patterned to form a plurality of reflective films 86 .

The manufacturing method according to the first embodiment of the present invention is also applicable to the manufacturing method of a TFT array panel for a transmissive LCD.

A TFT array panel for reflective LCD according to a third embodiment of the present invention will now be described in detail with reference to FIGS. 12 and 13. FIG.

As shown in FIGS. 12 and 13, the configuration is almost the same as that according to the first embodiment.

Different from the first embodiment, portions of each gate line 22 of the gate wirings 22 , 24 and 26 are wider than other portions to overlap the corresponding light-transmissive pixel electrodes 82 to obtain sufficient storage capacitance.

In addition, the data wirings 62, 65, 66, and 68 include conductor patterns 64 for storage capacitors overlapping the gate lines 22, and pixel electrodes 82 made of a light-transmitting conductive material are directly provided on the second insulating on layer 90. The pixel electrodes are substantially disposed in the pixel region, and are electrically connected to the plurality of drain electrodes 66 through the contact holes 76 and 96 . The pixel electrode 82 is electrically connected to the conductor pattern 64 through the contact holes 72 and 92 provided in the first and second insulating layers 70 and 90, and is provided in the first insulating layer 70 and the gate insulating layer 30 to expose the gate electrode. The contact hole 74 of the pad 24 is wider than the gate pad 24 .

The manufacturing method of the TFT array panel for reflective LCD according to the second embodiment of the present invention is almost the same as that according to the first embodiment until the step of forming contact holes 72, 74, 76 and 78 on the first insulating layer 70.

The manufacturing method of the TFT array panel according to the third embodiment of the present invention does not form a convex-concave pattern on the surface of the second insulating layer 90 , and provides the semiconductor layer 40 extending longitudinally along the data wirings 62 , 65 , 66 and 68 .

In the first embodiment, when the contact holes 72, 74, 76, and 78 exposing the plurality of drain electrodes 66, the plurality of gate pads 24, and the plurality of data pads 68 are formed in the first insulating layer 70, immediately A light-transmitting conductive material is deposited and patterned to form light-transmitting pixel electrodes 86 .

The above manufacturing method according to the embodiment of the present invention is also applicable to the manufacturing method of the TFT array plate for the transmissive LCD, which uses a photoresist pattern to form the semiconductor layer and the data wiring by photolithography, thereby simplifying the manufacturing process. This method will be described in detail with reference to the accompanying drawings.

First, the configuration of a unit pixel for a TFT array panel in an LCD manufactured using four masks according to an embodiment of the present invention will be described with reference to FIGS. 14 to 16 .

14 is a layout diagram of a TFT array plate for LCD according to a fourth embodiment of the present invention, and FIGS. 15 and 16 are cross-sectional views of the TFT array plate shown in FIG. 14 along lines XV-XV' and XVI-XVI' respectively ;

As in the third embodiment, gate wiring is formed on the insulating substrate 10 . The gate wiring is preferably made of a material having low resistivity such as silver, silver alloy, aluminum and aluminum alloy. The gate wiring includes a plurality of gate lines 22 , a plurality of gate pads 24 and a plurality of gate electrodes 26 . The gate wiring further includes a plurality of storage electrodes 28 formed on the substrate substantially parallel to the gate lines 22 and applied with a predetermined voltage, such as a common voltage from an external power source, which is also applied to the upper on the common electrode of the panel. The storage electrode 28 overlaps the storage capacitor conductor pattern connected to the pixel electrode 82 to form a storage capacitor for improving the charge storage capability of the pixel, wherein the conductor pattern will be described below. The storage electrode 28 can be ignored if the storage capacitance obtained by the overlap of the gate line 22 and the pixel electrode 82 to be described later is sufficient.

A gate insulating layer 30 preferably made of silicon nitride is formed on the gate wirings 22 , 24 , 26 and 28 while covering the gate wirings 22 , 24 , 26 and 28 .

Semiconductor patterns 42 and 48 preferably made of hydrogenated amorphous silicon are formed on the gate insulating layer 30, and preferably ohmic contact layer patterns or interlayer patterns made of amorphous silicon heavily doped with n-type impurities such as phosphorus 55 , 56 and 58 are formed on the semiconductor layers 42 and 48 .

Data wirings preferably made of an aluminum-based conductive material having low resistivity are formed on the ohmic contact layer patterns 55 , 56 and 58 . The data wiring includes a plurality of data portions 62 , 65 and 68 , drain electrodes 66 of a plurality of TFTs, and a storage capacitor conductor pattern 64 . Each data section includes: a data line 62 extending substantially longitudinally, a data pad 68 connected to one end of the data line 62 for receiving an image signal from an external device, and a plurality of sources branched from the data line 62 Electrode 65. The respective drain electrodes 66 are separated from the data portions 62, 65 and 68, and are disposed opposite to the respective source electrodes 53 with respect to the respective gate electrodes 26 or channel portions of the associated TFTs. A storage capacitor conductor pattern 64 is provided on the storage electrode 28 . In the absence of the storage electrode 28, the storage capacitor conductor pattern 64 is not provided.

The ohmic contact patterns 55 , 56 and 58 function to reduce contact resistance between the lower semiconductor patterns 42 and 48 and the upper data wirings 62 , 64 , 65 , 66 and 68 . The ohmic contact layer patterns 55 , 56 and 58 have substantially the same shape as the data wirings 62 , 64 , 65 , 66 and 68 . In detail, the data interlayer pattern 55 has substantially the same shape as the data portions 62, 65, and 68, the drain electrode interlayer pattern 56 has substantially the same shape as the drain electrode 66, and the storage capacitor interlayer pattern 58 has substantially the same shape as the storage capacitor conductor. Patterns 68 are substantially the same shape.

The semiconductor patterns 42 and 48 have the same shape as the data wirings 62 , 64 , 65 , 66 and 68 and the ohmic contact layer patterns 55 , 56 and 58 except for the channel region C of the TFT. Specifically, the storage capacitor semiconductor pattern 48 has substantially the same shape as the storage capacitor conductor pattern 68 and the storage capacitor ohmic contact layer pattern 58, while the TFT semiconductor pattern 42 layer is slightly different from the rest of the data wiring and ohmic contact layer patterns. On the channel region C of each TFT, although the data portions 62, 65 and 68 (in particular, the source electrode 65) are separated from the drain electrode 66, and the data intermediate layer pattern 55 is also separated from the drain electrode ohmic contact layer pattern 56. separated, but the TFT semiconductor pattern 42 is not disconnected so as to form a channel of the TFT.

The interlayer insulator includes a first insulating layer 70 preferably formed of silicon nitride and a second insulating layer 90 preferably made of an organic insulating material having a low dielectric constant, and as in the third embodiment, the interlayer insulator sets On data wires 62 , 65 , 66 and 68 . The first insulating layer 70 has a plurality of contact holes 76, 78, and 72 exposing the drain electrode 66, the data pad 68, and the storage capacitor conductor pattern 64, respectively, and exposing the gate pad 24 together with the gate insulating layer 30. A plurality of contact holes 74 . Similar to the third embodiment, the second insulating layer 90 is removed from the pad region to expose the first insulating layer 70, and the contact holes 72 and 96 expose the edges of the first insulating layer 70, the first insulating layer 70 An insulating layer 70 is a lower insulating layer such that the sidewalls of the contact holes 92 and 96 have a stepped shape.

A plurality of pixel electrodes 82 that receive image signals from the TFTs and generate an electric field in cooperation with electrodes on the upper panel are formed on the low-permittivity insulating layer 73 . The pixel electrode 82 is made of a light-transmitting conductive material such as IZO or ITO, and is electrically connected to the drain electrode 66 through the contact holes 76 and 96 to receive image signals. In addition, the pixel electrode 82 overlaps the adjacent gate line 22 and the adjacent data line 62 to increase the aperture ratio. However, the overlapping can be omitted. The pixel electrode 82 is connected to the storage capacitor conductor pattern 64 through the contact holes 72 and 92 to transmit image signals.

A plurality of sub-gate pads 84 and a plurality of sub-data pads 88 are formed on the first insulating layer 70 . The sub-gate pad 84 and the sub-data pad 88 are disposed on the gate pad 24 and the data pads 24 and 68, respectively, and thus are connected thereto through the contact holes 74 and 78, respectively. The sub-gate pads 84 and sub-data pads 88 are preferred, although not required, to protect the pads 24 and 68 and to aid in adhesion between the pads 24 and 68 and external circuit devices.

In the TFT array panel according to the fourth embodiment of the present invention, as described above, the contact holes 72 and 76 have stepped side walls due to the exposed surface of the first insulating layer 70, and expose the first insulating layer 70 at Surfaces in pad areas so that undercuts do not occur. This prevents disconnection of the pixel electrode 82 , the sub-gate pad 84 and the sub-data pad 88 . The sub-gate pad 84 and the sub-data pad 88 are at least partially disposed on the first insulating layer 70 .

In this embodiment, translucent ITO or IZO is used as an exemplary material of the pixel electrode 82 . However, for a reflective LCD, it is preferable to use a conductive material that does not transmit light.

Now, a method of manufacturing a TFT array panel for LCD having the configuration shown in FIGS. 14-16 using four masks will be described in detail with reference to FIGS. 14-16 and FIGS. 17A-24C.

First, as shown in FIGS. 17A-17C , gate wiring is formed on a substrate 10 by depositing a conductive material or a material for gate wiring and patterning it by photolithography using a first mask. It includes a plurality of gate lines 22 , a plurality of gate pads 24 , a plurality of gate electrodes 26 and a plurality of storage electrodes 28 . The gate wiring has a single-layer structure including a single layer made of a material having low resistivity such as aluminum, aluminum alloy, silver or silver alloy. Optionally, the conductive layer has a multi-layer structure including a single layer and a layer made of a conductive material having good contact properties with other materials, such as chromium, titanium and tantalum.

Next, as shown in FIGS. 18A and 18B, the gate insulating layer 30, the semiconductor layer 40 and the intermediate layer 50 are sequentially deposited by CVD so that the layers 30, 40 and 50 have 1,500-5,000 Ȧ, 500-2,000 Ȧ and 300- 600 Ȧ thickness. A conductive layer 60 for data wiring and having a low resistivity is deposited by sputtering, and the layer 60 has a thickness of 1,500-3,000 Ȧ, and then a photoresist with a thickness of 1-2 micrometers is coated on the conductive layer 60 etchant film 110.

Subsequently, the photoresist film 110 is exposed and developed through a second mask to form photoresist patterns 114 and 112 shown in FIGS. 19A-19C . The thickness of the first portion 114 of the photoresist patterns 114 and 112 on the TFT channel region C disposed between the source and drain electrodes 65 and 66 is formed to be smaller than that in which the data wirings 62, 64, 65, The thickness of the second portion 112 on the data area A of 66 and 68 . The photoresist film portion on the remaining area B is removed. A thickness ratio of the first portion 114 on the channel region C to the second portion 112 on the data region A is adjusted depending on etching conditions in an etching step described later. Preferably, the thickness of the first part 114 is equal to or less than half the thickness of the second part 112, in particular, it is equal to or less than 4000 Ȧ.

The position dependent thickness of a photoresist film can be obtained by several techniques. In order to adjust the exposure amount in the region A, a semitransparent region having a slit pattern, a lattice pattern, or a semitransparent film is provided on the mask.

When a slit pattern is used, preferably, the width of the portion between the slits or the distance between the portions (that is, the width of the slit) is smaller than the resolution of an exposure instrument used for photolithography. In the case of using a translucent film, films with different transmittances or with different thicknesses can be used to adjust the transmittance of the mask.

When the photoresist film is irradiated with a light beam through the above-mentioned mask, the polymer in the directly exposed portion is almost completely decomposed, and the polymer in the portion facing the slit pattern or the semi-transparent film due to small of exposure without being fully decomposed. The part of the polymer blocked by the light blocking film is hardly decomposed. The photoresist film is developed so that portions with polymer (which is not decomposed) remain and portions exposed to less light radiation become thinner than portions that have not undergone exposure. Here, it is not necessary to make the exposure time long enough to decompose all molecules.

The thin portion 114 of the photoresist pattern can be obtained by performing a reflow process such that the reflowable photoresist film flows into areas where there is no photoresist film after exposing and developing the photoresist film, The exposure therein uses a common mask having transmissive areas that completely transmit the light beam and blocking areas that completely block the light beam.

Thereafter, the photoresist pattern 114 and the underlying layers (that is, the conductive layer 60, the intermediate layer 50, and the semiconductor layer 40) are etched so that the data wiring and the underlying layers remain on the data region A, and the channel Only the semiconductor layer remains on the region C, and all three layers 60 , 50 and 40 in the remaining region B are removed to expose the gate insulating layer 30 .

As shown in FIGS. 20A and 20B , the exposed portion of the conductive layer 60 on the region B is removed so as to expose the underlying portion of the intermediate layer 50 . In this step, dry etching and wet etching are selectively used and are preferably performed under the condition that the conductive layer 60 is selectively etched while the photoresist patterns 112 and 114 are hardly etched. However, an etching situation that can etch the photoresist patterns 112 and 114 and the conductive layer 60 would be suitable for dry etching, because it is difficult to find a method that selectively etches only the conductive layer 60 without etching the photoresist patterns 112 and 114. Case. In this case, the first portion 114 should be relatively thick compared to the case of wet etching to prevent the underlying conductive layer 60 from being exposed due to etching.

Both dry etching and wet etching are suitable for conductive materials for data wiring including aluminum or an aluminum alloy. Wet etching is preferred for Cr, preferably using the etchant _CeNHO3 , Cr is difficult to remove by dry etching. However, a very thin Cr film of about 500 Å can be removed by dry etching.

Therefore, as shown in FIGS. 20A and 20B, the source/drain conductor pattern 67 (that is, the conductive layer portion on the channel region C and the data region A) and the storage capacitor conductor pattern 64 are retained, while the remaining region B Portions of the conductive layer 60 are removed to expose portions of the underlying intermediate layer 50 . The remaining conductor patterns 67 and 64 have substantially the same shape as the data wirings 62, 64, 65, 66 and 68, except that the source and drain electrodes 65 and 66 are still connected without being separated. The photoresist patterns 112 and 114 are also etched to a predetermined thickness when dry etching is used.

Next, as shown in FIGS. 21A and 21B, the exposed portion of the intermediate layer 50 on the region B and the underlying semiconductor layer 40 portion are simultaneously removed together with the first portion 114 of the photoresist film by dry etching. The sequential dry etching of the intermediate layer 50 and the semiconductor layer 40 may follow the dry etching of the conductor pattern 67, or an in-situ etching process may be performed. The etching of the intermediate layer 50 and the semiconductor layer 40 is preferably performed in a case where the photoresist patterns 112 and 114 , the intermediate layer 50 , and the semiconductor layer 40 are simultaneously etched without etching the gate insulating layer 30 . (Note that the semiconductor layer and the intermediate layer do not have etching selectivity.) In particular, the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are preferably equal to each other. For equal etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 , the thickness of the first portion 114 is preferably equal to or less than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50 .

Like this, as shown in Figure 21A and 21B, the conductive layer 60 part (that is, source/drain conductor pattern 67) and storage capacitor conductor pattern 64 on the channel region C and the data region A are reserved, and the remaining region B A portion of the conductive layer 60 is removed. In addition, the first portion 114 on the channel region C is removed to expose the source/drain conductor pattern 67, and the intermediate layer 50 and semiconductor layer 40 are partially removed on the region B to expose the underlying gate insulating layer 30 portion. . At the same time, the second portion 112 on the data region A is also etched to have a reduced thickness. In this step, the formation of the semiconductor patterns 42 and 48 is completed.

Reference numerals 57 and 58 denote intermediate layer patterns under the source/drain conductor pattern 67 and under the storage capacitor conductor pattern 64, respectively. Exposure of the portion of the source/drain conductor pattern 67 on the channel region C is optionally obtained by a separate photoresist (PR) etch-back step, which is not necessary if the photoresist film is sufficiently etched of.

Residual photoresist remaining on the surface of the source/drain conductor pattern 67 on the channel region C is then removed by ashing.

Subsequently, as shown in FIGS. 22A and 22B , the exposed portion of the source/drain conductor pattern 67 on the channel region C and the portion of the underlying source/drain interlayer pattern 57 are removed by etching. Dry etching may be applied to the source/drain conductor pattern 67 and the source/drain interlayer pattern 57 . Optionally, wet etching is used for the source/drain conductor pattern 67 and dry etching is used for the source/drain interlayer pattern 57 . At this time, as shown in FIG. 22B , the top of the semiconductor pattern 42 may be removed so that the thickness is reduced, and the second portion 112 of the photoresist pattern is etched to a predetermined thickness. Etching is carried out under the situation that the gate insulating layer 30 is hardly etched, and preferably, the photoresist film is very thick to prevent the second portion 112 from being etched so as to expose the underlying data wiring 62, 64, 65, 66 and 68.

In this way, the source and drain electrodes 65 and 66 are separated from each other while completing the formation of the data wiring lines 62 , 64 , 65 , 66 and 68 and the underlying ohmic contact layer patterns 55 , 56 and 58 .

Finally, the second portion 112 remaining on the data area A is removed. However, the removal of the second portion 112 may be performed between removing the portion of the source/drain conductor pattern 67 on the channel region C and removing the portion of the underlying intermediate layer pattern 57 .

As shown in FIGS. 23A-23C, after the data wirings 62, 64, 65, 66, and 68 are formed as described above, silicon nitride is deposited by CVD to form a first insulating layer 70. Referring to FIG. Before patterning the first insulating layer 70, the second insulating layer 90 is formed on the first insulating layer 70 by spin-coating a photosensitive organic material having good planarity and low dielectric constant. Spin-coating the second insulating layer 90 before patterning the first insulating layer 70 according to this embodiment of the present invention prevents the local distribution of the second insulating layer 90 on a specific area because there is no The height difference caused by the insulating layer 70.

Thereafter, the second insulating layer 90 is patterned by photolithography using a mask to form a plurality of contact holes 96 and 92 exposing portions of the first insulating layer 70 on the drain electrode 66 and the storage capacitor conductor pattern 68 . At this time, a portion of the second insulating layer 90 in the pad region provided with the gate pad 24 or the data pad 68 is removed so that the first insulating layer 70 is exposed.

Referring to FIGS. 24A and 24B , as in the first embodiment, the first insulating layer 70 and the gate insulating layer 30 are patterned by photolithography using a photoresist pattern to form a plurality of exposed gate pads 24, leakage electrodes, respectively. Contact holes 74 , 76 , 72 and 78 of pole 66 , storage capacitor conductor pattern 64 and data pad 68 . The contact holes 76 and 72 of the first insulating layer 70 exposing the drain electrode 66 and the storage capacitor conductor pattern 64 are disposed inside the contact holes 96 and 92 of the second insulating layer 90 .

Finally, after removing the photoresist pattern, as shown in FIGS. A pixel electrode 82 connected to the storage capacitor conductor pattern 64 , a plurality of sub-gate pads 84 connected to the gate pad 24 , and a plurality of sub-data pads 84 and 88 connected to the data pad 68 .

The fourth embodiment of the present invention not only provides the advantages according to the first embodiment, but also simplifies the process, that is, using one mask to form data wirings 62, 64, 65, 66 and 68, ohmic contact layer patterns 55, 56 and 58 , and the underlying semiconductor patterns 42 and 48, while, in this step, the source and drain electrodes 65 and 66 are separated from each other.

The connection between the driver IC and the pads of the TFT array panel for LCD manufactured by these methods is by using a tape carrier package (TCP) in which the driver IC is arranged on a corresponding film or by means of a chip on a film (chip). on film, COF) way. Optionally, the above-mentioned COG method of directly disposing the driver IC on the panel is used to realize the electrical connection therebetween.

As described above, when forming an organic insulating layer, according to the present invention, the organic insulating layer is spin-coated on the underlying insulating layer while maintaining a minimum level difference without patterning the underlying insulating layer, thereby preventing Organic insulating materials are confined to specific regions. This prevents image defects in reflective LCDs to improve display performance. In addition, the edge of the lower insulating layer is exposed at the contact portion, so that the sidewall of the contact hole has a stepped shape, thereby eliminating the undercut in the contact portion. This prevents disconnection at the contact portion to ensure reliability of the contact portion, thereby improving display characteristics of the product. In addition, the minimization of photolithography steps in the manufacture of TFT array panels for LCDs simplifies the manufacturing process and reduces production costs.

Claims (21)

1. method of making semiconductor device, described method comprises:

On substrate, form first wiring;

Deposition covers first insulating barrier of described first wiring;

On described first insulating barrier, form second insulating barrier;

The described second insulating barrier composition is exposed first contact hole of described first insulating barrier relative by photoetching with described first wiring with formation;

Use the photoresist pattern the described first insulating barrier composition to be exposed second contact hole of described first wiring and described first contact hole by photoetching with formation; And

Second wiring that formation is connected with described first wiring by described first and second contact holes.

2. method according to claim 1, wherein said first insulating barrier comprises silicon nitride or silicon dioxide.

3. method according to claim 1, wherein said second insulating barrier comprises organic insulating material.

4. method according to claim 1, wherein said second wiring comprises reflective conductive material.

5. method according to claim 1, the flat upper surfaces of described first insulating barrier of wherein said first contact holes exposing.

6. semiconductor device comprises:

Substrate;

Be formed on the wiring of first on the described substrate;

First insulating barrier, thus cover described first wiring and have first contact hole that exposes described first wiring by photoetching composition;

Second insulating barrier, thus be formed on described first insulating barrier and have second contact hole that exposes the flat upper surfaces of the border of described first contact hole and described first insulating barrier by photoetching composition; And

Be formed on second wiring that also links to each other on described second insulating barrier by described first and second contact holes and described first wiring,

Wherein said first insulating barrier is equal to or greater than 0.1 micron by the face width of described second contact holes exposing.

7. semiconductor device according to claim 6, wherein said second insulating barrier comprises organic insulating material.

8. semiconductor device according to claim 7, the surface of wherein said second insulating barrier has convex-concave pattern.

9. semiconductor device according to claim 6, wherein said second wiring comprises reflective conductive material.

10. a manufacturing is used for the method for the film transistor array plate of LCD, and this method comprises:

Form grid wiring on dielectric substrate, described grid wiring comprises gate line and the gate electrode that links to each other with described gate line;

The deposition gate insulator;

Form semiconductor layer;

Form data arrange, described data arrange comprises intersecting with described gate line and links to each other with the data wire that limits pixel region, with described data wire and the source electrode of close described gate electrode setting and the drain electrode that is oppositely arranged about described gate electrode and described source electrode;

Deposit first insulating barrier;

Spin coating organic insulating material on described first insulating barrier;

Second insulating barrier that described organic insulator composition is had first contact hole that exposes described first insulating barrier relative with formation by photoetching with described drain electrode;

Use the photoresist pattern the described first insulating barrier composition to be exposed second contact hole of described drain electrode and described first contact hole by photoetching with formation; And

The pixel electrode that formation is electrically connected by described first and second contact holes and described drain electrode.

11. method according to claim 10, wherein said pixel electrode comprise light transmission conductive electrode or reflection conductive film.

12. method according to claim 10, wherein the surface of described second insulating barrier has convex-concave pattern when described pixel electrode has reflective film.

13. method according to claim 12, wherein when described pixel electrode comprised optically transparent electrode and reflective film, described reflective film had the hole in described pixel region.

14. method according to claim 10 is wherein used to have the position and comply with the photoresist pattern of thickness and form described data arrange and described semiconductor layer simultaneously by photoetching.

15. method according to claim 10, the flat upper surfaces of described first insulating barrier of wherein said first contact holes exposing.

16. a film transistor array plate that is used for LCD comprises:

Be formed on the grid wiring on the dielectric substrate, described grid wiring comprises gate line and the gate electrode that links to each other with described gate line;

Cover the gate insulator of described grid wiring;

Be formed on the semiconductor layer on the described gate insulator;

Be formed on the data arrange on described gate insulator or the described semiconductor layer, this data arrange comprises with described gate line and intersects the drain electrode that links to each other with the data wire that limits pixel region, with described data wire and be arranged near the source electrode the described gate electrode and be oppositely arranged about described gate electrode and described source electrode;

First insulating barrier, thus cover described semiconductor layer and have first contact hole that exposes described drain electrode by photoetching composition;

Second insulating barrier, thus be formed on described first insulating barrier and have second contact hole that exposes the flat upper surfaces of described drain electrode and described first contact hole and described first insulating barrier by photoetching composition; And

Be formed on the pixel electrode that also links to each other with described drain electrode on described second insulating barrier by described first and second contact holes,

Wherein said first insulating barrier is equal to or greater than 0.1 micron by the upper surface width of described second contact holes exposing.

17. film transistor array plate according to claim 16, wherein said second insulating barrier comprises organic insulating material.

18. film transistor array plate according to claim 16, wherein said pixel electrode comprise light transmission conductive electrode or reflection conductive film.

19. film transistor array plate according to claim 16, wherein when described pixel electrode had reflective film, the surface of described second insulating barrier had convex-concave pattern.

20. film transistor array plate according to claim 16, wherein when described pixel electrode comprised optically transparent electrode and reflective film, described reflective film had the hole in described pixel region.

21. film transistor array plate according to claim 16, wherein said grid wiring further comprises the gate liner that links to each other with described gate line one end, described data arrange further comprises the data pad that links to each other with described data wire one end, and described first insulating barrier or described gate insulator have the 3rd contact hole that exposes described gate liner or described data pad, and described film transistor array plate further comprises by described the 3rd contact hole and described gate liner or described data pad is electrically connected and the sub-liner that is made of the identical layer of described pixel electrode.

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