CN100378687C - A cache prefetch module and method thereof - Google Patents
A cache prefetch module and method thereof Download PDFInfo
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- CN100378687C CN100378687C CNB2005100930779A CN200510093077A CN100378687C CN 100378687 C CN100378687 C CN 100378687C CN B2005100930779 A CNB2005100930779 A CN B2005100930779A CN 200510093077 A CN200510093077 A CN 200510093077A CN 100378687 C CN100378687 C CN 100378687C
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Abstract
The present invention discloses a cache prefetch module which comprises a cache bus interface, a system chip bus interface, control logic and a data buffer, wherein the control logic is used for sending out control information for reading an image subblock data to a system memory according to the control information from a processor for prefetching the complete image subblock data, then, the read image subblock data are stored in the data buffer, and the image subblock data in the data buffer are transmitted to a cache; the data buffer is used for storing the complete image subblock data read from the system memory. In addition, the present invention also discloses a cache prefetch method. Because the cache prefetch module of the present invention supports that one complete image subblock data is prefetched one time, and thus, the prefetching period of the image subblock data is shortened, the waiting time of the processor during the process that the image data is prefetched, and therefore, image processing speed is improved.
Description
Technical field
The present invention relates to the Data Access Technology field, particularly a kind of cache prefetch module and method thereof.
Background technology
In recent years, wait for the time of reading of data, proposed to use the technology of high-speed cache in order to reduce processor.Adopt high-speed cache System on Chip/SoC relevant portion as shown in Figure 1, this System on Chip/SoC comprises processor (CPU Core), high-speed cache, cache prefetch module, Installed System Memory, System on Chip/SoC bus.Wherein processor reading of data and control information of calculating and sending prefetch data to cache prefetch module from high-speed cache; What preserve in the high-speed cache is the data that processor will use; Cache prefetch module is used for being about to from the Installed System Memory read processor data of use, and data transmission is arrived high-speed cache; In store various data in the Installed System Memory; The System on Chip/SoC bus connects described cache prefetch module and Installed System Memory, and transmits various control informations and data.
Shown in Figure 2 is the structural representation of prior art high speed cache prefetching module, and this cache prefetch module comprises System on Chip/SoC bus interface, cache bus interface, data buffer and steering logic.Wherein the System on Chip/SoC bus interface is used for the connected system chip bus, be connected with Installed System Memory by the System on Chip/SoC bus, and in order to Data transmission and control information; The cache bus interface is used to connect high-speed cache, and in order to Data transmission and control information; The data buffer is used to store the view data of looking ahead from Installed System Memory, and it is made up of register, and the data buffer size is a cache lines (cache line), can store the data of 32 bytes; Steering logic is used for the prefetched instruction according to processor, the view data of a cache lines is read in control from Installed System Memory, and deposit the data buffer in, and the data of a cache lines in the data buffer are transferred to high-speed cache by the cache bus interface.Steering logic, the System on Chip/SoC bus interface, the data buffer, also exist the mutual of control information between the cache bus interface, thereby realize the transmission of data, when for example image data transmission in the data buffer being arrived high-speed cache, steering logic produces the control information to data buffer zone and cache bus interface, data buffer and cache bus interface are determined duty mutually according to the control information of steering logic then, when the data buffer is transmission (Transfer) state, the cache bus interface is that view data is transferred to high-speed cache from the data buffer through the cache bus interface when receiving (Receive) state.
In the Digital Image Processing process, every two field picture is divided into several image subblocks usually, the size of image subblock is generally 8 * 8 or 16 * 16 data points, the image subblock of 8 * 8 data points is corresponding to usually said piece (Block), and the image subblock of 16 * 16 data points is corresponding to usually said macro block (Macro Block).If image adopts the YUV4:2:2 coded format, each data point takies a byte, and the monochrome information of image subblock is respectively 8 * 8 bytes or 16 * 16 bytes so.Shown in Figure 3 is a picture frame of being made up of 99 macro blocks, and these 99 macro blocks are divided into 9 row 11 row, be labeled as respectively macro block 0, macro block 1 ... macro block 98, the size of each image subblock are 16 * 16 bytes, i.e. 256 bytes.
Suppose the image subblock of the N of processor in the pre-treatment frame shown in Figure 3 16 * 16 byte, the image subblock of N+1 16 * 16 bytes of need looking ahead, wherein N more than or equal to and 0 smaller or equal to 98.As shown in Figure 4, the look ahead process of an image subblock of aforementioned cache prefetch module is as follows in the prior art:
This moment, processor still was in idle condition, waited for the data of N+1 image subblock.
At this moment, processor still is in the state of waiting for N+1 image subblock data.
Look ahead flow process as can be seen from top, a cache lines is 32 byte datas because existing cache prefetch module can only be looked ahead at every turn, when image subblock data the time greater than 32 bytes, need repeatedly carry out just can the look ahead data of an image subblock of prefetch operation, processor is in waiting status for a long time during this, thereby causes image processing speed to slow down.
Summary of the invention
In view of this, the present invention proposes a kind of cache prefetch module and method thereof, in order to reduce the time that processor is waited for during view data is looked ahead at image subblock.
According to above-mentioned purpose, the invention provides a kind of cache prefetch module, comprise cache bus interface, System on Chip/SoC bus interface, steering logic and data buffer at least, wherein the cache bus interface is used to connect high-speed cache; The System on Chip/SoC bus interface is used for the connected system internal memory; Interconnective steering logic and data buffer are connected between cache bus interface and the System on Chip/SoC bus interface, described steering logic is used for the control information according to the sub-blocks of data of complete image of looking ahead of from processor, send the control information of reading the sub-blocks of data of described complete image to Installed System Memory, and the sub-blocks of data of the complete image that is read all is saved in described data buffer, and the sub-blocks of data of the complete image in the described data buffer is transferred to high-speed cache by a read operation; Data buffer, capacity are used to store the described sub-blocks of data of complete image that reads from Installed System Memory more than or equal to the size of an image subblock.
In technique scheme, described data buffer is made of register file.
Described control information of looking ahead the sub-blocks of data of complete image comprises the address information of first byte data in the described image subblock; Described steering logic is further used for producing according to the address information of first byte data in the described image subblock address information of remainder data in the described image subblock, and sends the control information of the described image subblock data that comprise described all data address information of image subblock to Installed System Memory.
The present invention also provides a kind of cache prefetch method, and this method may further comprise the steps:
A. receive processor and look ahead after the control information of the sub-blocks of data of complete image, cache prefetch module sends the control information of reading described image subblock data to Installed System Memory, and reads complete described image subblock data by a read operation; B. described image subblock data are saved in the cache prefetch module, comprise the data buffer of a capacity in the described cache prefetch module more than or equal to an image subblock; C. described image subblock data transmission is arrived high-speed cache.
Described control information of looking ahead the sub-blocks of data of complete image comprises the address information of first byte data in the described image subblock; Cache prefetch module described in the steps A further comprised before Installed System Memory sends the control information of reading described image subblock data: the address information of first byte data produces the address information of remainder data in the described image subblock in according to described image subblock; Described cache prefetch module sends the address information that the control information of reading described image subblock data comprises all data in the described image subblock to Installed System Memory.
Further, comprise that processor reads the step of described image subblock data from described high-speed cache after the step C.
From such scheme as can be seen, the sub-blocks of data of complete image because cache prefetch module support of the present invention is once looked ahead, shortened the cycle of the image subblock data of looking ahead, reduced the time that processor is waited for during view data is looked ahead, thereby improved image processing speed.
Description of drawings
Fig. 1 is the position view of cache prefetch module in system;
Fig. 2 is the structural representation of prior art high speed cache prefetching module;
Fig. 3 is an image that comprises 11 * 9 image subblocks;
Fig. 4 is the schematic flow sheet of one the 256 sub-piece of byte image of looking ahead in the prior art;
Fig. 5 is the structural representation of cache prefetch module of the present invention;
Fig. 6 is the look ahead schematic flow sheet of one the 256 sub-piece of byte image of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in more detail by the following examples.
The cache prefetch module that the present invention proposes is the same with prior art in the position of digital image processing system, but the concrete structure of the cache prefetch module that the present invention proposes and function are unlike the prior art.
With reference to figure 5, cache prefetch module of the present invention comprises System on Chip/SoC bus interface, cache bus interface, data buffer and steering logic.Wherein the System on Chip/SoC bus interface is used for the connected system chip bus, be connected with Installed System Memory by the System on Chip/SoC bus, and Data transmission and control information.The cache bus interface is used to connect high-speed cache, and Data transmission and control information.Steering logic and data buffer are connected between System on Chip/SoC bus interface and the cache bus interface, and steering logic and data buffer interconnect between the two.The data buffer is used to store the view data of looking ahead from Installed System Memory, it is made up of register, unlike the prior art be, data buffer of the present invention size is at least the size of an image subblock, according to existing Mpeg-1, Mpeg-2, Mpeg-4, H.261, H.263 or H.264 wait the encoding and decoding treatment technology to know that the size of image subblock is generally 64 bytes or 256 bytes, in order not cause redundant waste, the size of the needs data buffer that can handle according to real image is set to 64 bytes or 256 bytes, and promptly the data buffer is made up of the register file that can store 64 bytes or 256 bytes.Compared with prior art, be equivalent to newly add register on the structure in the data buffer.The prefetched instruction of steering logic receiving processor, after the address information of first byte data produces the address information of remainder data of an image subblock automatically in the image subblock that sends over according to processor, send the control information of reading these image subblock data to Installed System Memory by the System on Chip/SoC bus interface, this control information comprises the address information of all data in reading order and the above-mentioned image subblock, from Installed System Memory, read the data of an image subblock, and deposit the data buffer in, and the data of an image subblock in the data buffer are transferred to high-speed cache by the cache bus interface.Same as the prior art, steering logic, the System on Chip/SoC bus interface, the data buffer, also exist the mutual of control information between the cache bus interface, thereby realize the transmission of data between each module, when for example image data transmission in the data buffer being arrived high-speed cache, steering logic produces the control information to data buffer zone and cache bus interface, data buffer and cache bus interface are determined duty mutually according to the control information of steering logic then, when the data buffer is transmission (Transfer) state, the cache bus interface is that view data is transferred to high-speed cache from the data buffer through the cache bus interface when receiving (Receive) state.
Suppose the image subblock of the N of processor in the pre-treatment frame shown in Figure 3 16 * 16 byte, the image subblock of N+1 16 * 16 bytes of need looking ahead, wherein N more than or equal to and 0 smaller or equal to 98.As shown in Figure 6, the look ahead process of an image subblock of high speed cache prefetching module of the present invention is as follows:
Step 601, steering logic receive the look ahead control information of N+1 complete image subblock of processor, and this control information comprises the address information of first byte data in described N+1 the image subblock.The image subblock because cache prefetch module support of the present invention is once looked ahead, so processor can send the control information of the image subblock of looking ahead to this cache prefetch module.Then, steering logic produces the address information of all the other 255 byte datas in this image subblock according to the address information of first byte data in described N+1 the image subblock.The method possibility that the steering logic of different vendor produces the remainder data address information is different, the simplest method is exactly to add one to 255 fixed numeric values on the address information of first byte data successively, thereby produces the address information of remaining 255 byte data.
At this moment, the data of current N the image subblock of processor processing are perhaps handled the data of N image subblock, are in the state of waiting for N+1 image subblock data.If processor is being handled the data of N image subblock, so after the data of intact N the image subblock of processor processing, just can directly from high-speed cache, read N+1 image subblock data, thereby do not need to wait for, compare with prior art, reduce the time that processor is waited for, improved the efficient of Flame Image Process.If processor has been handled the data of N image subblock, and be in the state of waiting for N+1 image subblock data, so after this time of cache prefetch module end looked ahead, just can from high-speed cache, read the data of N+1 image subblock, compare with prior art, reduce the time that processor is waited for equally, improved the efficient of Flame Image Process.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a cache prefetch device comprises cache bus interface, System on Chip/SoC bus interface, steering logic and data buffer at least, and wherein the cache bus interface is used to connect high-speed cache; The System on Chip/SoC bus interface is used for the connected system internal memory; Interconnective steering logic and data buffer are connected between cache bus interface and the System on Chip/SoC bus interface,
It is characterized in that, described steering logic is used for the control information according to the sub-blocks of data of complete image of looking ahead of from processor, send the control information of reading the sub-blocks of data of described complete image to Installed System Memory, and the sub-blocks of data of the complete image that is read all is saved in described data buffer, and the sub-blocks of data of the complete image in the described data buffer is transferred to high-speed cache by a read operation;
Data buffer, capacity are used to store the described sub-blocks of data of complete image that reads from Installed System Memory more than or equal to the size of an image subblock.
2. cache prefetch device according to claim 1 is characterized in that described data buffer is made of register file.
3. cache prefetch device according to claim 1 is characterized in that described control information of looking ahead the sub-blocks of data of complete image comprises the address information of first byte data in the described image subblock;
Described steering logic is further used for producing according to the address information of first byte data in the described image subblock address information of remainder data in the described image subblock, and sends the control information of the described image subblock data that comprise described all data address information of image subblock to Installed System Memory.
4. a cache prefetch method is characterized in that, this method may further comprise the steps:
A. receive processor and look ahead after the control information of the sub-blocks of data of complete image, cache prefetch module sends the control information of reading described image subblock data to Installed System Memory, and reads complete described image subblock data by a read operation;
B. described image subblock data are saved in the cache prefetch module, comprise the data buffer of a capacity in the described cache prefetch module more than or equal to an image subblock;
C. described image subblock data transmission is arrived high-speed cache.
5. method according to claim 4 is characterized in that described control information of looking ahead the sub-blocks of data of complete image comprises the address information of first byte data in the described image subblock;
Cache prefetch module described in the steps A further comprised before Installed System Memory sends the control information of reading described image subblock data: the address information of first byte data produces the address information of remainder data in the described image subblock in according to described image subblock;
Described cache prefetch module sends the address information that the control information of reading described image subblock data comprises all data in the described image subblock to Installed System Memory.
6. method according to claim 4 is characterized in that, comprises that further processor reads the step of described image subblock data from described high-speed cache after the step C.
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| CN101526924B (en) * | 2009-04-22 | 2010-09-08 | 东南大学 | A Method for Optimizing Data Access of Digital Signal Processing Chip |
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| CN101634971B (en) * | 2009-09-01 | 2011-07-06 | 威盛电子股份有限公司 | Data pre-extraction method and device, computer system |
| CN102110147B (en) * | 2011-02-16 | 2012-10-10 | 北京数码大方科技有限公司 | Cache-based CAD file data unloading method and device |
| CN103729142B (en) * | 2012-10-10 | 2016-12-21 | 华为技术有限公司 | The method for pushing of internal storage data and device |
| CN103034455B (en) * | 2012-12-13 | 2015-09-16 | 东南大学 | Based on data message buffer memory management method and the system of Decoding Analysis in advance |
| CN103077129B (en) * | 2012-12-31 | 2016-07-13 | 上海算芯微电子有限公司 | Information processing method and device |
| CN104899824B (en) * | 2014-03-05 | 2018-11-16 | 珠海全志科技股份有限公司 | Processing method and system of the image data in DRAM |
| CN107168660B (en) * | 2016-03-08 | 2024-05-10 | 成都锐成芯微科技股份有限公司 | Image processing cache system and method |
| WO2018111246A1 (en) * | 2016-12-13 | 2018-06-21 | Google Llc | Systems and methods for prefetching content items |
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