CN100377115C - Stack cache memory and buffer storage method suitable for context switching - Google Patents

Abstract

This invention discloses one shed high buffer memory and its buffer memory method suitable for upper and down text switch, which comprises at least two shed high speed buffer blocks; one or gate circuit, one selector, wherein, the shed buffer memory block is composed of label part, data part and control part; the said shed high speed buffer block is composed of at least three comparing circuits and one and gate circuit. The method comprises the following steps: a, initiating shed; b, aligning shed space; c, recycling shed space; comparing label to determine whether to shot of shed high buffer.

Description

Stack cache memory and buffer storage method suitable for context switching

technical field

The invention relates to the technical field of microprocessor architecture, in particular to a stack cache memory and a buffer storage method suitable for context switching.

Background technique

With the rapid development of microprocessor design and production technology, the gap between memory access speed and processor operation speed is becoming more and more significant. Moreover, the gap between the access speed of the memory and the operation speed of the processor increases at a rate of 50% every year, making the memory access speed more and more a bottleneck for improving the performance of the processor. Utilizing the principle of locality, using one or more levels of cache memory (Cache, referred to as "cache") is one of the effective means to improve the performance of the storage system. A cache is a small, fast special memory that holds instructions and data recently used by the processor. When the processor is running, if the accessed instruction or data is already in the cache, it can be accessed at a very high speed, otherwise it needs to access the memory and wait for a long time. Designing an efficient cache can significantly reduce the processor's average memory access time.

In order to make better use of the principle of locality and improve the cache hit rate, the cache is further divided into an instruction cache (Instruction Cache) and a data cache (Data Cache). Memory access is divided into code segment, data segment, heap space, and stack space, which makes it possible to further refine the data cache. Among them, the access of stack space data has good time locality and space locality, and the program continuously accesses the data close to the top of the stack. When the function is called, the saving of local variables, parameter passing, saving and restoring of registers are all done through the access of stack space. Stack cache memory (Stack Cache, referred to as "stack cache") separates stack access from data cache, which can make better use of the characteristics of stack space access, while preventing stack data from replacing heap data in the data cache Causes data cache pollution and reduces usage of data cache ports. The characteristics of stack space data access: (1) The access of stack space data has good time locality and space locality, and the program continuously accesses the data close to the top of the stack. Therefore, the stack cache does not need to be very large to have a high hit rate. (2) Stack space allocation, that is, the stack top pointer (sp) decreases, and there is no need to retrieve the original value of the corresponding block from the low-level storage system. (3) The stack space is reclaimed, that is, the stack top pointer (sp) is increased, and there is no need to write the reclaimed value (even if it is dirty) to the low-level storage system. (4) Stack access is access to continuous space, and continuous space can be accessed in the form of the same base address plus offset.

Figure 1 is a traditional stack cache structure and access diagram. In order to quickly obtain the information of whether the stack cache hits and the hit data, the stack cache uses a virtual address access method. The stack cache is divided into three parts: flag, data and control parts. The input is the address to access the stack cache, and the output is the signal and hit data of the stack cache hit or miss. The flag part of the stack cache includes a virtual base address (Vbase) field, a valid bit (Valid) field, a physical base address (Pbase) field, a stack top address (Top) field and a stack bottom address (Bottom) field. The data part of the stack cache includes a data (Data) field and a dirty bit (W) field indicating whether the data has been written. Since the stack of the microprocessor is allocated from high address to low address, the address of the bottom of the stack is greater than the address of the top of the stack. The bottom address of the stack is agreed by software, that is, determined by the binary program interface standard (ABI). As shown in FIG. 1 , the control unit includes a first comparison circuit, a second comparison circuit and an AND gate circuit. The first comparison circuit completes the judgment of whether the base address of the access is equal to the virtual base address of the stack cache, that is, judges whether Base=Vbase? . The second comparison circuit completes the judgment of whether the access address belongs to the stack space, that is, judges whether Top≤Vaddr≤Bottom? . The AND gate circuit completes the AND operation between the output of the first comparison circuit, the output of the second comparison circuit and the effective bit, determines whether the stack cache is hit, and outputs a signal of a stack cache hit or miss.

The address for accessing the stack cache is divided into two fixed parts: the base address (Base) and the offset (Offset). The base address is used to compare with the virtual base address of the stack cache to determine whether the stack cache access is hit. The offset is used to select the required content in the data field, and output the stack cache hit data.

The stack cache is organized in the form of a circular queue, caching contiguous regions. The stack cache judges the allocation and recovery of stack space by detecting the change of the top pointer of the stack. Stack space allocation, that is, the stack top pointer (sp) is reduced, and the stack space is directly allocated in the stack cache without retrieving the original value of the corresponding block from the low-level storage system. If the space in the stack cache is not enough to allocate a new stack space, in order to ensure the continuity of the stack cache, replace the data closest to the bottom of the stack in the stack cache. Stack space reclamation, that is, the stack top pointer (sp) is increased, and there is no need to write dirty reclaimed values to the low-level storage system.

Stack cache access, by performing a flag comparison to determine whether the stack cache is hit. To compare the stack cache flag, it is necessary to judge whether the access address belongs to the stack space, that is, the access address is greater than or equal to the address of the top of the stack and less than or equal to the address of the bottom of the stack, the base address of the access is the same as the virtual base address in the stack cache flag, and the effective The value of the bit field is 1. If the above conditions are met at the same time, the stack cache hits. Use the offset index data field to get the required data.

A stack cache miss, if the access address does not belong to the stack space, is handled by the data cache. The stack cache misses, and the access address belongs to the stack space. If the access address is less than the minimum address value in the current stack cache, that is, less than the address closest to the top of the stack, the minimum address in the stack cache is retrieved from the lower storage system. address to miss address data. The stack cache misses, and the access address belongs to the stack space. If the access address is greater than the maximum address value in the current stack cache, that is, greater than the address closest to the bottom of the stack, the maximum address in the stack cache is retrieved from the lower storage system. address to miss address data. This ensures the continuity of the stack cache.

When performing context switching, since the identification information of the process (including thread) is not recorded in the stack cache, the new process and the original process may be assigned the same virtual address, resulting in different physical addresses but the same virtual address. Therefore, in order to ensure data consistency during context switching, it is necessary to write all dirty data in the stack cache to the low-level storage system to release space for new processes. See US Patent No. 6167488, patent name "Stack caching circuit with overflow/underflow unit". Even if there is enough space in the stack cache for newer processes, dirty data must be written to the underlying storage system for correctness.

When the processor runs a single-process application, the stack cache shows good performance, but when running multi-user, multi-programming and multi-threading, due to the need for context switching Writing all dirty data in the stack cache to the low-level storage system at once is very expensive. After the context is switched back, the written data needs to be retrieved to the stack cache, and the cost of data transmission is very high. Therefore, a processor with a stack cache has good performance in a single-process application, but the effect is not ideal when running in a multi-process (including thread) environment, especially when context switching is frequently performed. The application of multi-user, multi-program and multi-thread is the development trend of microprocessor, which is inevitable.

Therefore, the deficiencies of the prior art require the design of a microprocessor stack cache suitable for context switching to reduce the average memory access time of the processor and greatly improve the memory access performance of the microprocessor in practical applications.

Contents of the invention

The purpose of the present invention is to overcome the deficiency that the stack cache in the prior art is not suitable for context switching, thereby providing a stack cache that can be used well when encountering frequent context switching in a multi-user, multi-program and multi-thread environment. Effect, and the hardware overhead is small, and the microprocessor stack cache and method suitable for context switching are easy to implement.

In order to achieve the above object, the present invention takes technical scheme as follows:

A stack cache suitable for context switching comprising:

Two or more stack cache blocks, the stack cache block is composed of a flag part, a data part and a control part;

An OR gate circuit, connected to the output end of the control part of the stack cache block, is used for the OR operation of each stack cache block hit signal, and outputs the result of the stack cache memory hit or miss;

a selector connected to the output of the control part of the stack cache block and connected to the output of the data part of the stack cache block for selecting the data of the hit stack cache block and outputting the stack cache block Cache hit data;

Further, the flag part of the stack cache block includes a virtual base address (Vbase) field, a valid bit (Valid) field, a physical base address (Pbase) field, a stack top address (Top) field, a stack bottom address (Bottom) domain, process address space identification (PASID, referred to as "process identification") domain;

Further, the data part of the stack cache block includes a data (Data) field and a dirty bit (W) field representing whether the data has been written;

Further, the control part of each stack cache block includes: at least three comparison circuits and an AND gate circuit; wherein, the input end of the first comparison circuit is connected to the virtual base address domain of the flag part and the stack cache The base address field connection of the access address is used to complete the judgment of whether the base address of the access is equal to the virtual base address of the sign part, and its output terminal is connected to the AND gate circuit; the input terminal of the second comparison circuit is connected to the stack of the sign part The top address domain is connected with the stack bottom address domain and the access address of the stack cache, and is used to complete the judgment of whether the access address belongs to the stack space, and its output terminal is connected to the AND gate circuit; the input terminal of the third comparison circuit is connected to the The process address space identification field of the above flag part is connected with the process address space identification field of the control register, and is used to complete the judgment whether the value of the process address space identification field is equal to the process address space identification of the access instruction, and its output terminal is connected to the described AND gate circuit; the valid bit field of the flag part is also connected to the input terminal of the AND gate circuit; the output terminal of the AND gate circuit is respectively connected to the OR gate circuit and the selector; the control register The content of is the process address space identification field; the control register is directly connected to the input end of the third comparison circuit of the stack cache memory.

The microprocessor stack cache memory suitable for context switching provided by the present invention, its input is the address of the access stack cache and the process address space identifier of the access instruction, and its output is the hit or miss signal and the hit data.

In the present invention, the value of the process address space identifier of the input access instruction comes from the control register of the microprocessor, and there is a corresponding process address space identifier for each memory access instruction. In the microprocessor, there are control registers that store the corresponding content of the process address space identifier, but the stored registers are different and the storage methods are different. For example, the MIPS processor uses the EntryHi register to store the address space identifier ASID (Address SpaceIdentifier), and the EntryLow register to store the global bit G (Global Bit), which together constitute the process address space identifier.

According to the above-mentioned microprocessor stack cache memory, a microprocessor stack cache storage method suitable for context switching comprises the following steps:

(1) Context switch, initialize the stack; if the corresponding process stack space is not allocated in the stack cache, record the address of the bottom of the initialization stack and the address of the top of the stack in the stack cache;

(2) stack space allocation; if the stack cache has distributable space, allocate new unused space in the stack cache, if the stack cache has no distributable space, then select the stack cache block to write back to the low-level storage system, And initialize the flag of the newly allocated stack cache block;

(3) Stack space reclaiming; there is no need to write the dirty reclaimed value to the low-level storage system, and directly reclaim and release the stack cache space;

(4) Instruction access stack cache; Carry out sign comparison, determine whether access stack cache hits according to sign comparison result; If hit, execute step (5); If not hit, execute step (6);

(5) The hit data that the stack cache block of output hit is carried out data index with offset and obtains;

(6) Determine whether the access address belongs to the stack space; if the access address does not belong to the stack space, it is processed by the data cache; if it belongs to the stack space, the stack cache block where the miss address is retrieved from the low-level storage system is at the bottom of the stack and the stack data between top addresses.

In the above step (2), if there is no space available for allocation in the stack cache, select the stack cache block to be written back to the low-level storage system, and the first-in-first-out strategy (FIFO), random strategy (Random) or least recently used strategy ( LRU). If the first-in-first-out strategy (FIFO) is adopted, the selection of the stack cache block that enters first can be realized by adding a field (Age) indicating the allocation time of the stack cache block to the sign of the stack cache block, and the newly allocated stack cache block is high-speed. The Age field of the cache block flag is cleared, and the Age field of other stack cache block flags is incremented by 1.

In above-mentioned step (4), described mark compares and refers to judging whether to satisfy following condition simultaneously: access address is greater than or equal to stack top address and is less than or equal to stack bottom address, and the base address of access is identical with the virtual base address in the stack cache block mark , the value of the valid bit field in the stack cache block flag with the same virtual base address and the access base address is 1, and the value of the process address space identification field is the same as the process address space identification of the access instruction; the access stack cache hit means The above conditions are met; if the above conditions are not met, the access stack cache misses.

The present invention has the following advantages:

1. The stack cache of the present invention is organized in blocks, and a special process address space identifier is used in the stack cache block flag to distinguish the address spaces of different processes. So this is a stack cache method that is specially designed for multi-user, multi-program, and multi-thread environments, and can well adapt to process (including thread) context switching.

2. The present invention only needs to add the PASID field and the Age field of the process address space identifier in the stack cache block flag, the hardware overhead is small, the control is simple, and the complexity of implementation is avoided.

Description of drawings

Figure 1 is a traditional stack cache structure and access diagram.

FIG. 2 is a stack cache structure and access diagram applicable to context switching according to an embodiment of the present invention.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

In FIG. 2, numeral 10 denotes a specific embodiment of a stack cache suitable for context switching according to the present invention. In this embodiment, the stack cache suitable for context switching consists of two stack cache blocks, an OR circuit 11 and a selector 12 . The input of this embodiment is the address 13 of the access stack cache and the process address space identifier 14 of the access instruction, and the output is a hit or miss signal and hit data. The data in each stack cache block is contiguous, similar to a traditional stack cache.

The two stack cache blocks have the same structure and are referred to as the first and second stack cache blocks for ease of expression, wherein the first stack cache block includes three parts: a flag part 15 , a data part 16 and a control part 17 . The sign part 15 of the first stack cache block includes: the virtual base address (Vbase) field is used to represent the virtual base address of the stack cache block, and the effective bit (Valid) field is used to represent whether the stack cache block is valid, the physical base address The (Pbase) domain is used to indicate the physical base address corresponding to the virtual base address of the stack cache block, the top address of the stack (Top) domain is used to indicate the top address of the stack of the process stack space to which the stack cache block belongs, and the bottom address of the stack (Bottom) domain It is used to indicate the stack bottom address of the process stack space to which the stack cache block belongs, the process address space identifier (PASID) field is used to indicate the process address space identifier of the process to which the stack cache block belongs, and the allocation time (Age) field is used to indicate the stack high speed. The allocation time of the cache block. Each entity of the stack cache mark part in the figure corresponds to a mark of a stack cache block, and number 18 in the figure represents the mark part of the second stack cache block, and its structure is the same as the mark part 15 of the first stack cache block. The data portion 16 of the first stack cache block includes a data (Data) field and a dirty bit (W) field indicating whether the data has been written. Each individual of the stack cache data in the figure represents the data of a stack cache block, and the number 19 in the figure represents the data part of the second stack cache, whose structure is the same as the data part 16 of the first stack cache block. The control section 17 of the first stack cache block includes a first comparison circuit 20 , a second comparison circuit 21 , a third comparison circuit 22 and an AND circuit 23 . The first comparison circuit 20 completes the judgment of whether the accessed base address is equal to the virtual base address of the first stack cache block, that is, judges whether Base=Vbase? . The second comparison circuit 21 completes the judgment of whether the access address belongs to the stack space, that is, judges whether Top≤Vaddr≤Bottom? . The third comparison circuit 22 completes the judgment of whether the value of the process address space identification field is equal to the process address space identification 14 of the access instruction. The value of the process address space identifier 14 (PASID) of the access instruction comes from the control register of the microprocessor, and there is a corresponding process address space identifier for each memory access instruction. The AND gate circuit 23 completes the AND operation of the output of the first comparison circuit 20, the output of the second comparison circuit 21, the output of the third comparison circuit 22 and the effective bit field of the flag part 15, determines whether the first stack cache block hits, and outputs the first Signal of a stack cache block hit or miss.

The OR gate circuit 11 completes the OR operation of the hit signals of each stack cache block, namely the first and second stack cache blocks in this embodiment, and outputs the result of the stack cache 10 hit or miss.

The selector 12 finishes selecting the data of the hit stack cache block, and outputs the stack cache hit data.

The address (Vaddr) 13 of the instruction to access the stack cache is divided into two fixed parts: a base address (Base) and an offset (Offset). Wherein the base address is used to compare with the virtual base address in the stack cache block mark to judge whether the stack cache access hits, and the offset is used to select the required content in the data field. The control register (Control Register) of the processor with process identification information specifies the process address space identification 14 of the access stack cache instruction, which is used to compare with the process address space identification in the stack cache block identification to identify the process where the access instruction is located .

In this embodiment, two stack cache blocks are taken as an example to illustrate the stack cache of the present invention. It should be understood that the stack cache according to the present invention may include multiple stack cache blocks, all of which have the same structure and Connection method, which is competent for those skilled in the art.

According to the stack cache memory provided in this embodiment, a microprocessor stack cache storage method suitable for context switching, the specific implementation steps are as follows:

(1) Context switch, initialize the stack; if there is no corresponding process stack space allocated in the stack cache, record the initialization stack bottom address and stack top address of the process in the stack cache. If the corresponding process stack space has been allocated in the stack cache, it means that the original process context is switched back, and no operation is required.

(2) Stack space allocation, that is, the pointer at the top of the stack decreases; if the stack cache has allocatable space, allocate new unused space in the stack cache. If there is no allocated space in the stack cache, the first-in-first-out stack cache block is selected to be written back to the low-level storage system according to the first-in-first-out strategy (FIFO), and the stack cache block is released to be allocated to a new process, and the new allocation is initialized The stack cache block flag. The selection of the stack cache block that enters first is realized by adding an allocation time (Age) field in the sign of the stack cache block, and the stack cache block with the largest Age value is the stack cache block that enters first. The Age field of the newly allocated stack cache block flag is cleared, and the Age field of other stack cache block flags is incremented by 1. If the process that needs to allocate stack space has already allocated a stack cache block, modify the stack top pointer in the stack cache block flag where the process is located, and clear the W field corresponding to the newly allocated stack space. If the address of the top of the stack is not in the stack cache block already allocated by the process, a new stack cache block where the address of the top of the stack is located is allocated. If the process that needs to allocate stack space has not allocated a stack cache block, allocate the stack cache block where the address of the new top of the stack is located. Vbase in the newly distributed stack cache block sign is set by the base address of the top of the stack, Pbase is set by the physical base address corresponding to the top of the stack base address, the process address space identification domain is set as the current process address space identification, and the bottom address of the stack ( Bottom) and stack top address (Top) are set as initializing stack bottom address and current stack top address, effective bit field (Valid) is set to 1, and the W domain initialization of stack cache block data is 0.

(3) Stack space reclamation, that is, the stack top pointer is increased; there is no need to write the dirty recovery value to the low-level storage system, directly reclaim and release the stack cache space, and modify the stack top pointer. If the stack space is all reclaimed, that is, the top pointer of the stack is equal to the value of the bottom pointer of the stack, then the value of the valid bit field (Valid) corresponding to the stack cache flag of the reclaimed stack space is 0.

(4) The instruction accesses the stack cache, performs flag comparison, and determines whether the stack cache hits according to the flag comparison result. Perform flag comparison, that is, judge whether to satisfy: (a) the access address is greater than or equal to the top address of the stack and less than or equal to the bottom address of the stack. (b) The base address of the access is the same as the virtual base address in the stack cache block tag. (c) The value of the valid bit (Valid) field in the stack cache block flag whose virtual base address is the same as the access base address is 1. (d) The base address is the same. The value of the process address space identifier field in the stack cache block flag is the same as the process address space identifier of the access instruction. If the above conditions are met simultaneously, the stack cache hits, and step (5) is executed; otherwise, step (6) is executed;

(5) Access hit, output the hit data obtained by indexing the data of the hit stack cache block with the offset.

(6) Access miss, judge whether the access address belongs to the stack space. It is processed in two cases: (a) The access address does not belong to the stack space and is processed by the data cache. (b) The access address belongs to the stack space, and the data of the stack cache block where the miss address is located is retrieved from the low-level storage system between the bottom and top addresses of the stack to ensure that the stack cache blocks are continuous. Allocates a stack cache block whose virtual base address is the same as the base address of the access address. Access the low-level storage system data return, set the Vbase in the stack cache block flag with the base address, set the Pbase in the flag with the physical base address corresponding to the base address, set the Valid field in the flag to 1, and fill the stack with the PASID in the control register The PASID field and the Age field in the cache block flag are cleared to zero, and the values of the Age field of other stack cache blocks are increased by 1. The returned data is stored in the Data field of the stack cache block data, and the corresponding W field is set to 0.

Three specific implementation examples are listed below. Through the examples of distribution and recovery of stack space, stack cache access hit and stack cache access miss, how to increase the process address in the stack cache block mark by the stack cache mentioned in the present invention with blocks as the organizational form The space identification domain distinguishes the space occupied by different processes and implements a stack cache method suitable for context switching.

Example 1. Stack space allocation, the virtual address is 32 bits, the stack bottom address is 0x7fff8000, the stack top address is reduced to 0x7fff7c00, the process address space identifier PASID in the control register is process 8, the stack cache block size is 4KB, each The Vbase of the stack cache block sign is 20 bits, 0ffset is 12 bits, and the stack cache size is 16KB, which is divided into 4 stack cache blocks. There is no stack cache block with process number 8 in the stack cache, and no stack cache block with flag effective bit 0. The space to be allocated is 1KB (0x7fff8000-0x7fff7c00). Find the stack cache block with the largest Age. The maximum Age of the second stack cache block is 8, the process number is 1, the address of the top of the stack is 0x7fff7b00, and the address of the bottom of the stack is 0x7fff8000 , Vbase is 0x7fff7, Valid is 1, and Pbase is 0x00ff7. Replace the stack cache block, starting from the top of the stack of process 1 to the bottom of the stack, that is, the offset is 0xb00 to 0xfff, if the corresponding item W of the indexed data field is 1, it is dirty, and write the corresponding item to the low-level storage system , the value of the write-back W field is 0, and the write-back address is Pbase with Offset. For example, the data whose Offset is 0xb00 is dirty, the Pbase is 0x00ff7, and the write-back address is 00ff7b00. The size of the stack cache block is 4KB, which is greater than or equal to the space that needs to be allocated, which is enough for the new process stack space to be allocated. Process 8 enters the second stack cache block, the Vbase of the mark is set to 0x7fff7, Valid is set to 1, PASID is set to the PASID in the control register, which is 8, Pbase is set to the physical base address 0x01ff7 corresponding to the virtual base address, and Bottom is set to It is 0x7fff8000, Top is set to 7fff7c00, and Age is set to 0. The Age of other stack cache blocks is incremented by 1. When the stack space is reclaimed, the address of the top of the stack is increased to 0x7fff7f00. It is not necessary to write the corresponding data in the stack cache to the low-level storage system, but only to change the top of the stack to 0x7fff7f00.

Example 2. The address Vaddr of the memory access instruction is 0x7fff7f80, the process address space identifier PASID in the control register is process 7, the stack cache block size is 4KB, the Vbase of each flag stack cache block is 20 bits, and the Offset is 12 bits , the stack cache size is 16KB, divided into 4 stack cache blocks. The base address (Base) of the access address is 0x7fff7, and the offset (Offset) is 0xf80. The virtual base address (Vbase) of the first stack cache block in the stack cache is 0x7fff7, the process address space identifier (PASID) is 7, the valid bit (Valid) is 1, the bottom address of the stack (Bottom) is 0x7fff8000, the stack The top address (Top) is 0x7fff7400, the physical base address (Pbase) is 0x1ff7, and the Age is 0. The data indexed at offset 0xf80 in the first stack cache block is 0x01fc00c0. Perform flag comparison, the access address is greater than or equal to the stack top address and less than or equal to the stack bottom address (0x7fff7400≤0x7fff7f80≤0x7fff8000), the access base address is equal to the virtual base address of the first stack cache block mark 0x7fff7f80, the first stack cache block mark The value of the valid bit field in is 1, and the value of the process address space identification field is 7 which is the same as the process address space identification of the access instruction. If the condition of stack cache hit is satisfied, the hit information is returned. Select the data 0x01fc00c0 obtained by using the offset index data field of the first stack cache block in the data field, and output the hit data 0x01fc00c0.

Example 3. The address Vaddr of the memory access instruction is 0x7fff7f80, the process address space identifier PASID in the control register is process 7, the stack cache block size is 4KB, the Vbase of each stack cache block flag is 20 bits, and the Offset is 12 bits , the stack cache size is 16KB, divided into 4 stack cache blocks. The base address (Base) of the access address is 0x7fff7, and the offset (Offset) is 0xf80. The virtual base address (Vbase) of the first stack cache block flag in the stack cache is 0x7fff6, the process address space identifier (PASID) is 7, the valid bit (Valid) is 1, and the stack bottom address (Bottom) is 0x7fff8000, The stack top address (Top) is 0x7fff6000, the physical base address (Pbase) is 0x1ff6, and the Age is 2. The access address is greater than or equal to the stack top address and less than or equal to the stack bottom address (0x7fff7400≤0x7fff7f80≤0x7fff8000), the value of the effective bit field in the flag is 1, and the value of the process address space identification field in the flag is the same as the process identifier of the access instruction, which is 7. But the access base address is not equal to the virtual base address 0x7fff6 of the first stack cache block, the process address space flag without other stack cache blocks is 7, and the effective bit of the third stack cache block flag is 0. When the stack cache misses, the access address belongs to the stack space, and the data between the stack top address and the stack bottom address of the stack cache block where the miss address is retrieved from the low-level storage system enters the third stack cache block, ensuring Stack cache blocks are contiguous. That is, the data from the virtual address 0x7fff7000 to 0x7fff7fff is retrieved, and the corresponding physical address is 0x01ff7000 to 0x01ff7fff. Access the low-level storage system data and return, put the Vbase in the third stack cache block mark as 0x7fff7, put Pbase as the corresponding physical base address 0x01ff7, put the Valid field as 1, fill the PASID with the address space identifier 7 in the control register, set The Age field is 0, and the value of the Age field of other stack cache blocks is increased by 1. The returned data is stored in the Data field of the third stack cache block data, and the corresponding W field is set to 0.

Through the description of the above embodiments, the advantages of the present invention are obvious. The invention overcomes the disadvantage that the traditional stack cache method is not suitable for process (including thread) context switching, and has good feasibility.

Finally, it should be noted that: the above embodiments are only used to illustrate and not limit the technical solutions of the present invention, although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be modified or Any modification or partial replacement without departing from the spirit and scope of the present invention shall fall within the scope of the claims of the present invention.

Claims (8)

1. A stack cache suitable for context switching, comprising: Two or more stack cache blocks, the stack cache block is composed of a flag part, a data part and a control part; An OR circuit, connected to the output end of the control part of the stack cache block, used for the OR operation of the hit signal of each stack cache block, and output the result of the stack cache memory hit or miss; a selector coupled to the output of said control portion of said stack cache block and coupled to the output of said data portion of said stack cache block for selecting data from a hit stack cache block , output stack cache hit data. 2. The stack cache memory suitable for context switching according to claim 1, wherein the structure of each of the stack cache blocks is the same. 3. The stack cache memory suitable for context switching according to claim 2, wherein the flag part of the stack cache block comprises a virtual base address field, an effective bit field, a physical base address field, and a stack top address Domain, stack bottom address domain, process address space identification domain. 4. The stack cache suitable for context switching according to claim 3, wherein the data part of each stack cache block includes a data field and a dirty bit field indicating whether the data has been written. 5. The stack cache memory suitable for context switching according to any one of claims 1-4, wherein the control part of each said stack cache block comprises: at least three comparison circuits and an AND Gate circuit; wherein, the input terminal of the first comparison circuit is connected with the virtual base address field of the flag part and the base address field of the access address of the stack cache, whether the base address for completing the access is equal to the virtual base address of the flag part Judgment, its output terminal is connected to the described AND gate circuit; The input terminal of the second comparison circuit is connected with the stack top address field and the stack bottom address field of the flag part and the access address of the stack cache, and is used to complete whether the access address Belonging to the judgment of the stack space, its output end is connected to the described AND gate circuit; the input end of the third comparison circuit is connected with the process address space identification domain of the said sign part, and the process address space identification domain of the control register of the microprocessor is connected with the The input end of the third comparison circuit is connected, and is used to complete the judgment whether the value of the process address space identification field is equal to the process address space identification of the access instruction, and its output end is connected to the described AND circuit; domain is also connected to the input of the AND circuit; the output of the AND circuit is respectively connected to the OR circuit and the selector. 6. A microprocessor stack cache storage method suitable for context switching, the steps are as follows: (1) Context switch, initialize the stack; if the corresponding process stack space is not allocated in the stack cache, record the address of the bottom of the initialization stack and the address of the top of the stack in the stack cache; (2) stack space allocation; if the stack cache has distributable space, allocate new unused space in the stack cache, if the stack cache has no distributable space, then select the stack cache block to write back to the low-level storage system, And initialize the flag of the newly allocated stack cache block; (3) Stack space reclaiming; there is no need to write the dirty reclaimed value to the low-level storage system, and directly reclaim and release the stack cache space; (4) Instruction access stack cache; Carry out sign comparison, determine whether access stack cache hits according to sign comparison result; If hit, execute step (5); If not hit, execute step (6); (5) The hit data that the stack cache block of output hit is carried out data index with offset and obtains; (6) Determine whether the access address belongs to the stack space; if the access address does not belong to the stack space, it is processed by the data cache; if it belongs to the stack space, the stack cache block where the miss address is retrieved from the low-level storage system is at the bottom of the stack and the stack data between top addresses. 7. according to the described microprocessor stack cache storage method that is applicable to context switching according to claim 6, it is characterized in that, in described step (2), if stack cache does not have distributable space, select stack cache block to write Returning to the low-level storage system, the strategy adopted is first-in-first-out strategy, random strategy or least-recently-used strategy; if the first-in-first-out strategy is adopted, the selection of the stack cache block that enters first is added to the flag of the stack cache block Realization of the field representing the allocation time of the stack cache block, the field of the newly allocated stack cache block flag is cleared, and the fields of other stack cache block flags are incremented by 1. 8. according to claim 6 or 7 described and be applicable to the microprocessor stack high-speed storage method of context switch, it is characterized in that, in described step (4), described sign comparison refers to judging whether to meet the following conditions simultaneously: The access address is greater than or equal to the stack top address, and less than or equal to the stack bottom address, the base address of the access is the same as the virtual base address in the stack cache block flag, and the valid bit field in the stack cache block flag with the virtual base address and the access base address is the same value of 1, the value of the process address space identification domain is the same as the process address space identification of the access instruction; the access stack cache hit means that the above conditions are met; if the above conditions are not met, the access stack cache misses.

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