CN100376081C - Delay locked loop capable of sharing counter and related method - Google Patents

Abstract

A delay locked loop is used to delay an input clock to lock a delayed clock. The delay locked loop includes: a frequency divider, used to divide the frequency of the input clock by N to generate a frequency division signal; a plurality of delayers, used to delay the input clock according to a count value to generate a plurality of delayed clocks with different delays in each delayer, wherein the plurality of delayers are connected in series with each other; a phase detector, coupled to a last delayer, used to detect a phase change between a last delayed clock and the input clock; and a counter, coupled to the phase detector and the frequency divider, used to generate the count value according to the phase change between the last delayed clock and the input clock.

Description

Delay-locked loop with shared counter and related method

technical field

The invention relates to a delay-locked loop, in particular to a delay-locked loop which can share a counter.

Background technique

A delay locked loop (DLL) is a circuit structure commonly used in computer operating environments to generate the required clocks. When the computing clock of the computer is gradually increasing, to implement the design of high-speed components, Then the clock distribution with low clock skew (low-skew) will become more and more important. Known computer systems include a processor capable of exchanging data with various types of memory and input/output units. Taking synchronous dynamic random access memory (SDRAM) as an example, its application is transmitted to a data processor in a pipeline, and the data transmission rate at this time is roughly equal to the operating frequency of the processor. In double data rate (DDR) memory applications, when a memory clock generates a rising edge (rising edge) or a negative edge (falling edge), double data rate synchronous random access memory (DDR SDRAM) will transfer data Output to a memory controller (memory Controller). The delay-locked loop used in the memory controller is designed to generate a delayed clock according to the memory clock to delay the timing of the memory controller's latch (latch) input clock, which means that the delay-locked loop can provide a delay amount to properly By shifting the original positive or negative edge of the memory clock, the memory controller can finally store the correct data in the latch device.

Please refer to FIG. 1 , which is a functional block diagram of a known delay locked loop (DLL) 100 . The delay locked loop 100 includes a multiplexer (multiplexer, MUX) 102, a frequency divider (frequency divider) 104, an inverter (inverter) 105, a phase detector (phase detector) 106, a counter (counter) 108, and a delay device (delay component) 110. For example, if the DLL 100 wants to lock a delayed clock that is 90 degrees behind the input clock (that is, is orthogonal to the input clock) and has a frequency of 500 MHz, the detailed operation is as follows.

Assume that the multiplexer 102 selects the clock CLK ₁ as the input clock IN with a frequency of 1 GHz, and the input clock IN is reversed by the inverter 105 to generate a reference clock REFCLK. The delayer 110 is composed of many delay chains (delay chain), and each delay chain corresponds to an input clock of a different operating frequency band. In other words, the delayer 110 can provide a broadband input clock application, and its application is known in the art. A brief description is as follows. Here, the delayer 110 provides the input clock _CLK1 with a predetermined delay amount dt to output a delayed clock FBCLK. As for which delay chain to use, it is selected by a selection signal SEL[1:0]. Here, the selection signal SEL[1:0] with a length of 2 bits can select 4 different delay chains, corresponding to inputs of different frequencies. clock. The phase detector 106 then compares the phases of the delayed clock FBCLK and the reference clock REFCLK, and if the phase of the reference clock REFCLK is ahead of that, a rising signal UP is triggered once. After the rising signal UP is input to the counter 108, the counter 108 receives the next edge of the frequency division signal CNTCLK4 (which can be triggered by a rising edge or a falling edge), and then outputs a count value DCNT[7:0] incremented by 1. The frequency division signal CNTCLK4 is generated by the frequency divider 104, where the frequency division multiplier is 4, that is, the period of the frequency division signal CNTCLK4 is 4 times that of the input clock CLK ₁ , but the frequency division multiplier is not limited, for example, the division The frequency multiplier can also be 8 or 16 times. The counter 108 keeps counting up to control the delay 110 to gradually increase the delay dt until the delayed clock output by the delay 110 lags behind the input clock by 180 degrees. Once the delayed clock lags behind the input clock by 180 degrees, it is known that the delay locked loop 100 enters the locked state, and then the frequency of the input clock is reduced from 1 GHz to 500 MHz, and the delayed clock lags behind the input clock by 90 degrees. At this time, the delayed clock output of the delayer is the desired delayed clock that is 90 degrees behind the input clock (that is, is orthogonal to the input clock) and has a frequency of 500 MHz.

However, as can be seen from the above description, each time the known delay-locked loop wants to generate the required delay clock, it needs to increase the operating frequency of the input clock by 2 times (for example, 500MHz becomes 1GHz), and output When the delayed clock is 180 degrees behind, the input clock of the actual operating frequency (for example, 500 MHz) is re-inputted to obtain a delayed clock that is 90 degrees behind the input clock (that is, is orthogonal to the input clock). The above-mentioned method is not only complicated and time-consuming, but also when the operating frequency of the input clock becomes higher and higher, the operation of multiplying the frequency of the input clock becomes more and more difficult. In addition, for the broadband delayer, since there are multiple delay chains, and the counter is designed to make the low-frequency delay chain operate normally, when the input clock increases, the delay chain corresponding to the high frequency will not match the counter. There is a risk of abnormal operation. In other words, known DLLs cannot properly share a counter without risking improper operation.

Contents of the invention

In view of this, it is an object of the present invention to provide a DLL that does not need to multiply the operating frequency of the input clock and can share a counter without risk of abnormal operation.

To achieve the above object, the present invention provides a delay locked loop that can share a counter to delay an input clock to lock a delayed clock. The delay-locked loop includes: a frequency divider, which is used to divide the frequency of the input clock by N to generate a frequency division signal; a plurality of delayers, which are used to delay the input clock according to a count value for each The delayer generates a plurality of delayed clocks with different delays, wherein the plurality of delayers are connected in series; a phase detector, coupled to a final delayer, is used to detect a phase transition between a final delayed clock and the input clock; and a The counter, coupled to the phase detector and the frequency divider, is used to generate the count value according to the phase transition between the last delayed clock and the input clock.

The present invention also provides a broadband delayer, which is used to delay an input clock according to a count value to generate a delayed clock. The wide-band delay device includes: a decoder, which is used to decode the count value and then output a decoded signal; a plurality of code detectors, which are used to generate multiple detection signals according to the count value; a delay chain, coupled to the decoder and the plurality of code detectors, for delaying the input clock according to the plurality of detection signals and the decoding signal to output a plurality of temporarily delayed clocks corresponding to different delay amounts; a multiplexer, coupled to the decoder and the plurality of delay chains, for selecting the delayed clock corresponding to the input clock frequency from the plurality of temporarily delayed clocks according to the decoder; and an output buffer , coupled to the multiplexer for outputting the delayed clock.

The present invention also provides a method for delaying an input clock to lock a delayed clock, which includes: dividing the frequency of the input clock by N to generate a frequency division signal; delaying the input clock according to a count value to generate different delaying a plurality of delayed clocks; detecting a phase transition of a last delayed clock and the input clock; and generating the count value according to the phase transition of the last delayed clock and the input clock; wherein the last delayed clock lags behind the input when locked Clock 180 degrees.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment will be exemplified below and described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a functional block diagram of a known delay locked loop.

FIG. 2 is a functional block diagram of an embodiment of a delay-locked loop that can share a counter in the present invention.

FIG. 3 is a circuit diagram of the delayer shown in FIG. 2 .

Description of reference symbols

100, 200 Delay locked loop

102, 202 Multiplexer

104, 204 frequency divider

105, 205 reverser

106, 206 phase detector

108, 208 counters

110, 210, 212 delayer

302 Decoder

304, 306, 308, 310 delay chain

312, 313, 314 code detectors

316 Multiplexer

318 output buffer

Detailed ways

FIG. 2 is a functional block diagram of an embodiment of a delay-locked loop 200 that can share a counter in the present invention. The delay locked loop 200 includes a multiplexer (multiplexer, MUX) 202, a frequency divider (frequency divider) 204, an inverter (inverter) 205, a phase detector (phase detector) 206, a counter (counter) 208, and a plurality of delay components (delay components) 210,212. By using the improved delayers 210, 212 of the present invention, the delay-locked loop 200 of the present invention can share the counter 208 in the environment of broadband input clock without the risk of abnormal operation, the details of which will be described later. For example, if the DLL 200 wants to lock to a delayed clock that is 90 degrees behind the input clock (ie, is orthogonal to the input clock) and has a frequency of 500 MHz, its operation is as follows.

Assume that the multiplexer 202 selects the clock CLK ₁ as the input clock IN with a frequency of 500 MHz, and the input clock IN is reversed by the inverter 205 to generate a reference clock REFCLK. The delayers 210 and 212 are composed of many delay chains, and each delay chain corresponds to an input clock of a different operating frequency band, and the detailed operating circuit will be described later. Here, the delayers 210 and 212 jointly provide the input clock IN with a predetermined delay amount dt to output a delayed clock FBCLK2. As for which delay chain to use for the delayers 210 and 212, it is selected by a selection signal SEL[1:0]. Here, the selection signal SEL[1:0] with a length of 2 bits can select 4 different delay chains, respectively Corresponding to input clocks of different frequencies. The phase detector 206 then compares the phases of the delayed clock FBCLK2 and the reference clock REFCLK, and if the phase of the reference clock REFCLK is ahead of that, a rising signal UP is triggered. After the rising signal UP is input to the counter 208, the counter 208 outputs the count value DCNT[7:0] incremented by 1 upon the next edge of the frequency division signal CNTCLK4 (which can be a rising edge or a falling edge). The frequency division signal CNTCLK4 is generated by the frequency divider 204, and the frequency division ratio is 4, but the frequency division ratio is also not limited. The counter 208 keeps counting up to control the delay dt provided by the delayers 210 and 212 to gradually increase until the delayed clock output by the delayer 212 lags behind the input clock by 180 degrees. Once the delayed clock FBCLK2 lags behind the input clock by 180 degrees, the delay locked loop 200 of the present invention enters into a locked state, and the delayed clock FBCLK2 output by the delayer 210 lags behind the input clock by 90 degrees.

It can be seen from the above description that when the delay locked loop 200 of the present invention wants to generate the required delay clock every time, it is not necessary to increase the operating frequency of the input clock by 2 times (for example, 500MHz becomes 1GHz) as the known delay locked loop, but can directly Input the input clock corresponding to the operating frequency into the delay locked circuit of the present invention, and then take out the delayed clock whose output is 90 degrees behind from the first delayer (delayer 210) after being locked (at this time, the second delayer lags behind the input clock 180 degrees).

The principle of the improved delayers 210 and 212 of the present invention, which can share the counter 208 in the environment of a broadband input clock without the risk of abnormal operation, will be described in detail below. The circuit configurations of the delayers 210 and 212 are identical, and the delayer 210 is taken as an example here.

FIG. 3 is a circuit diagram of the delayer 210 shown in FIG. 2 . The delayer 210 includes a decoder (decoder) 302, a plurality of delay chains 304, 306, 308, and 310, a plurality of code detectors (codedetector) 312, 313, and 314, a multiplexer 316, and an output Buffer (output buffer) 318. Each delay chain corresponds to input clocks of different operating frequency bands, and the configuration is as follows: there are 128 delay units in the delay chain 304, 64 delay units in the delay chain 306, 32 delay units in the delay chain 308, and 32 delay units in the delay chain 310. 16 delay units. In other words, the delay chain 304 to the delay chain 310 correspond to the operating frequency band from low frequency to high frequency. Please note that the operating frequency band corresponding to each delay chain is different from other delay chains, and the arrangement from low to high frequency is only for convenience of illustration. In addition, the number of delay units in the delay chain is determined by its corresponding operating frequency band. The higher the operating frequency band, the fewer the number of delay units. Conversely, the lower the operating frequency band, the greater the number of delay units.

The decoder 302 performs a decoding operation on the input count value DCNT[7:0] and then outputs a decoding signal to control each delay chain to delay the input clock IN to output temporarily delayed clocks corresponding to different delay amounts, and The control multiplexer 316 selects the most appropriate temporarily delayed clock corresponding to the operating frequency of the input clock from each delay chain, and then outputs the actually required delayed clock through the output buffer 318 .

Since the count value DCNT[7:0] of the counter matches the lowest frequency delay chain 304 (with 128 delay units in it), its count range is 0 to 127 (expressed in 8 bits). However, other delay chains (delay chain 306, delay chain 308, delay chain 310) do not match the count value DCNT[7:0] of the counter, so there is a possibility of abnormal operation, for example, for delay chain 306 Specifically, since there are only 64 delay units, when the count value DCNT[7:0] exceeds 63, the corresponding decoding signal may overflow when controlling the delay chain 306 to output the delay signal. Similarly, the delay chain 308 and the delay chain 310 also have overflow problems. The improved delayer of the present invention includes a plurality of code detectors 312 , 313 , and 314 to assist in solving the problem of overflow in decoding when controlling a higher-frequency delay chain. For example, for the delay chain 306, when the count value DCNT[7:0] exceeds 63, the code detector 312 outputs a detection signal so that the corresponding count value DCNT[7:0] keeps increasing, delaying Instead, the delay amount of the delayed clocks of the chain 306 gradually decreases to solve the overflow problem. Similarly, the code detectors 313 and 314 are respectively used to solve the problem when the delay chains 308 and 310 have count overflows, so as to assist the decoder 302 to correctly control each delay chain in the case of multiple delay chains .

When the delay-locked loop of the present invention wants to generate the required delay clock, it is not necessary to increase the operating frequency of the input clock by 2 times, and the input clock at the operating frequency can be processed directly. In addition, for broadband delayers with multiple delay chains, the delay locked loop of the present invention can also share a counter and maintain normal operation of higher frequency delay chains without increasing the number of counters.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is based on the claims of the present invention.

Claims (8)

1. a delay-locked loop is used for postponing an input clock to lock a delayed clock, and this delay-locked loop includes:

One frequency divider, be used for frequency with this input clock divided by N to produce a frequency division signal;

A plurality of delayers are used for postponing this input clock to produce the different a plurality of delayed clocks that postpone in each delayer according to a count value, and wherein these a plurality of delayers are connected in series each other;

One phase detectors are coupled to a last last delayer that is connected in series in these a plurality of delayers, are used for detecting the phase transition of a last delayed clock and this input clock; And

One counter is coupled to these phase detectors and this frequency divider, is used for producing this count value according to the phase transition of this last delayed clock and this input clock;

Wherein, this last delayer produces during locking should last delayed clock falls behind this input clock 180 and spends.

2. delay-locked loop as claimed in claim 1, it also includes one first multiplexer, is coupled to this frequency divider, these phase detectors and this a plurality of delayers, uses to select one from the clock of a plurality of different frequencies and be used as this input clock.

3. delay-locked loop as claimed in claim 1, wherein these a plurality of delayers include one first delayer and one second delayer, one first delayed clock that this first delayer produces falls behind this input clock 90 degree, and this last delayed clock that this second delayer produces falls behind this input clock 180 degree; This first delayed clock is the output of this delay-locked loop.

4. delay-locked loop as claimed in claim 1, wherein this delayer includes:

One decoder is used for doing to export a decoding signal after the decoding computing according to this count value;

A plurality of code detectors are used for producing a plurality of detection signals according to this count value;

A plurality of delay chains are coupled to this decoder and this a plurality of code detectors respectively, are used for postponing this input clock to export a plurality of temporary delay clocks of corresponding different retardations according to these a plurality of detection signals and this decoding signal;

One second multiplexer is coupled to this decoder and this a plurality of delay chains, is used for according to this delayed clock of selecting corresponding input clock frequency in oneself these a plurality of temporary delay clocks of this decoding signal; And

One output buffer is coupled to this second multiplexer, is used for exporting this delayed clock;

Wherein the lowest frequency delay chain in these a plurality of delay chains is controlled the retardation of this input clock to export a lowest frequency temporary delay clock according to this decoding signal, other delay chain is controlled the retardation of this input clock according to this decoding signal and corresponding a plurality of detection signals, wherein when the decoding signal will make indivedual delay chain generation overflow, corresponding detection signal promptly influenced this decoding signal and controls.

5. one kind postpones an input clock to lock the method for a delayed clock, and it includes:

With the frequency of this input clock divided by N to produce a frequency division signal;

Postpone this input clock to produce the different a plurality of delayed clocks that postpone according to a count value;

Detect the phase transition of a last delayed clock and this input clock; And

Phase transition according to this last delayed clock and this input clock produces this count value;

Wherein, this last delayed clock falls behind this input clock 180 degree during locking.

6. method as claimed in claim 5, it also comprises selects one from the clock of a plurality of different frequencies and is used as this input clock.

7. method as claimed in claim 5, wherein these a plurality of delayed clocks include one first delayed clock and a last delayed clock, when locking, this first delayed clock falls behind this input clock 90 degree, this last delayed clock falls behind this input clock 180 degree, and wherein this first delayed clock is the output of this delay-locked loop.

8. method as claimed in claim 5 wherein postpones this input clock and also includes with the step that produces arbitrary delayed clock:

This count value is done to export a decoding signal after the decoding computing;

Produce a plurality of detection signals according to this count value;

Postpone this input clock to export a plurality of temporary delay clocks of corresponding different retardations according to these a plurality of detection signals and this decoding signal;

In these a plurality of temporary delay clocks, select this delayed clock of corresponding input clock frequency according to this decoding signal; And

Export this delayed clock;

Wherein a lowest frequency temporary delay clock is exported control the retardation of this input clock according to this decoding signal after, and other temporary delay clock is exported control the retardation of this input clock according to this decoding signal and corresponding a plurality of detection signals after.

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