CN100375199C - semiconductor integrated circuit device - Google Patents

Abstract

To independently test a functional block, without enlarging the scale of a testing circuit. The device is provided with: a scan path, which includes parallel routes between outputs of a logic part 80 and inputs of a functional block 90 and a serial shift route for serially transmitting data, and is equipped with selectors 10, 11, and 12 and flip-flops 30, 31, and 32; and selectors 60, 61, and 62, which are connected to the serial shift route of the scan path, and switch the outputs of the functional block 90 and the serial shift route to be connected to the inputs of a logic part 81. The test data are shifted-in the functional block 90 from an SI (scan in) terminal via the selectors 60, 61, and 62, and the selectors 60, 61, and 62 are switched so as to output the data outputted from the functional block 90.

Description

Conductor integrated circuit device

Technical field

(the Random Access Memory: the random access memory) conductor integrated circuit device of etc. functional block, the logic section that is connected with this functional block and test circuit that they are tested that the present invention relates to possess RAM.

Background technology

Figure 21 represents to possess the circuit diagram of traditional conductor integrated circuit device of patent documentation 1 disclosed scanning test function.As shown in figure 21, this conductor integrated circuit device comprises: by the selector switch 10,11,12 of shift mode signal SM control; Trigger (FF) 30,31,32; Selector switch 50,51,52 by test mode signal TEST control; Logic section 80,81; RAM91.

Among Figure 21, selector switch 10,11,12 and trigger 30,31,32 constitute scanning pattern.This scanning pattern be have between the input of the output of logic section 80 and RAM91 IEEE Std parallel highway and from SI (scanning input) terminal to SO (scanning is exported) terminal till the memory circuit of the serial-shift path that is used for the serial transfer data.

The action of conductor integrated circuit device shown in Figure 21 then is described.

When moving usually, set shift mode signal SM=0 selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST=0, selector switch 50,51,52 is switched to " 0 " input end.That is, the data of logic section 80 outputs are selected by selector switch 10,11,12, are input to input terminal DI0, DI1, the DI2 of RAM91 via trigger 30,31,32.Here, though not shown, input clock in trigger 30,31,32.In addition, select by selector switch 50,51,52, be sent to logic section 81 from lead-out terminal DO0, the DO1 of RAM91, the data of DO2.Like this, when moving usually, RAM91 becomes the state that inserts 80,81 of logic section, carries out writing and reading of data.

During the sweep test of actuating logic portion 80,81, set test mode signal TEST=1, selector switch 50,51,52 is switched to " 1 " input end.In this state, because the data that selector switch 50,51,52 is selected and output is imported in " 1 " input end, thereby RAM91 is by bypass, and scanning pattern becomes the state that inserts 81 of logic section 80 and logic section.Under this state, control shift mode signal SM, the sweep test of actuating logic portion 80,81.

During the sweep test of actuating logic portion 81, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end.Because selector switch 10,11,12 is selected the data imported in " 1 " input ends, thereby if provide clock 3 times to trigger 30,31,32, then move by serial-shift from the test data of 3 bits of SI terminal, store trigger 30,31,32 into.Because test mode signal TEST=1, thereby the test data of 3 bits of trigger 30,31,32 storages offers logic section 81, by confirming the data of logic section 81 outputs, the sweep test of actuating logic portion 81.

During the sweep test of actuating logic portion 80, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end.The data of 3 bits that the logic section 80 of the input test data and the action that puts rules into practice is exported are selected by selector switch 10,11,12.If provide clock 1 time to trigger 30,31,32, then the data from 3 bits of logic section 80 store trigger 30,31,32 respectively into.At this moment, the data of trigger 32 storages 1 bit are exported from the SO terminal.Then set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end.If provide clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are exported the sweep test of actuating logic portion 80 by the serial-shift action from the serial of SO terminal.

In the conductor integrated circuit device shown in Figure 21, under the state of shift mode signal SM=1, move by serial-shift, test data from the SI terminal can be set to input terminal DI0, DI1, the DI2 of RAM91, but, do not have data load with lead-out terminal DO0, the DO1 of RAM91, DO2 output to trigger 30,31,32 and from the function that the SO terminal is read, can't carry out the independent test of RAM91.

Figure 22 represents to possess the circuit diagram of traditional conductor integrated circuit device of the independent test function of patent documentation 1 disclosed RAM91.It is to append by output to select the selector switch 60,61,62 of signal SELDO control and the selector switch of being controlled by ram test signal RAMTEST 70,71,72 on conductor integrated circuit device shown in Figure 21, in order to carry out the test pattern of RAM91.

Here, at " 1 " of selector switch 60,61,62 input end, import lead-out terminal DO0, the DO1 from RAM91, the data of DO2 respectively, in " 0 " of selector switch 60 input end input test data, import data respectively from trigger 30,31 at " 0 " of selector switch 61,62 input end from the SI terminal.In addition, in the data of " 0 " of selector switch 70,71,72 input end input from trigger 30,31,32, at " 1 " of selector switch 70,71,72 input end, input is from the ram test data of SID terminal.

The action of conductor integrated circuit device shown in Figure 22 then is described.

When moving usually, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST=0, selector switch 50,51,52 is switched to " 0 " input end, set ram test signal RAMTEST=0, selector switch 70,71,72 is switched to " 0 " input end.In this state, the data of logic section 80 outputs are via input terminal DI0, DI1, the DI2 of trigger 30,31,32 input RAM91.Here, input clock in trigger 30,31,32.In addition, be sent to logic section 81 from lead-out terminal DO0, the DO1 of RAM91, the data of DO2.Like this, when moving usually, RAM91 becomes the state that inserts 80,81 of logic section, carries out writing and reading of data.

During the sweep test of actuating logic portion 80, logic section 81, set test mode signal TEST=1, selector switch 50,51,52 is switched to " 1 " input end, set output and select signal SELDO=0, selector switch 60,61,62 is switched to " 0 " input end.RAM91 is by bypass in this state, and the scanning bus becomes the state that inserts 81 of logic section 80, logic section.Under this state, same with conductor integrated circuit device shown in Figure 21, control shift mode signal SM, scan test logic portion 80, logic section 81.

During testing ram 91, set ram test signal RAMTEST=1, selector switch 70,71,72 is switched to " 1 " input end, will supply with RAM91 as writing data from the ram test data of SID terminal.Here, the ram test data of 1 bit are offered RAM91 jointly as the data that write of 3 bits.That is, can be with " 000 " or " 111 " as writing the instantaneous RAM91 of offering of data.

By output select the selector switch 60,61,62 of signal SELDO control be used for from the data load of the test result of lead-out terminal DO0～DO2 of RAM91 to scanning pattern.Set output and select signal SELDO=1, selector switch 60,61,62 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, if provide clock 1 time to trigger 30,31,32, then from the data storage of the test result of lead-out terminal DO0～DO2 of RAM91 to trigger 30,31,32.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.Then set output and select signal SELDO=0, selector switch 60,61,62 is switched to " 0 " input end, if provide clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are read from the SO terminal by the serial-shift action, carry out fault verification by the proving installation of chip exterior or the self testing circuit of chip internal.

[patent documentation 1]

Te Kaiping 10-73641 communique (paragraph 0018～0039, Fig. 1, Fig. 4)

[disclosure of an invention]

[problem that invention solves]

Because traditional conductor integrated circuit device as above constitutes, thereby in the circuit shown in Figure 21, the problem of the independent test of the functional block that can't carry out RAM91 etc. is arranged.In addition, in the circuit shown in Figure 22, there is the scale of test circuit of the functional block of RAM91 etc. to become big problem.

The present invention is in view of solving the above problems, and its purpose is for providing: do not increase the scale of test circuit, can carry out the conductor integrated circuit device of the independent test of the functional block of RAM91 etc.

Summary of the invention

Conductor integrated circuit device of the present invention possesses: the functional block that connects between the 1st logic section and the 2nd logic section; Have between the input of the output of the 1st logic section and functional block IEEE Std parallel highway and in order to the scanning bus of the serial-shift path of serial transfer data, it by in order to the output of switching the 1st logic section and serial-shift path so that be connected to a plurality of the 1st selector switchs of input of functional block and a plurality of triggers of storage data constitute; A plurality of the 2nd selector switchs are connected on the serial-shift path of scanning pattern, in order to the output of handoff functionality piece with the serial-shift path so that be connected with the input of the 2nd logic section.Wherein, test data is displaced to functional block from the serial-shift path of scanning pattern via the 2nd selector switch, switches the 2nd selector switch, the data of functional block output are exported via the 2nd selector switch.

Thereby, have the scale that does not increase test circuit, separately the effect of test function block.

Description of drawings

Fig. 1 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 1.

Fig. 2 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 2.

Fig. 3 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 3.

Fig. 4 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 4.

Fig. 5 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 5.

Fig. 6 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 6.

Fig. 7 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 7.

Fig. 8 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 8.

Fig. 9 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 9.

Figure 10 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 10.

Figure 11 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 11.

Figure 12 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 12.

Figure 13 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 13.

Figure 14 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 14.

Figure 15 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 15.

Figure 16 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 16.

Figure 17 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 17.

Figure 18 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 18.

Figure 19 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 19.

Figure 20 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 20.

Figure 21 is the structural circuit figure of traditional conductor integrated circuit device.

Figure 22 is the structural circuit figure of traditional conductor integrated circuit device.

Symbol description

10,11,12,13 selector switchs; 10a, 11a, 12a AND-OR composite gate type selector switch; 20,21,22 phase inverters; 30,31,32,33 triggers; 40,41,42,43 phase inverters; 40a, 41a, 42a phase inverter; 60,61,62,63 selector switchs; 60a, 61a, 62a AND-OR composite gate type selector switch; 60b, 61b, 62b AND-NOR composite gate type selector switch; 80,81 logic section; 90 functional blocks; 91 RAM; 91a RAM; 100 selector switchs; 110,111,112,113,114,115,116 gate circuits; 110a, 110b, 110c gate circuit; 120 Reflector generative circuits; 121 phase inverters; 122 AND circuit; 123 OR circuit; 124 AND circuit; 125 triggers; 130 OR circuit.

Embodiment

Below, the embodiment of the invention is described.

Embodiment 1

Fig. 1 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 1.As shown in Figure 1, this conductor integrated circuit device comprises: by the selector switch 10,11,12 (the 1st selector switch) of shift mode signal SM control; Trigger (FF) 30,31,32; Selector switch 60,61,62 (the 2nd selector switch) by test mode signal TEST2 control; Logic section 80 (the 1st logic section), logic section 81 (the 2nd logic section); Functional block 90.Here, functional block 90 is not only RAM, also comprises the various logic functions piece of computing circuit, interface circuit, storage block etc.

Among Fig. 1, constitute the scanning bus by selector switch 60,61,62, selector switch 10,11,12 and trigger 30,31,32.This scanning pattern is a memory circuit, have between the input of the output of logic section 80 and functional block 90 IEEE Std parallel highway and in order to carry out the serial-shift path of serial transfer data to SO (scanning is exported) terminal from SI (scanning input) terminal, selector switch 60,61,62 is connected with the serial-shift path of scanning pattern.

Among Fig. 1, change the insertion position of the selector switch 50,51,52 of traditional Figure 21,, lead-out terminal DO0, the DO1 of functional block 90, the data load of DO2 output are arrived scanning pattern as selector switch 60,61,62.Thereby, do not increase the test circuit scale and just can carry out the independent test of functional block 90.

Then explanation action.

When moving usually, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.In this state, the data of logic section 80 outputs are selected by selector switch 10,11,12, are input to input terminal DI0, DI1, the DI2 of functional block 90 via trigger 30,31,32.Here, input clock in trigger 30,31,32.

In addition, select by selector switch 60,61,62, be sent to logic section 81 from lead-out terminal DO0, the DO1 of functional block 90, the data of DO2.Like this, when moving usually, functional block 90 becomes the state that inserts 80,81 of logic section, computing that puts rules into practice and data processing.

During the sweep test of actuating logic portion 80,81, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.In this state, functional block 90 is by bypass, and scanning pattern becomes the state that inserts 81 of logic section 80 and logic section.Under this state, control shift mode signal SM, the sweep test of actuating logic portion 80,81.

During the sweep test of actuating logic portion 81, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, if provide clock 2 times to trigger 30,31,32, then the test data from 2 bits of SI terminal stores trigger 30,31 into by the serial-shift action.

Owing to set test mode signal TEST2=1, thereby, the test data of following 1 bit of SI terminal is selected by selector switch 60, to logic section 81 inputs, the test data of each 1 bit of trigger 30,31 storages is selected by selector switch 61,62 respectively, to logic section 81 input, the sweep test of the test data actuating logic portion 81 by adding up to 3 bits.

During the sweep test of actuating logic portion 80, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, if provide clock 1 time to trigger 30,31,32, then the data from 3 bits of the test result of the logic section 80 of having imported test data store trigger 30,31,32 respectively into.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, as if providing clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.This occasion can store the next test data to logic section 81 into trigger 30,31 from the SI terminal.In addition, the sweep test of this logic section 80 and logic section 81 repeatedly repeats when the test data to input changes.

When carrying out the test of functional block 90, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end.Set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, if provide clock 3 times to trigger 30,31,32, then the test data from 3 bits of SI terminal stores trigger 30,31,32 into by the serial-shift action, to input terminal DI0, DI1, the DI2 input of functional block 90.The action of functional block 90 carry out desired, the data of test result are from lead-out terminal DO0, DO1, DO2 output.

Then set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end, if provide clock 1 time to trigger 30,31,32, then from the data storage of the test result of lead-out terminal DO0, the DO1 of functional block 90, DO2 to trigger 30,31,32.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, as if providing clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.In addition, the test of this functional block 90 repeatedly repeats when the test data from the input of SI terminal is changed.

As mentioned above, according to this embodiment 1, the scale that can obtain not increase test circuit is the effect of test function block 90 separately just.

Embodiment 2

Fig. 2 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 2.Among this embodiment 2, as shown in Figure 2, the functional block among Fig. 1 of embodiment 1 90 is altered to RAM91, phase inverter 20,21,22 is inserted the serial-shift path of scanning pattern.By this phase inverter 20,21,22, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 ").Thereby, when carrying out the test of RAM91, can carry out such test easily, that is, next cycle writes " 111 " after writing " 000 ", or is writing the test that " 111 " back next cycle writes " 000 ".

Then explanation action.

When common action, it doesn't matter for phase inverter 20,21,22, and except the functional block 90 of embodiment 1 only was altered to RAM91, other were identical with embodiment 1.In addition, also basic identical when the sweep test of logic section 80,81 with embodiment 1, can consider the data of test data and test result anti-phase or noninverting by phase inverter 20,21,22.

The test case of RAM91 is described.

At first, the situation that writes test of RAM91 being carried out primary data is described.Set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.If provide clock 3 times,, store trigger 30,31,32 into from the test data of 3 bits of SI terminal then by the serial-shift action to trigger 30,31,32.But, because storage is by the anti-phase test data of phase inverter 20,21,22 in the trigger 30,32, thereby, with test data " 010 " from SI terminal when input displacement, the test data of the output of trigger 30,31,32 becomes " 111 ", and test data " 111 " is input to input terminal DI0, DI1, the DI2 of RAM91.

If from the follow-up test data " 101010... " of SI terminal displacement input, then be input to the test data state of " 111 " and the state of " 000 " repeatedly of input terminal DI0, DI1, the DI2 of RAM91.When the test data " 111 " of setting expectation or " 000 ", RAM91 is write.Like this, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 ").In addition, this test data repeatedly repeats when being written in of RAM91 changed the address.

Then, the situation of the specific address execution of RAM91 being read test is described.Set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.If test is read in the particular address execution to RAM91, then the data of test result are exported from selector switch 10,11,12 via selector switch 60,61,62 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91.If provide clock 1 time to trigger 30,31,32, then the data of test result store trigger 30,31,32 respectively into.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.If provide clock 2 times,, the data of each 1 bits of trigger 30,31 storages from SO terminal displacement output, are confirmed to add up to the content of the data of 3 bits then by the serial-shift action to trigger 30,31,32.But because the data of trigger 30 storage are by phase inverter 21,22, the data of trigger 31 storages are by behind the phase inverter 22, from SO terminal serial output, thereby must consider that this situation tests.In addition, the test of reading of this RAM91 repeatedly repeats when the address is changed.

In addition, also can omit phase inverter 20, this occasion can make from the test data of SI terminal displacement input and above-mentioned occasion anti-phase.

If relatively this embodiment 2 and traditional Figure 22, then the selector switch 50,51,52 of Figure 22 and selector switch 70,71,72 become unnecessary.

As mentioned above, according to this embodiment 2, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, simultaneously, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), can obtain efficiently to carry out the effect of the test of RAM91.

Embodiment 3

Fig. 3 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 3.Among this embodiment 3, as shown in Figure 3, the phase inverter 20,21,22 among Fig. 2 of replacement embodiment 2 inserts phase inverter 40,41,42 on the serial-shift path of scanning pattern.By this phase inverter 40,41,42, the test data that writes RAM91 can be switched 1 clock period and be helped 0 (" 000 ") or complete 1 (" 111 ").

Then explanation action.

Usually during action, it doesn't matter for phase inverter 40,41,42, and except only the functional block 90 of embodiment 1 being altered to the RAM91, other are identical with embodiment 1.In addition, also basic identical when the sweep test of logic section 80,81 with embodiment 1, can consider the data of test data and test result anti-phase or noninverting by phase inverter 40,41,42.

The situation of the test of RAM91 is described.

At first, the situation that writes test of RAM91 being carried out primary data is described.Set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.If provide clock 3 times,, store trigger 30,31,32 into from the test data of 3 bits of SI terminal then by the serial-shift action to trigger 30,31,32.But, because storage is by the anti-phase test data of phase inverter 40,41,42 in the trigger 30,32, thereby with test data " 010 " from SI terminal when input displacement, the test data of the output of trigger 30,31,32 becomes " 111 ", to input terminal DI0, DI1, the DI2 input test data " 111 " of RAM91.

If from the follow-up test data " 101010... " of SI terminal displacement input, then be input to the test data state of " 111 " and the state of " 000 " repeatedly of input terminal DI0, DI1, the DI2 of RAM91.When the test data " 111 " of setting expectation or " 000 ", RAM91 is write.Like this, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 ").In addition, this test data repeatedly repeats when being written in of RAM91 changed the address.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.If test is read in the particular address execution to RAM91, then the data of test result are exported from lead-out terminal DO0, DO1, the DO2 of RAM91, and are anti-phase by phase inverter 40,41,42 respectively via selector switch 60,61,62, from selector switch 10,11,12 outputs.If provide clock 1 time to trigger 30,31,32, then the oppisite phase data of test result stores trigger 30,31,32 respectively into.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then, with input terminal DI0, DI1, the DI2 of the oppisite phase data input RAM91 of the test result of trigger 30,31,32 storage, write the oppisite phase data of test result to RAM91.For example, be the occasion of " 000 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 output, write test data " 111 " at next cycle to RAM91.

Then, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.As if providing clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.But because the data of trigger 30 storage are by phase inverter 41,42, the data of trigger 31 storages are by behind the phase inverter 42, from SO terminal displacement output, thereby must consider that this situation tests.In addition, the test of reading and write of this RAM91 repeatedly repeats when the address is changed.

As mentioned above, according to this embodiment 3, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, simultaneously, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), can obtain efficiently to carry out the effect of the test of RAM91.

Embodiment 4

Fig. 4 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 4.Among Fig. 1 of embodiment 1, the output of trigger 30,31,32 is imported to input terminal DI0, DI1, the DI2 of functional block 90, and among this embodiment 4, as shown in Figure 4, the output of selector switch 10,11,12 is imported to input terminal DI0, DI1, the DI2 of functional block 90.

Then explanation action.

When moving usually, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.The data of logic section 80 outputs are selected by selector switch 10,11,12, and directly input terminal DI0, DI1, the DI2 to functional block 90 imports.

In addition, select by selector switch 60,61,62, be sent to logic section 81 from lead-out terminal DO0, the DO1 of functional block 90, the data of DO2.Like this, when moving usually, functional block 90 becomes the state that inserts 80,81 of logic section, computing that puts rules into practice and data processing.Among this embodiment 4, when moving usually, it doesn't matter for trigger 30,31,32, also can not provide clock in the trigger 30,31,32.

The position of the trigger 30,31,32 among Fig. 4 of the Fig. 1 of embodiment 1 and embodiment 4 in the serial-shift path of scanning pattern is identical, thereby the sweep test of logic section 80,81 is identical with embodiment 1.

When carrying out the test of functional block 90, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.If provide clock 2 times,, store trigger 30,31 into from the test data of 2 bits of SI terminal then by the serial-shift action to trigger 30,31,32.

Test data from following 1 bit of SI terminal is selected by selector switch 60 and selector switch 10, to the input terminal DI0 of functional block 90 input, the test data of each 1 bit of trigger 30,31 storages is selected by selector switch 61,62 and selector switch 11,12 respectively, to input terminal DI1, the DI2 of functional block 90 input.The action of functional block 90 carry out desired is with lead-out terminal DO0, DO1, the DO2 output from functional block 90 of the data of test result.

Then, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end, if provide clock 1 time to trigger 30,31,32, then from the data storage of the test result of lead-out terminal DO0, the DO1 of functional block 90, DO2 to trigger 30,31,32.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, as if providing clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.In addition, the test of this functional block 90 repeatedly repeats when the test data from the input of SI terminal is changed.

As mentioned above, according to this embodiment 4, can be under the situation of the scale that does not increase test circuit test function block 90 separately, simultaneously, when action usually, do not provide clock can finish the effect of test to trigger 30,31,32 even can obtain yet.

Embodiment 5

Fig. 5 is that the formation of the conductor integrated circuit device of the embodiment of the invention 5 is circuit diagrams.Among Fig. 2 of embodiment 2, the output of trigger 30,31,32 is imported to input terminal DI0, DI1, the DI2 of RAM91, shown in Figure 5 among this embodiment 5, the output of selector switch 10,11,12 is imported to input terminal DI0, DI1, the DI2 of RAM91.

Then explanation action.Usually during action, it doesn't matter for phase inverter 20,21,22 and trigger 30,31,32, and except only the functional block 90 of embodiment 4 being altered to RAM91, other are identical with embodiment 4, also can not provide clock to trigger 30,31,32.In addition, also basic identical when the sweep test of logic section 80,81 with embodiment 4, can consider by phase inverter 20,21,22 data of test data and test result are anti-phase or noninverting.

The test case of RAM91 is described.At first, the situation that writes test of RAM91 being carried out primary data is described.Set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.If provide clock 2 times,, store trigger 30,31 into from the test data of 2 bits of SI terminal then by the serial-shift action to trigger 30,31,32.

But, because the anti-phase test data of trigger 30 storages, thereby during from SI terminal displacement input " 10 ", the output of trigger 30,31 becomes " 11 ".To the input terminal DI1 of RAM91 input, to the input terminal DI2 of RAM91 input, the test data of input terminal DI1, the DI2 of input RAM91 becomes " 00 " via phase inverter 22 in the output of trigger 31 via phase inverter 21 in the output of trigger 30.In addition, if provide follow-up test data " 1 " from the SI terminal, then import via the input terminal DI0 of phase inverter 20 to RAM91, input terminal DI0, the DI1 of input RAM91, the test data of DI2 become " 000 ".

If from the follow-up test data " 101010... " (" 1 " of beginning is aforesaid test data " 1 ") of SI terminal displacement input, the test data of input terminal DI0, DI1, DI2 of then importing RAM91 in the state of the state of " 000 " and " 111 " alternately repeatedly.When desired data " 000 " or " 111 " input, execution writes to RAM91.Like this, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 ").In addition, this test data repeatedly repeats when being written in of RAM91 changed the address.

It is identical with embodiment 2 that the situation of reading test is carried out in the specific address of RAM91.In addition, identical with embodiment 2, also phase inverter 20 can be omitted.

As mentioned above, according to this embodiment 5, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), efficiently carry out the test of RAM91, simultaneously, even do not provide clock also can finish the effect of test can obtain to move usually the time to trigger 30,31,32.

Embodiment 6

Fig. 6 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 6.Among Fig. 3 of embodiment 3, the output of trigger 30,31,32 is imported to input terminal DI0, DI1, the DI2 of RAM91, and among this embodiment 6, as shown in Figure 6, the output of selector switch 10,11,12 is imported to input terminal DI0, DI1, the DI2 of RAM91.

Then explanation action.Usually during action, it doesn't matter for phase inverter 40,41,42 and trigger 30,31,32, and except only the functional block 90 of embodiment 4 being altered to the RAM91, other are identical with embodiment 4, also can not provide clock to trigger 30,31,32.In addition, also basic identical when the sweep test of logic section 80,81 with embodiment 4, can consider by phase inverter 40,41,42 data of test data and test result are anti-phase or noninverting.

The test case of RAM91 is described.RAM91 is carried out the situation that writes test of primary data, and except phase inverter 20,21,22 only becomes the phase inverter 40,41,42, other are identical with embodiment 5.

Then explanation is carried out the situation of reading and write test to the specific address of RAM91.Set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.If test is read in the specific address execution to RAM91, then the data of test result are exported to lead-out terminal DO0, DO1, the DO2 of RAM91, and are anti-phase by phase inverter 40,41,42 via selector switch 60,61,62 respectively, from selector switch 10,11,12 outputs.

Then, with input terminal DI0, DI1, the DI2 input of the oppisite phase data of the test result of selector switch 10,11,12 output, write the oppisite phase data of test result to RAM91 to RAM91.For example, the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 output are the occasion of " 000 ", write test data " 111 " at next cycle to RAM91.

Then, if provide clock 1 time to trigger 30,31,32, then the oppisite phase data of the test result of selector switch 10,11,12 outputs stores trigger 30,31,32 respectively into.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then set TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.As if providing clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.But because the data of trigger 30 storage are by phase inverter 41,42, the data of trigger 31 storages are by behind the phase inverter 42, from SO terminal displacement output, thereby must consider that this situation tests.In addition, the test of reading and write of this RAM91 repeatedly repeats when the address is changed.

As mentioned above, according to this embodiment 6, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch and help 0 that (" " 000 ") or complete 1 (" 111 "); efficiently carry out the test of RAM91; simultaneously do not provide the effect of clock to trigger 30,31,32 in the time of can obtaining to move usually in the test data that 1 clock period will write RAM91.

Embodiment 7

Fig. 7 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 7.Among this embodiment 7, as shown in Figure 7, in Fig. 6 of embodiment 6, append the selector switch 100 (the 3rd selector switch) that the data that will output to the SO terminal feed back to the SI terminals side.This selector switch 100 is controlled by loop enable signal LOOPEN.Fig. 5 of Fig. 3 of Fig. 2 of embodiment 2, embodiment 3, embodiment 5 can append selector switch 100 too.

Then explanation action.

When moving usually, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.Usually during action, it doesn't matter for phase inverter 40,41,42 and trigger 30,31,32, and except only the functional block 90 of embodiment 4 being altered to RAM91, other are identical with embodiment 4, also can not provide clock to trigger 30,31,32.

In addition, when the sweep test of logic section 80,81, set loop enable signal LOOPEN=0, selector switch 100 is switched to " 0 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.The sweep test of this logic section 80,81 is also basic identical with embodiment 4, can consider by phase inverter 40,41,42 data of test data and test result are anti-phase or noninverting.

The situation of the test of RAM91 is described.At first, the situation that writes test of RAM91 being carried out primary data is described.Set loop enable signal LOOPEN=0, selector switch 100 is switched to " 0 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.

If provide clock 3 times,, store trigger 30,31,32 into from the test data of 3 bits of SI terminal then by the serial-shift action to trigger 30,31,32.But, because the anti-phase test data of trigger 30,32 storages, thereby during from SI terminal displacement input " 010 ", the output of trigger 30,31,32 becomes " 111 ".In this state, the next test data of SI terminal is anti-phase by phase inverter 40, be sent to the input terminal DI0 of RAM91, the data of the output of trigger 30 " 1 " are anti-phase by phase inverter 41, be sent to the input terminal DI1 of RAM91, the data of the output of trigger 31 " 1 " are anti-phase by phase inverter 42, are sent to the input terminal DI2 of RAM91.

Then, if set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, and then the data of the output of trigger 32 " 1 " are sent to the input terminal DI0 of RAM91 via phase inverter 40, and input terminal DI0, the DI1 of RAM91, the data of DI2 become " 000 ".Under the state of loop enable signal LOOPEN=1,, change input terminal DI0, the DI1 of RAM91, the data of DI2, make its state of " 000 " and state of " 111 " repeatedly by phase inverter 40,41,42 at every turn when trigger 30,31,32 provides clock.When the test data " 000 " of setting expectation or " 111 ", execution writes to RAM91.Being written in when changing the address of the RAM91 of this test data repeatedly repeats.

It is identical with embodiment 6 that the situation of reading and write test is carried out in the specific address of RAM91.This occasion, the setting of loop enable signal LOOPEN can be arbitrarily.

In addition, among this embodiment 7, when writing of RAM91 execution primary data tested, from SI terminal displacement input test data, make the output of trigger 30,31,32 become " 111 ", also can make the output of trigger 30,31,32 become " 000 " from SI terminal displacement input test data.

As mentioned above, according to this embodiment 7, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), efficiently carry out the test of RAM91, simultaneously, even do not provide clock also can finish the effect of test can obtain to move usually the time to trigger 30,31,32.

In addition, according to this embodiment 7, set loop enable signal LOOPEN=0, make trigger 30,31,32 become the test data of " 111 " or " 000 " from SI terminal displacement input, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, be sent to RAM91 input terminal DI0～DI2 data at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

Embodiment 8

Fig. 8 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 8.Among this embodiment 8, as shown in Figure 8, in Fig. 7 of embodiment 7, append in order to monitor at short notice from the gate circuit 110 of the data of the test result of RAM91 output.This gate circuit 110 is same values in order to the data of the output of detection selector switch 60,61,62.Among Fig. 8, use the AND door as gate circuit 110, but also can use one of NAND door, OR door, NOR door.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 7.Action when by the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 7.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are sent to the input of gate circuit 110 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91 via selector switch 60,61,62.At this moment, if the data of test result " 111 ", then the supervisory signal MONI of gate circuit 110 outputs becomes " 1 ", if the data of test result are not " 111 ", then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

In addition, anti-phase from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 by phase inverter 40,41,42, offer input terminal DI0, DI1, the DI2 of RAM91.Then, when the oppisite phase data of this test result is write RAM91, if provide clock to trigger 30,31,32, the oppisite phase data of trigger 30,31,32 these test results of storage then.

Then, if set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, then the oppisite phase data of the test result of trigger 30,31,32 storages is sent to the input of gate circuit 110 respectively via selector switch 60,61,62.The data of test result " if 000 ", then the input of gate circuit 110 becomes " 111 ", and the supervisory signal MONI of gate circuit 110 outputs becomes " 1 ", if the data of test result are not " 000 ", then supervisory signal MONI becomes " 0 ".Thereby, by checking supervisory signal MONI, even whether the data of test result of exporting lead-out terminal DO0, DO1, the DO2 output of yet decidable RAM91 from the displacement of SO terminal are not " 000 ".In addition, the test of reading and write of this RAM91 repeatedly repeats in the change address.

As mentioned above, according to this embodiment 8, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), efficiently carry out the test of RAM91, simultaneously, even do not provide clock also can finish the effect of test can obtain to move usually the time to trigger 30,31,32.

In addition, according to this embodiment 8, set loop enable signal LOOPEN=0, import the test data that makes trigger 30,31,32 become " 111 " or " 000 " from the displacement of SI terminal, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, input terminal DI0～DI2 of RAM91 at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

And, according to this embodiment 8, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

Embodiment 9

Fig. 9 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 9.Among this embodiment 9, as shown in Figure 9, the gate circuit among Fig. 8 of embodiment 8 110 as gate circuit 111, is moved to the outgoing side of phase inverter 40,41,42 from the outgoing side of selector switch 60,61,62.This gate circuit 111 is same values in order to the data of the output of detection phase inverter 40,41,42.Among Fig. 9, use the AND door as gate circuit 111, but also can use one of NAND door, OR door, NOR door.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 7.Action when by the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 7.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are exported from lead-out terminal DO0, DO1, the DO2 of RAM91, and are anti-phase by phase inverter 40,41,42 via selector switch 60,61,62 respectively, are sent to the input of gate circuit 111.At this moment, if the data of test result " 000 ", then the supervisory signal MONI of gate circuit 111 outputs becomes " 1 ", if the data of test result are not " 000 ", then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 000 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

In addition, anti-phase from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 by phase inverter 40,41,42, offer input terminal DI0, DI1, the DI2 of RAM91.Then, when the oppisite phase data of this test result is write RAM91, if provide clock 1 time to trigger 30,31,32, the oppisite phase data of trigger 30,31,32 these test results of storage then.

Then, if set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, then the oppisite phase data of the test result of trigger 30,31,32 storages is sent to selector switch 60,61,62 respectively.The oppisite phase data of the test result of the output of selector switch 60,61,62 is anti-phase again by phase inverter 40,41,42, is sent to the input of gate circuit 111.The data of test result " if 111 ", then the input of gate circuit 111 becomes " 111 ", and the supervisory signal MONI of gate circuit 111 outputs becomes " 1 ", if the data of test result are not " 111 ", then supervisory signal MONI becomes " 0 ".Thereby, by checking supervisory signal MONI, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even do not export also decidable from the displacement of SO terminal.In addition, the test of reading and write of RAM91 repeatedly repeats in the change address.

As mentioned above, according to this embodiment 9, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), efficiently carry out the test of RAM91, simultaneously, even do not provide clock also can finish the effect of test can obtain to move usually the time to trigger 30,31,32.

In addition, according to this embodiment 9, set loop enable signal LOOPEN=0, import the test data that makes trigger 30,31,32 become " 111 " or " 000 " from the displacement of SI terminal, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, input terminal DI0～DI2 of RAM91 at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

And, according to this embodiment 9, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

Embodiment 10

Figure 10 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 10.Among this embodiment 10, as shown in figure 10, the gate circuit among Fig. 8 of embodiment 8 110 is moved to the outgoing side of selector switch 10,11,12 as the outgoing side of gate circuit 112 from selector switch 60,61,62.This gate circuit 112 is same values in order to the data of the output of detection selector switch 10,11,12.Among Figure 10, use the AND door as gate circuit 112, but also can use one of NAND door, OR door, NOR door.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 7.Action when by the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 7.And, specific address execution to RAM91 is read and is write in the situation of test, except the data of the test result of gate circuit 112 by judging lead-out terminal DO0, DO1 from RAM91, DO2 from the data of selector switch 10,11,12 output were " 000 " or " 111 ", other were identical with embodiment 9.

As mentioned above, according to this embodiment 10, can obtain the effect identical with embodiment 9.

Embodiment 11

Figure 11 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 11.Among this embodiment 11, as shown in figure 11, the gate circuit among Fig. 8 of embodiment 8 110 is moved as the outgoing side of gate circuit 113 from the output lateral trigger 30,31,32 of selector switch 60,61,62.This gate circuit 113 is same values in order to the data of the output of detection triggers 30,31,32.Among Figure 11, use the AND door as gate circuit 113, but also can use one of NAND door, OR door, NOR door.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 7.Action when by the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 7.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are to lead-out terminal DO0, DO1, the DO2 output of RAM91, respectively via selector switch 60,61,62 and selector switch 10,11,12, anti-phase by phase inverter 40,41,42, the oppisite phase data of test result is sent to the input of trigger 30,31,32 and input terminal DI0, DI1, the DI2 of RAM91.

Then, when the oppisite phase data of test result is write RAM91, if provide clock 1 time to trigger 30,31,32, the oppisite phase data of trigger 30,31,32 these test results of storage then, the oppisite phase data of test result is sent to the input of gate circuit 113.

At this moment, if the data of test result " 000 ", then the output data of trigger 30,31,32 is " 111 ", and the supervisory signal MONI of gate circuit 113 output becomes " 1 ", and the data of test result are if not " 000 ", and then supervisory signal MONI becomes " 0 ".Thereby, if check supervisory signal MONI, even then can not judge also from SO terminal displacement output whether the data of the test result of lead-out terminal DO0, DO1 from RAM91, DO2 are " 000 ".

Then, if set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, then the oppisite phase data of the test result of trigger 30,31,32 storages is sent to selector switch 60,61,62 respectively.The oppisite phase data of the test result of the output of selector switch 60,61,62 is anti-phase again by phase inverter 40,41,42, becomes the data of test result, is sent to the input of trigger 30,31,32 via selector switch 10,11,12.Then, if provide clock 1 time to trigger 30,31,32, the data of trigger 30,31,32 store test results then, and be sent to the input of gate circuit 113.

The data of test result " if 111 ", then the input of gate circuit 113 becomes " 111 ", and the supervisory signal MONI of gate circuit 111 output becomes " 1 ", and the data of test result are if not " 111 ", and then supervisory signal MONI becomes " 0 ".Like this, by checking supervisory signal MONI, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even do not export also decidable from the displacement of SO terminal.In addition, the test of reading and write of RAM91 repeatedly repeats in the change address.

As mentioned above, according to this embodiment 11, can obtain the effect identical with embodiment 9.

Embodiment 12

Figure 12 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 12.Among Fig. 4 of embodiment 4, the input of trigger 30,31,32 is connected with the output of selector switch 10,11,12, and among this embodiment 12, as shown in figure 12, the input of trigger 30,31,32 is connected with the output of selector switch 60,61,62, the output of trigger 30,31,32 is connected with logic section 81, from the outputing between the SO terminal of selector switch 12, appends trigger 33.Thereby, when moving usually, do not increase the output register that circuit scale just can be used as trigger 30,31,32 functional block 90 when moving usually.

Then explanation action.

When moving usually, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.The data of logic section 80 outputs are selected by selector switch 10,11,12, and directly input terminal DI0, DI1, the DI2 to functional block 90 imports.

Select by selector switch 60,61,62 from lead-out terminal DO0, the DO1 of functional block 90, the data of DO2, be sent to the input of trigger 30,31,32, because the output of trigger 30,31,32 is connected with logic section 81, thereby, when moving usually, functional block 90 and trigger 30,31,32 become the state that inserts 80,81 of logic section, by providing clock to trigger 30,31,32, computing that puts rules into practice and data processing.At this moment, trigger 30,31,32 is as the output register action of functional block 90.

During the sweep test of actuating logic portion 80,81, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.Functional block 90 is by bypass in this state, and scanning pattern becomes the state that inserts 81 of logic section 80 and logic section.Under this state, control shift mode signal SM, the sweep test of actuating logic portion 80,81.

During the sweep test of actuating logic portion 81, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, if provide 3 clocks (also can provide to trigger 33) to trigger 30,31,32, then the test data from 3 bits of SI terminal stores trigger 30,31,32 into by the serial-shift action.

The test data input logic portion 81 of 3 bits of these trigger 30,31,32 outputs, the action of logic section 81 carry out desired.The output of logic section 81 is connected with not shown other scanning patterns and the output buffer of LSI, with traditional method test.

The situation of the sweep test of actuating logic portion 80 is described.The input of logic section 80 is connected with the input buffer of LSI with the trigger output of not shown other scanning buses, provides test data with traditional method.According to this test data, the action of logic section 80 carry out desired, the output of the test result of logic section 80 are sent to " 0 " input end of selector switch 10,11,12.Set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, if provide 1 clock (also can provide to trigger 30) to trigger 31,32,33, then the data from 3 bits of the test result of logic section 80 store trigger 31,32,33 respectively into.At this moment, the data of 1 bit of trigger 33 storages are exported to the SO terminal.

Then, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, if provide 2 clocks (also can provide) to trigger 30 to trigger 31,32,33, then the data of each 1 bit of trigger 31,32 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.This occasion can store trigger 30,31 into from the SI terminal to the next test data of logic section 81.In addition, the sweep test of this logic section 80 and logic section 81 repeatedly repeats in the test data of change input.

When carrying out the test of functional block 90, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.If provide 3 clocks (also can offer trigger 33),, will store trigger 30,31,32 into from the test data of 3 bits of SI terminal then by the serial-shift action to trigger 30,31,32.

The test data of 3 bits of these trigger 30,31,32 storages is selected by selector switch 10,11,12, is input to input terminal DI0, DI1, the D12 of functional block 90.The action of functional block 90 carry out desired (if necessity then provides clock) is exported the data of test result to lead-out terminal DO0, DO1, the DO2 of functional block 90.

Then, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end, if provide clock 1 time to trigger 30,31,32, then from the data storage of the test result of lead-out terminal DO0, the DO1 of functional block 90, DO2 to trigger 30,31,32.

Then, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, if provide 3 clocks (also can offer trigger 30) to trigger 31,32,33, then the data of each 1 bit of trigger 30,31,32 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.In addition, the test of this functional block 90 repeatedly repeats in the test data of SI terminal input in change.

As mentioned above, according to this embodiment 12, test function block 90 separately under the situation of the scale that does not increase test circuit, simultaneously, when moving usually, under the situation that does not increase circuit scale, the effect of the output register of the functional block 90 when having trigger 30,31,32 as action usually.

Embodiment 13

Figure 13 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 13.Among Fig. 8 of embodiment 8, the input of trigger 30,31,32 is connected with the output of selector switch 10,11,12, and among this embodiment 13, as shown in figure 13, the input of trigger 30,31,32 is connected with the output of selector switch 60,61,62, the output of trigger 30,31,32 is connected with logic section 81, appends trigger 33 between the SO terminal from outputing to of selector switch 12.Thereby, when moving usually, do not increase circuit scale, the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.Among Figure 13, use the AND door as gate circuit 110, but also can use one of NAND door, OR door, NOR door.

Then explanation action.

When moving usually, set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.The data of logic section 80 outputs are selected by selector switch 10,11,12, and directly input terminal DI0, DI1, the D12 to RAM91 imports.

Select by selector switch 60,61,62 from lead-out terminal DO0, the DO1 of RAM91, the data of DO2, be sent to the input of trigger 30,31,32, the output of trigger 30,31,32 is connected with logic section 81, thereby, when moving usually, RAM91 and trigger 30,31,32 become the state that inserts 80,81 of logic section, by providing clock to trigger 30,31,32, computing that puts rules into practice and data processing.At this moment, trigger 30,31,32 is as the output register action of RAM91.

In addition, when the sweep test of logic section 80,81, set loop enable signal LOOPEN=0, selector switch 100 is switched to " 0 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.In this state, RAM91 is by bypass, and scanning pattern becomes the state that inserts 81 of logic section 80 and logic section.Under this state, control shift mode signal SM, the sweep test of actuating logic portion 80,81.

During the sweep test of actuating logic portion 81, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, if provide 3 clocks (also can offer trigger 33) to trigger 30 31,32, then the test data from 3 bits of SI terminal stores trigger 30,31,32 into by the serial-shift action.At this moment, consider the phase inverter 40,41,42 that inserts the serial-shift path, be necessary the test data that provides suitable.

The test data of 3 bits of these trigger 30,31,32 outputs is to logic section 81 inputs, the action of logic section 81 carry out desired.The output of logic section 81 is connected with not shown other scanning patterns and the output buffer of LSI, with traditional method test.

The situation of the sweep test of actuating logic portion 80 is described.The input of logic section 80 is connected with the input buffer of LSI with the trigger output of other not shown scanning patterns, provides the test test data with traditional method.According to this test data, the action of logic section 80 carry out desired, the output of the test result of logic section 80 are sent to " 0 " input end of selector switch 10,11,12.Set shift mode signal SM=0, selector switch 10,11,12 is switched to " 0 " input end, if provide 1 clock (also can offer trigger 30) to trigger 31,32,33, then the data from 3 bits of the test result of logic section 80 store trigger 31,32,33 respectively into.At this moment, the data of 1 bit of trigger 33 storages are exported from the SO terminal.

Then, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, if provide 2 clocks (also can offer trigger 30) to trigger 31,32,33, then the data of each 1 bit of trigger 31,32 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.This occasion also can store trigger 30,31 into from the SI terminal to the next test data of logic section 81.In addition, at this moment, need consider to give suitable test data to the phase inverter 40,41,42 that the serial-shift path inserts.In addition, the sweep test of this logic section 80 and logic section 81 repeatedly repeats in the test data of change input.

The situation of the test of RAM91 is described.At first, the situation that writes test of RAM91 being carried out primary data is described.Set loop enable signal LOOPEN=0, selector switch 100 is switched to " 0 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end.

If provide clock 3 times,, store trigger 30,31,32 into from the test data of 3 bits of SI terminal then by the serial-shift action to trigger 30,31,32.But, because the anti-phase test data storage of storage in the trigger 31, thereby during from SI terminal displacement input " 101 ", the output of trigger 30,31,32 becomes " 111 ".The output of trigger 30,31,32 is anti-phase by phase inverter 40,41,42, is selected by selector switch 10,11,12, and data " 000 " are sent to input terminal DI0, DI1, the DI2 of RAM91.

Then, set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, at every turn when trigger 30,31,32 provides clock, change input terminal DI0, the DI1 of RAM91, the data of DI2 by phase inverter 40,41,42, make it repeatedly at the state of the state of " 000 " and " 111 ".When the test data " 000 " of setting expectation or " 111 ", execution writes to RAM91.Being written in when changing the address of the RAM91 of this test data repeatedly repeats.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are sent to the input of gate circuit 110 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91 via selector switch 60,61,62.At this moment, if the data of test result " 111 ", then the supervisory signal MONI of gate circuit 110 outputs becomes " 1 ", if the data of test result are not " 111 ", then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

Then, if provide clock 1 time to trigger 30,31,32, then trigger 30,31,32 is stored the data of these test results.Then, if set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, then the data of trigger 30,31,32 storages are anti-phase by phase inverter 42,40,41, select by selector switch 12,10,11, be sent to input terminal DI2, DI0, the DI1 of RAM91, simultaneously, be sent to " 1 " input end of selector switch 60,61,62.This occasion, the data of trigger 32 storages are via " 1 " input end of selector switch 100.

At this moment, if the data of the test result of RAM91 " 000 ", then the supervisory signal MONI of gate circuit 110 outputs becomes " 1 ", if the data of the test result of RAM91 are not " 000 ", then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 000 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

Then, the oppisite phase data (being " 000 " or " 111 " during non-fault) with this test result writes RAM91.In addition, the test of reading and write of this RAM91 repeatedly repeats in the change address.

As mentioned above, according to this embodiment 13, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), can obtain efficiently to carry out the effect of the test of RAM91.

In addition, according to this embodiment 13, set loop enable signal LOOPEN=0, import the test data that makes trigger 30,31,32 become " 111 " or " 000 " from the displacement of SI terminal, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, input terminal DI0～DI2 of RAM91 at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

And, according to this embodiment 13, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

And, according to this embodiment 13, when moving usually, do not increase under the situation of circuit scale, have the effect of the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Embodiment 14

Figure 14 is that the formation of the conductor integrated circuit device of the embodiment of the invention 14 is shown circuit diagram.Among this embodiment 14, as shown in figure 14, the gate circuit among Figure 13 of embodiment 13 110 is moved to the outgoing side of phase inverter 40,41,42 as the outgoing side of gate circuit 114 from selector switch 60,61,62.This gate circuit 114 is same values in order to the data of the output of detection phase inverter 40,41,42, also can consider the test of this situation execution RAM91.Among Figure 14, use the AND door as gate circuit 114, but also can use one of NAND door, OR door, NOR door.In addition, identical among Figure 14 with Figure 13, the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 13.Action when with the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 13.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are sent to the input of trigger 30,31,32 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91 via selector switch 60,61,62.If provide clock 1 time to trigger 30,31,32, then trigger 30,31,32 is stored the data of these test results.The data of the test result of trigger 30,31,32 storages are anti-phase by phase inverter 40,41,42, are sent to the input of gate circuit 114.

At this moment, if the data of test result " 000 ", then the supervisory signal MONI of gate circuit 114 output becomes " 1 ", and the data of test result are if not " 000 ", and supervisory signal MONI becomes " 0 ".Thereby,, whether be " 000 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

Then, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, write the oppisite phase data of test result to RAM91, simultaneously, if provide clock 1 time to trigger 30,31,32, then the data of trigger 30,31,32 storages are anti-phase by phase inverter 42,40,41, select by selector switch 12,10,11,, be loaded into trigger 30,31,32 and output via " 1 " input end of selector switch 60,61,62.This occasion, the data of trigger 32 storages are via " 1 " input end of selector switch 100.

Because the output data of trigger 30,31,32 is anti-phase by phase inverter 40,41,42, be sent to the input of gate circuit 114, thereby, trigger 30,31,32 is output as the occasion of " 000 " (data of test result are " 111 "), the supervisory signal MONI of gate circuit 114 outputs becomes " 1 ", the data of the test result of RAM91 are if not " 111 ", and then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.In addition, the test of reading and write of this RAM91 repeatedly repeats in address change.

As mentioned above, according to this embodiment 14, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), can obtain efficiently to carry out the effect of the test of RAM91.

In addition, according to this embodiment 14, set loop enable signal LOOPEN=0, import the test data that makes trigger 30,31,32 become " 111 " or " 000 " from the displacement of SI terminal, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, input terminal DI0～DI2 of RAM91 at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

And, according to this embodiment 14, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

And, according to this embodiment 14, when moving usually, do not increase under the situation of circuit scale, have the effect of the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Embodiment 15

Figure 15 is that the formation of the conductor integrated circuit device of the embodiment of the invention 15 is shown circuit diagram.Among this embodiment 15, as shown in figure 15, the gate circuit among Figure 13 of embodiment 13 110 is moved to the outgoing side of selector switch 10,11,12 as the outgoing side of gate circuit 115 from selector switch 60,61,62.This gate circuit 115 is same values in order to the data of the output of detection selector switch 10,11,12, also can consider the test of this situation execution RAM91.Among Figure 15, use the AND door as gate circuit 115, but also can use one of NAND door, OR door, NOR door.In addition, identical among Figure 15 with Figure 13, the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 13.Action when with the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 13.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are sent to the input of trigger 30,31,32 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91 via selector switch 60,61,62.If provide clock 1 time to trigger 30,31,32, then trigger 30,31,32 is stored the data of these test results.The data of the test result of trigger 30,31,32 storages are anti-phase by phase inverter 40,41,42, are sent to the input of gate circuit 115 via selector switch 10,11,12.

At this moment, if the data of test result " 000 ", then the supervisory signal MONI of gate circuit 115 output becomes " 1 ", and the data of test result are if not " 000 ", and supervisory signal MONI becomes " 0 ".Thereby,, whether be " 000 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

Then, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, write the oppisite phase data of test result to RAM91, simultaneously, if provide clock 1 time to trigger 30,31,32, then the data of trigger 30,31,32 storages are anti-phase by phase inverter 42,40,41, select by selector switch 12,10,11,, be loaded into trigger 30,31,32 and output via " 1 " input end of selector switch 60,61,62.This occasion, the data of trigger 32 storages are via " 1 " input end of selector switch 100.

Because the output data of trigger 30,31,32 is anti-phase by phase inverter 40,41,42, be sent to the input of gate circuit 115 via selector switch 10,11,12, thereby, trigger 30,31,32 is output as the occasion of " 000 " (data of test result are " 11 "), the supervisory signal MONI of gate circuit 115 outputs becomes " 1 ", the data of the test result of RAM91 are if not " 111 ", and then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.In addition, the test of reading and write of this RAM91 repeatedly repeats in address change.

As mentioned above, according to this embodiment 15, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), can obtain efficiently to carry out the effect of the test of RAM91.

In addition, according to this embodiment 15, set loop enable signal LOOPEN=0, import the test data that makes trigger 30,31,32 become " 111 " or " 000 " from the displacement of SI terminal, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, input terminal DI0～DI2 of RAM91 at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

And, according to this embodiment 15, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

And, according to this embodiment 15, when moving usually, do not increase under the situation of circuit scale, have the effect of the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Embodiment 16

Figure 16 is that the formation of the conductor integrated circuit device of the embodiment of the invention 16 is shown circuit diagram.Among this embodiment 16, as shown in figure 16, the gate circuit among Figure 13 of embodiment 13 110 is moved as the outgoing side of gate circuit 116 from the output lateral trigger 30,31,32 of selector switch 60,61,62.This gate circuit 116 is same values in order to the data of the output of detection triggers 30,31,32, also can consider the test of this situation execution RAM91.Among Figure 16, use the AND door as gate circuit 116, but also can use one of NAND door, OR door, NOR door.In addition, identical among Figure 16 with Figure 13, the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Then explanation action.

Usually during action and the action the during sweep test of logic section 80,81 identical with embodiment 13.Action when with the test of RAM91 writing of RAM91 execution primary data being tested in addition, is also identical with embodiment 13.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, selector switch 100 is switched to " 1 " input end, set shift mode signal SM=1, selector switch 10,11,12 is switched to " 1 " input end, set test mode signal TEST2=0, selector switch 60,61,62 is switched to " 0 " input end.

If test is read in the specific address execution to RAM91, then the data of test result are sent to the input of trigger 30,31,32 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91 via selector switch 60,61,62.If provide clock 1 time to trigger 30,31,32, then trigger 30,31,32 is stored the data of these test results.The data of the test result of trigger 30,31,32 storages are sent to the input of gate circuit 116.

At this moment, if the data of test result " 111 ", then the supervisory signal MONI of gate circuit 116 output becomes " 1 ", and the data of test result are if not " 111 ", and supervisory signal MONI becomes " 0 ".Thereby,, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

Then, set test mode signal TEST2=1, selector switch 60,61,62 is switched to " 1 " input end, write the oppisite phase data of test result to RAM91, simultaneously, if provide clock 1 time to trigger 30,31,32, then the data of trigger 30,31,32 storages are anti-phase by phase inverter 42,40,41, select by selector switch 12,10,11,, be loaded into trigger 30,31,32 and output via " 1 " input end of selector switch 60,61,62.This occasion, the data of trigger 32 storages are via " 1 " input end of selector switch 100.

Because the output data of trigger 30,31,32 is sent to the input of gate circuit 116, thereby, trigger 30,31,32 is output as the occasion of " 111 " (data of test result are " 000 "), the supervisory signal MONI of gate circuit 116 outputs becomes " 1 ", the data of the test result of RAM91 are if not " 000 ", and then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 000 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even then do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.In addition, the test of reading and write of this RAM91 repeatedly repeats in address change.

As mentioned above, according to this embodiment 16, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, can switch in the test data that 1 clock period will write RAM91 and help 0 (" 000 ") or complete 1 (" 111 "), can obtain efficiently to carry out the effect of the test of RAM91.

In addition, according to this embodiment 16, set loop enable signal LOOPEN=0, import the test data that makes trigger 30,31,32 become " 111 " or " 000 " from the displacement of SI terminal, then, if switch to loop enable signal LOOPEN=1, then at every turn when trigger 30,31,32 provides clock, input terminal DI0～DI2 of RAM91 at the state of " 111 " and " 000 " alternately repeatedly, thereby, needn't provide test data again from the SI terminal, acquisition can be carried out the effect of the test of RAM91 easily.

And, according to this embodiment 16, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

And, according to this embodiment 16, when moving usually, do not increase under the situation of circuit scale, have the effect of the output register of the RAM91 in the time of trigger 30,31,32 can being used as action usually.

Embodiment 17

Figure 17 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 17.Among this embodiment 17, as shown in figure 17, selector switch among Fig. 8 of embodiment 8 10,11,12 and selector switch 60,61,62 are altered to AND-OR composite gate type selector switch 10a, 11a, 12a and AND-OR composite gate type selector switch 60a, 61a, 62a, AND-OR composite gate type selector switch 10a, 11a, 12a are by shift mode signal SMA, SMB control, composite gate type selector switch 60a, 61a, 62a are controlled by test mode signal TEST2A, 2B.

Then explanation action.

Action when moving usually is substantially the same manner as Example 8.But, among Figure 17, set shift mode signal SMA=0, shift mode signal SMB=1, AND-OR composite gate type selector switch 10a, 11a, 12a select the output of logic 80, set test mode signal TEST2A=0, test mode signal TEST2B=1, composite gate type selector switch 60a, 61a, 62a select the output of RAM91, thereby RAM91 becomes the state that inserts 81 of logic section 80 and logic section.In addition, when moving usually, can not provide clock to trigger 30,31,32 yet.

Action when the sweep test of logic section 80,81 is also substantially the same manner as Example 8.But, among Figure 17, set loop enable signal LOOPEN=0, selector switch 100 is switched to " 0 " input end, set test mode signal TEST2A=1, test mode signal TEST2B=0, composite gate type selector switch 60a, 61a, 62a select scanning pattern, thereby, RAM91 is by bypass, and the scanning bus becomes the state that inserts 81 of logic section 80 and logic section.Under this state, control shift mode signal SMA, SMB, the sweep test of actuating logic portion 80,81.

During the sweep test of actuating logic portion 81, set shift mode signal SMA=1, shift mode signal SMB=0, if provide clock 2 times to trigger 30,31,32, then the test data from 2 bits of SI terminal stores trigger 30,31 into by the serial-shift action.

Owing to set test mode signal TEST2A=1, thereby, the test data of following 1 bit of SI terminal is selected by composite gate type selector switch 60a, to logic section 81 inputs, the test data of each 1 bit of trigger 30,31 storages is respectively by composite gate type selector switch 61a, and 62a selects, to logic section 81 inputs, according to the test data that adds up to 3 bits, the sweep test of actuating logic portion 81.

During the sweep test of actuating logic portion 80, set shift mode signal SMA=0, shift mode signal SMB=1, if provide clock 1 time to trigger 30,31,32, then the data from 3 bits of the test result of the logic section 80 of having imported test data store trigger 30,31,32 respectively into.At this moment, the data of 1 bit of trigger 32 storages are exported from the SO terminal.

Then, set shift mode signal SMA=1, shift mode signal SMB=0, as if providing clock 2 times to trigger 30,31,32, then the data of each 1 bit of trigger 30,31 storages are from SO terminal displacement output, and affirmation adds up to the content of the data of 3 bits.This occasion can store trigger 30,31 into from the SI terminal to the next test data of logic section 81.In addition, the sweep test of this logic section 80 and logic section 81 repeatedly repeats in the test data of change input.

When the test of RAM91, state by applying flexibly shift mode signal SMA=0, SMB=0 and the state of test mode signal TEST2A=0, TEST2B=0 can easily be controlled the data that write of RAM91.Specifically, by setting shift mode signal SMA=0, SMB=0, can be sent to input terminal DI0, the DI1 of RAM91, the input data setting of DI2 becomes the state of " 000 ".In addition, by setting shift mode signal SMA=1, test mode signal TEST2A=0, TEST2B=0, can be sent to input terminal DI0, the DI1 of RAM91, the input data setting of DI2 becomes the state of " 111 ".That is, among this embodiment 17, the setting that writes data of the serial-shift of scanning pattern action becomes and does not need.

Explanation in the test of RAM91 to RAM91 carry out primary data write test the time action.By setting shift mode signal SMA=0, SMB=0, be sent to input terminal DI0, the DI1 of RAM91, the primary data of DI2 is set the state of " 000 " for, carries out writing of primary data " 000 ".In addition, by setting shift mode signal SMA=1, test mode signal TEST2A=0, TEST2B=0, be sent to input terminal DI0, the DI1 of RAM91, the primary data of DI2 is set the state of " 111 " for, carries out writing of primary data " 111 ".In addition, the write activity of this primary data repeatedly repeats in the change address.

Then, the situation of the specific address execution of RAM91 being read and write test is described.Set loop enable signal LOOPEN=1, shift mode signal SMA=1, SMB=0, test mode signal TEST2A=0, test mode signal TEST2B=1.

If test is read in the specific address execution to RAM91, then the data of test result are sent to the input of gate circuit 110 respectively from lead-out terminal DO0, DO1, the DO2 output of RAM91 via composite gate type selector switch 60a, 61a, 62a.At this moment, if the data of test result " 111 ", then the supervisory signal MONI of gate circuit 110 output becomes " 1 ", and the data of test result are if not " 111 ", and then supervisory signal MONI becomes " 0 ".Thereby,, whether be " 111 " from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 even do not export also decidable from the displacement of SO terminal if check supervisory signal MONI.

In addition, anti-phase from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 by phase inverter 40,41,42, offer input terminal DI0, DI1, the DI2 of RAM91 via AND-OR composite gate type selector switch 10a, 11a, 12a.Then, the oppisite phase data of this test result is write RAM91, simultaneously, if provide clock 1 time to trigger 30,31,32, the oppisite phase data of trigger 30,31,32 these test results of storage then.Then, set test mode signal TEST2A=1, test mode signal TEST2B=0, the oppisite phase data of the test result of trigger 30,31,32 storages is sent to the input of gate circuit 110 respectively via composite gate type selector switch 60a, 61a, 62a.This occasion, the data of trigger 32 storages are via " 1 " input end of selector switch 100.

The data of test result " if 000 ", then the input of gate circuit 110 becomes " 111 ", and the supervisory signal MONI of gate circuit 110 output becomes " 1 ", and the data of test result are if not " 000 ", and then supervisory signal MONI becomes " 0 ".Thereby, by checking supervisory signal MONI, even whether the data of test result of exporting lead-out terminal DO0, DO1, the DO2 output of yet decidable RAM91 from the displacement of SO terminal are not " 000 ".In addition, the test of reading and write of this RAM91 repeatedly repeats in address change.

As mentioned above, according to this embodiment 17, can be under the situation of the scale that does not increase test circuit testing ram 91 separately, when the test of RAM91, state by applying flexibly shift mode signal SMA=0, SMB=0 and the state of test mode signal TEST2A=0, TEST2B=0, the setting that writes data of the serial-shift action of scanning pattern becomes unnecessary, can easily control the data that write of RAM91, simultaneously, when moving usually, do not provide clock can finish the effect of test to trigger 30,31,32 even can obtain yet.

And, according to this embodiment 17, by the only inspection of execution monitoring signal MONI, even whether the data that yet can carry out the test result of lead-out terminal DO0, DO1 from RAM91, DO2 from the displacement output of SO terminal are not the test of " 111 " and whether are the test of " 000 ", thereby can obtain easily to carry out the effect of the test of RAM91.

Embodiment 18

Figure 18 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 18.Among this embodiment 18, as shown in figure 18, AND-OR composite gate type selector switch 60a, 61a, 62a among Figure 17 of embodiment 17 are altered to AND-NOR composite gate type selector switch 60b, 61b, 62b, the phase inverter 40,41,42 that inserts in the scanning pattern among deletion Figure 17 appends phase inverter 40a, 41a, 42a at the path that outputs to logic section 81 from AND-NOR composite gate type selector switch 60b, 61b, 62c.

Then explanation action.

Because AND-NOR composite gate type selector switch 60b, 61b, 62b comprise the function of phase inverter, thereby, do not need to insert among Figure 17 the phase inverter 40,41,42 of scanning pattern.In addition, for the data of the test result that do not make lead-out terminal DO0, DO1 from RAM91, DO2 are sent to logic section 81 after anti-phase, the output of AND-NOR composite gate type selector switch 60b, 61b, 62b is sent to logic section 81 via phase inverter 40a, 41a, 42a.In addition, if can be sent to logic section 81 from the data of the test result of lead-out terminal DO0, the DO1 of RAM91, DO2 after anti-phase the time, deletion phase inverter 40a, 41a, 42a.Other actions are identical with embodiment 17.

As mentioned above, according to this embodiment 18, can obtain the effect identical with embodiment 17.

Embodiment 19

Figure 19 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 19.Among Fig. 8 of embodiment 8, with the RAM91 of 3 bits as object, and among this embodiment 19, with the RAM91a of 4 bits shown in Figure 19 as object.Promptly, with the input terminal of RAM91a as DI0, DI1, DI2, D13, lead-out terminal is as DO0, DO1, DO2, DO3, append selector switch 13, selector switch 63, trigger 33, phase inverter 43, making the lead-out terminal of logic section 80 and the input terminal of logic section 80 is 4 bits, with the gate circuit 110 among Fig. 8 of 3 gate circuit 110a, 110b, 110c formation embodiment 8.The input of gate circuit 110a is connected with the output of selector switch 60,62, the input of gate circuit 110b is connected with the output of selector switch 61,63, the output of input AND circuit 110a, the 110b of gate circuit 110c is connected, and the output of gate circuit 110c is equivalent to the output of the gate circuit 110 among Fig. 8.

Then explanation action.

For example, when the test of RAM91a, under the state of test mode signal TEST2=0, by the output MONIA of monitor door circuit 110a, the having or not of the output DO0 of even bit that can testing ram 91a, DO2 dependent failure.Equally, by the output MONIB of monitor door circuit 110b, but the having or not of the output DO1 of the odd number bit of testing ram 91a, DO3 dependent failure.That is, among the embodiment 19, compare, be the function of even bit or odd number bit owing to appended the abort situation of decidable RAM91a, thereby can carry out more detailed fault diagnosis RAM91a with embodiment 8.Other actions are identical with embodiment 8.

As mentioned above, according to this embodiment 19,, also can obtain RAM91a is carried out the effect of more detailed fault diagnosis except the effect of embodiment 8.

Embodiment 20

Figure 20 is the structural circuit figure of the conductor integrated circuit device of the embodiment of the invention 20.Among this embodiment 20, as shown in figure 20, append Reflector generative circuit (FAIL FLAG GENERATOR) 120 and OR circuit 130, can easily carry out the fault diagnosis of RAM91 to Fig. 8 of embodiment 8.Reflector generative circuit 120 is made of phase inverter 121, AND circuit 122, OR circuit 123, AND circuit 124, trigger 125.

In the Reflector generative circuit 120 shown in Figure 20, for comparing enable signal CMPEN, basically, if when when ram test, expecting supervisory signal MONI=1, set relatively enable signal CMPEN=1, if supervisory signal MONI sets relatively enable signal CMPEN=0 when uncertain or during expectation supervisory signal MONI=0, make the comparison of supervisory signal MONI become masked state.In order to judge having or not of fault in real time, fault monitoring signal FAILMONI is exported to the inner self-test control circuit that carries of for example LS1.That is, setting under the state that compares enable signal CMPEN=1, when having the fault opposite with expectation, supervisory signal MONI=0, fault monitoring signal FAILMONI=1 is output.

If reset signal RESETL=0 provides clock to trigger 125, then trigger 125 resets to " 0 ".In order to judge the test result of RAM, with Reflector signal FAILFLAG to the inner self-test control circuit output of carrying of for example LSI, if non-fault, fault monitoring signal FAILMONI=0 then, if fault is arranged, fault monitoring signal FAILMONI=1 then.In case the Reflector signal becomes FAILFLAG=1, keep this state with the OR circuit 123 that is provided with in the Reflector generative circuit 120.

OR circuit 130 is according to the test mode signal TEST2A or the Reflector signal FAILFLAG of outside, and output is for the test mode signal TEST2 of selector switch 60,61,62.

Then explanation action.

When the fault diagnosis of RAM91, under the state of reset signal RESETL=0, the trigger 125 in Reflector generative circuit 120 provides clock, sets Reflector signal FAILFLAG=0.Then, reset signal RESETL=1, the test of the RAM91 of Fig. 8 explanation of execution embodiment 8.

If fault exists, supervisory signal from gate circuit 110 becomes MONI=0, then the output of AND circuit 124 becomes " 1 ", if provide clock to trigger 125, when then the Reflector signal becomes FAILFLAG=1 and output, testing setup mode signal TEST2=1 switches to " 1 " input end with selector switch 60,61,62.At this moment, also provide clock, the storage failure data to trigger 30,31,32.Here, in order to cancel later ram test, with the fault analysis action of the reason of finding out Reflector signal FAILFLAG=1, for example carry out by the inner self-test control circuit that carries of LSI.

When the test of the test of RAM91, because shift mode signal SM=1, thereby, setting loop enable signal LOOPEN=1, test mode signal TEST2=1, under the state of shift mode signal SM=1, even also to trigger 30,31,32 provide clock, this fault data also remains on 3 triggers 30 of the serial-shift path of scanning pattern, 31, in the circulating register that 32 loop connects, thereby, if the correct clock number that is provided is provided, then can comprise the data of fault data from SO terminal displacement output, analysis is the fault of which data bit.

For example, illustrate according to RAM91 the the 0th, the 1st, the 2nd, the order of 3... address carries out the situation of test.If after the 1st address detected has initial fault, then Reflector signal FAILFLAG=1 transfers to the fault analysis action.The data that include the fault data that keeps in the circulating register that is connected with the loop of 3 triggers 30,31,32 are from SO terminal displacement output.

When carrying out the test that detects the 2nd fault, from the action that Reflector signal FAILFLAG is resetted.But in the 0th address, during the test of the 1st address, order is enable signal CMPEN=0 relatively, makes comparison become masked state.Order is the control of enable signal CMPEN=0 relatively, for example carries out according to the address of the initial fault of storing in the self-test control circuit.In the 0th address, during the test of the 1st address, owing to set relatively enable signal CMPEN=0, thereby irrelevant with the value of supervisory signal MONI, fault monitoring signal FAILMONI becomes " 0 " forcibly, becomes masked state.

In the test below the 2nd address, suitably control ratio compares action than enable signal CMPEN.When for example in the 3rd address, having the 2nd fault, at the test moment of the 3rd address Reflector signal FAILFLAG=1, transfer to the fault analysis action constantly at this, the data that include the fault data that keeps in the circulating register that is connected with the loop of 3 triggers 30,31,32 are from SO terminal displacement output.

When RAM91 is the RAM of band redundancy feature, can be with the switching controls data of these fault datas as redundant circuit.

As mentioned above, according to this embodiment 20, except the effect of embodiment 8, generate Reflector signal FAILFLAG by Reflector generative circuit 120, store the fault data of RAM91 into trigger 30,31,32, after end of test (EOT) or in the test, have no progeny,, can obtain to carry out the effect of the detailed diagnostics relevant with the fault that detects by from SO terminal displacement output fault data.

In addition, enforcement of the present invention needn't be applied to the input and output terminal of all functions piece 90 or RAM91, even certain applications also can obtain effect.For example, when the input end subnumber of functional block 90 is different with the output terminal subnumber, cooperate a less side right, also can implement the present invention to form.

Claims (14)

1. conductor integrated circuit device comprises:

The the 1st and the 2nd logic section;

The functional block that connects between above-mentioned the 1st logic section and above-mentioned the 2nd logic section;

Have between the input of the output of above-mentioned the 1st logic section and above-mentioned functions piece IEEE Std parallel highway and in order to the scanning pattern of the serial-shift path of serial transfer data, it comprises: a plurality of the 1st selector switchs, in order to output and the above-mentioned serial-shift path that switches above-mentioned the 1st logic section, so that be connected with the input of above-mentioned functions piece; A plurality of triggers are stored above-mentioned data;

A plurality of the 2nd selector switchs are connected on the serial-shift path of above-mentioned scanning pattern, in order to switch the output and the above-mentioned serial-shift path of above-mentioned functions piece, so that be connected with the input of above-mentioned the 2nd logic section,

It is characterized in that:

Test data offers the above-mentioned functions piece from the serial-shift path of above-mentioned scanning pattern via above-mentioned the 2nd selector switch, switch above-mentioned the 2nd selector switch after, the data of above-mentioned functions piece output are exported via above-mentioned the 2nd selector switch.

2. the described conductor integrated circuit device of claim 1 is characterized in that:

Trigger on the serial-shift path is connected to outside the IEEE Std parallel highway between the input of the output of the 1st logic section and functional block.

3. the described conductor integrated circuit device of claim 1 is characterized in that:

Functional block is the occasion of RAM, inserts a plurality of phase inverters on the serial-shift path of scanning bus, helps 0 or complete 1 in order to the data change that will offer above-mentioned RAM by 1 clock period.

4. the described conductor integrated circuit device of claim 3 is characterized in that:

Phase inverter is connected with the output of the 2nd selector switch.

5. the described conductor integrated circuit device of claim 3 is characterized in that:

Scanning pattern possesses the 3rd selector circuit that feeds back to the input of serial-shift path in order to the output with the serial-shift path.

6. the described conductor integrated circuit device of claim 5 is characterized in that:

Possessing gate circuit, is values of regulation in order to the data from functional block that detect via the output of one of the 2nd selector switch, phase inverter and the 1st selector switch.

7. the described conductor integrated circuit device of claim 5 is characterized in that:

Possessing gate circuit, is the value of regulation in order to the data from functional block of storing in the detection triggers.

8. the described conductor integrated circuit device of claim 1 is characterized in that:

The input of the trigger on the serial-shift path of scanning pattern is connected with the output of the 2nd selector switch, and the output of above-mentioned trigger is connected with the input of the 2nd logic section.

9. the described conductor integrated circuit device of claim 8 is characterized in that:

When functional block is the occasion of RAM, comprising:

The a plurality of phase inverters that insert on the serial-shift path of scanning pattern help 0 or complete 1 in order to the data change that will offer above-mentioned RAM by 1 clock period;

The 3rd selector circuit feeds back to the input of above-mentioned serial-shift path in order to the output with the serial-shift path of above-mentioned scanning bus;

Gate circuit is values of regulation in order to the data from above-mentioned RAM that detect via the output of one of the 2nd selector switch, phase inverter and the 1st selector switch.

10. the described conductor integrated circuit device of claim 8 is characterized in that:

When functional block is the occasion of RAM, comprising:

The a plurality of phase inverters that insert on the serial-shift path of scanning pattern help 0 or complete 1 in order to the data change that will offer above-mentioned RAM by 1 clock period;

The 3rd selector circuit feeds back to the input of above-mentioned serial-shift path in order to the output with the serial-shift path of above-mentioned scanning bus;

Gate circuit is the value of regulation in order to the data from above-mentioned RAM of storing in the detection triggers.

11. the described conductor integrated circuit device of claim 1 is characterized in that:

Functional block is the occasion of RAM,

Use AND-OR composite gate type selector switch as the 1st selector switch and above-mentioned the 2nd selector switch.

12. the described conductor integrated circuit device of claim 1 is characterized in that:

Functional block is the occasion of RAM,

Use AND-OR composite gate type selector switch and AND-NOR composite gate type selector switch as the 1st selector switch and above-mentioned the 2nd selector switch.

13. the described conductor integrated circuit device of claim 1 is characterized in that:

Functional block is the occasion of RAM, comprising:

The a plurality of phase inverters that insert on the serial-shift path of scanning pattern help 0 or complete 1 in order to the data change that will offer above-mentioned RAM by 1 clock period;

The 3rd selector circuit feeds back to the input of above-mentioned serial-shift path in order to the output with the serial-shift path of above-mentioned scanning bus;

Gate circuit is values of regulation in order to the data from the odd number bit of above-mentioned RAM that detect via above-mentioned scanning pattern output;

Gate circuit is values of regulation in order to the data from the even bit of above-mentioned RAM that detect via above-mentioned scanning pattern output.

14. the described conductor integrated circuit device of claim 1 is characterized in that:

Functional block is the occasion of RAM, comprising:

The a plurality of phase inverters that insert on the serial-shift path of scanning pattern help 0 or complete 1 in order to the data change that will offer above-mentioned RAM by 1 clock period;

The 3rd selector circuit feeds back to the input of above-mentioned serial-shift path in order to the output with the serial-shift path of above-mentioned scanning bus;

Gate circuit is values of regulation in order to the data from above-mentioned RAM that detect via above-mentioned scanning pattern output;

The Reflector generative circuit, when above-mentioned gate circuit detects when the data of above-mentioned RAM are not the value of regulation, output switches to above-mentioned serial-shift path with above-mentioned the 2nd selector switch simultaneously in order to the cancellation test of above-mentioned RAM next time and the Reflector signal of execution fault analysis.

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