CN100375060C - Embedded system and real-time monitoring and processing method thereof - Google Patents
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Abstract
The present invention relates to an embedded system for monitoring memory at real time and a method thereof for monitoring memories and picking up mistake of memory cross at real time, wherein the method for monitoring memories at real time comprises the following steps: a real-time memory monitor proxy mission module is started, and a series of memory monitoring is initialized; instructions from back-stage users are received; memory control points are set according to concrete conditions, and the instructions from users are transmitted to the real-time memory monitor proxy mission module. When triggering conditions are met, the present invention carries out adjustment for exception interrupt processing.
Description
Technical field
The present invention relates to the disposal route of a kind of embedded system of real-time monitoring internal memory and real-time monitoring thereof, seizure memory overwriting mistake, relate in particular to the real-time monitoring method in a kind of embedded system engineering release.
Background technology
Embedded system, nowadays promptly a kind of dedicated computer system that is embedded in the object system is being widely used and is developing, and " embeddability ", " specificity " they are three fundamentals of embedded system with " computer system ".Embedded software moves in embedded OS usually, and the hardware platform of embedded system adopts special-purpose process chip usually.Therefore, the exploitation of embedded system, debugging all need uses special-purpose hardware or Software tool support, and needs compiler to generate special debug version.And in the engineering release of the employed software of user after exploitation is finished, then can't use exploitation, the debugging acid of these hardware or software.
Embedded system needs and can work reliably for a long time, but the mistake in the software wherein is inevitable, especially need take the mistake of the internal memory operation that certain memory headroom causes in the software owing to program, for example, the visit of crossing the border of global variable, the illegal read/write memory etc. that crosses the border.These are wrong gently then to cause the flow process of program run to be made mistakes, serious even cause systemic breakdown.If when debugging, can not find all problems, in the operational process of engineering release, just might break down.And after the fault that these internal memory illegal operations are caused takes place, can not in time analyze accordingly and debug again, then be difficult to capture fault type and location thereof, improve to stability of embedded system and brought difficulty.
Nowadays, in some embedded OSs, utilize debug registers that the function of Hardware Breakpoint is provided, can be when specified memory be modified the operation (hang-up) of interrupt system, wait for customer analysis.But this function has certain limitation, and for example, the value of certain global variable can change within the specific limits under the normal condition, will make mistakes in case be rewritten into the illegal value system, and use Hardware Breakpoint can't capture this mistake.In addition, in engineering release, do not allow to interrupt any task yet, can only deal with problems, use Hardware Breakpoint to be suitable in this case by the method for catching field data, carrying out ex-post analysis then.
Summary of the invention
At the problems referred to above, the technical problem to be solved in the present invention is exactly the shortcoming can't to monitor specified memory, seizure in the existing embedded system engineering release in real time and analyze the software error of the read/write memory that illegally crosses the border in order to overcome.
The invention provides the embedded system that a kind of real-time monitoring is handled, comprising:
One embedded system with a plurality of debug registers is handled device;
One processor interrupt control module is used to control described processor, and the execution that realization is read and write and instruction to the internal memory of being monitored is characterized in that:
By described processor interrupt control module linear address and relevant control bit are set in the debug registers of described processor, make described processor can when satisfying a trigger condition, trigger the debugging aborted automatically; And
Field data is analyzed and write down to described processor interrupt control module to the information in the described debug registers when satisfied one is provided with condition.
The present invention further provides a kind of embedded system real-time monitoring disposal route, comprised step:
The present invention utilizes embedded system to handle debug registers and the corresponding machine-processed execution that realizes the read-write and instruction of monitoring internal memory thereof that device provides.Linear address (address that the memory management pattern maps out when being the paging type management) is set in the debug registers of handling it and control bit relevant in the debugging control register is set by utilizing, processor can trigger the debugging abnormality processing automatically when trigger condition satisfies, realized analysis, information record to the scene.
Adopt the method for the invention, compared with prior art, owing to taked in embedded system, to monitor in real time internal memory, the record field data, the technical measures for ex-post analysis can effectively detect, write down the failure message in the embedded software running.The present invention has simultaneously enriched the Hardware Breakpoint function that processor provides, and whether the memory value that can monitor specified memory by the customization call back function in real time changes, monitors the medium various situations of task that the operation of revising internal memory occurs in non-appointment in a normal span.
Utilize the method for instruction execution monitoring among the present invention, can the operation of designated order in the real-time monitor (RTM) in engineering release, the problem of leaking for example for the analysis of built-in Installed System Memory, can be by the customization call back function, interface malloc to operating system in program operation process monitors, the size of application memory block when record malloc interface is called, function calling relationship etc., determine to produce the erroneous procedures of memory overflow, simultaneously can obtain the complete internal memory distribution plan of embedded system, comprise the memory block size, the task of application internal memory, application time, there are the information such as particular location in the source program in the application.
After fault took place in embedded system, the recorded information of fault in-situ provided strong support to the faults analysis location.Method provided by the invention is not limited to a certain product, is the method for a general embedded system real-time monitoring, can improve embedded system greatly, and the debugging property of embedded system engineering release is especially improved the quality of program.
Description of drawings
Figure 1 shows that embedded system memory monitoring processing capacity module map of the present invention;
Figure 2 shows that Intel80 * 86 debug registers explanations;
Figure 3 shows that real-time monitoring proxy task of the present invention is provided with internal memory monitoring point treatment scheme;
Figure 4 shows that general purpose I ntel80 * 86 interrupt INT, 1 Hardware Breakpoint processing flow chart;
Figure 5 shows that with Intel80 * 86 to be the real-time monitoring Interrupt Process sub-process of the present invention of example;
Figure 6 shows that with Intel80 * 86 to be the running stack internal memory distribution of the present invention of example.
Embodiment
Below in conjunction with accompanying drawing, be that the embedded processing chip of Intel80 * 86 is an example with the cpu type, be described in further detail according to the enforcement of the order of accompanying drawing technical scheme, the disposal route of other cpu type is similar.
Fig. 1 is the internal memory monitoring processing capacity module map of embedded system 3 of the present invention, and it comprises that mainly embedded system handles device 1 and processor interrupt control module 2, and processor interrupt control module 2 also mainly comprises three modules, below explanation respectively.
Foreground debugging aborted processing module 11: after obtaining interrupt spot information (step S501), analyze the interrupt spot, and analytical information is recorded buffer area (step S502).
Background processing module 13: on debug machine, start background program (step S507), safeguard the connection (step S508) of AM/BAM; Receive the background user order and send foreground internal memory monitoring proxy task module 11 (step S509) to, and receive the on-the site analysis information that foreground internal memory monitoring proxy task module 11 is returned, then with its demonstration or preservation (step S510).Background processing module 13 can start or close at any time.
Foreground real-time monitoring proxy task module 12: internal memory monitoring initial work (step S503); Safeguard be connected (step S504) with debug machine; The user command of sending according to background processing module 13 is provided with internal memory monitoring point (step S505) then; The timing scan buffer area, the interrupt spot information that writes down in buffer area under the unimpeded situation of AM/BAM communication sends to the backstage, empties buffer area (step S506) then.Initial work comprises that initialization is used to debug the buffer area of record field data after the down trigger, the communication of initialization AM/BAM, the debugging exception handler of initialization debugging exception handler, replacement operation system default etc.
Foreground debugging aborted processing module 11 is emphasis parts of the present invention, is that the embedded processing chip of Intel80x86 is an example below with the cpu type, and emphasis is described foreground debugging aborted processing module.
Fig. 2 has introduced the debug registers DRn that cpu type is 80 * 86 processor and the implication of each zone bit.
The interruption of relevant debugging has two among the Intel 80 * 86, and interrupt vector number is 1 and 3, and wherein interrupt INT 1 is used to handle single-step debug and hardware interrupts, and interrupt INT 3 is used for process software and interrupts.Using INT1 and INT3 is the essential technique that realizes debugger, and debugger uses interrupt INT 1 and INT3 to realize that the method for debugging is summarized as follows:
The INT1 Hardware Breakpoint: utilize the debugging support of processor itself, four debug registers of DR0-DR3 are preserved the linear address of four breakpoints, the DR7 register holds be the condition of each breakpoint.When Hardware Breakpoint is set, the linear address of triggering command is set in the DR0-DR3 of debug registers position and control bit relevant in the debugging control register (DR7) is set, after any one establishment in following four conditions, it is unusual that processor can produce INT 1 debugging, and control is handed to debugger, comprising: instruction is carried out, the content of specified memory is modified, the internal memory of appointment is had operation on read/write, the I/O port.
The INT3 software breakpoint: debugger is with the break-poing instruction (Oxcc of a byte, be INT3H) replace the first byte of the instruction of wish to trigger interrupting, when program is carried out to the break-poing instruction place, it is unusual that processor will produce the INT3 software interruption, the debugging exception handler of acquiescence will be called, and section/offset address that be kept in the stack this moment is exactly the address of a byte after the break-poing instruction.
The debugging operations that Intel 80 * 86 provides 8 debug registers DR0-DR7 to be used for processor controls, these registers can be read and write by the MOV instruction.The debug registers that Intel 80 * 86 provides can be used to realize 1-4 Hardware Breakpoint, and DR4 and DR5 keep use at present in 8 debug registers.For being described below of debug registers DR0-DR3, DR6, DR7:
DR0-DR3 is the debugging breakpoint register, and each debugging breakpoint register can be preserved one 32 breakpoint linear address;
DR6 is a debug status register, the debugging mode when being used to write down interrupt INT 1 generation, and 32 implications of DR6 are as shown in Figure 2.Here that major concern is B0-B3: the B0-B3 position is corresponding with debug registers DR0-DR3 respectively, and sign has been hit which debug registers (being used with LENn, the R/Wn position of DR7) when interrupting the INT1 generation.
DR7 is the debugging control register, is used to the condition that enables breakpoint and breakpoint is set, 32 implications of DR7 as shown in Figure 2, wherein:
R/WO-R/W3: the condition of definition breakpoint;
00: interrupt during execution command;
01: interrupt when writing internal memory;
In 10:I/O when operation, interrupted (the DE zone bit of control register CR4 be set to invalid) at 1 o'clock;
11: produce during the read/write internal memory and interrupt;
LEN0-LEN3: the memory size that defines the needs monitoring relevant with breakpoint register;
The 00:1 byte;
The 01:2 byte;
10: undefined;
The 11:4 byte;
The GD:GD position is that 1 o'clock sign debug registers is protected;
L0-L3: be to represent that the debug registers DR0-DR3 of correspondence was the task level breakpoint at 1 o'clock;
G0-G3: be to represent that the debug registers DR0-DR3 of correspondence was system-level breakpoint at 1 o'clock.
Fig. 3 is that real-time monitoring proxy task module of the present invention is provided with internal memory monitoring point processing flow chart.
At first, real-time monitoring proxy task module 12 receives the order on backstages, and judges the condition that is provided with whether legal (step 101); If legal, judge whether that then the debug registers of free time can be used (step 102); If have, then close interruption and forbid task preemption (step 103); Then according to monitored memory address in the condition, trigger condition being set to DR0-DR3, DR7 debug registers make amendment (step 104); Then, information (step 105) such as the address information of recording setting internal memory control, accumulative total trigger recording number of times information and call back function; Allow task preemption again and open the operation (step 106) of interruption.
The wherein said available condition that is provided with comprises:
1, memory address: value can be any 32 bit address.If use MMU reflection virtual memory in the embedded system, the memory address in the 4G all may effectively be not limited to the physical memory size of veneer, so this parameter is not added restriction.
2, trigger condition: value is:
(1) 0: monitored instruction is carried out;
(2) 1: internal memory is rewritten in monitoring;
(3) 2: monitoring read/write internal memory;
(4) 3: monitoring I/O operation.
3, cumulative number: produce monitoring record after the accumulative total how many times satisfies trigger condition, promptly enter treatment scheme shown in Figure 4.
4, call back function: the call back function that the user provides, value can be sky.Can preset call back function by the user, in call back function, judge whether to need to produce monitoring record.When call back function returns success, produce monitoring record, otherwise be left intact.
When internal memory monitoring point is set, after the debug registers of revising processor, produce index information simultaneously, be used to identify the condition that is provided with of the internal memory monitoring point that has been provided with.Because processor is supported at most 4 internal memory monitoring points, and 4 index informations can be arranged at most, essential record usage flag and above 4 monitoring condition is set.
Fig. 4 is Intel80 * 86 general interrupts INT1 Hardware Breakpoint processing flow charts.
The treatment scheme of Fig. 4 is mainly used in after hardware interrupts INT1 triggers, and preserves the interrupt spot, hangs up current task, waits for customer analysis.Because interrupt INT 1 is used to handle single-step debug interruption and hardware interrupts, major concern of the present invention be handling of Hardware Interrupt, omitted the processing that single-step debug is interrupted.The treatment scheme of interrupt INT 1 is described below:
At first, the trap tag position TraceFlag (step 201) among the removing EFLAGS; Then, carry out the register pop down, comprise 8 16 bit registers and 6 debug registers (step 202); Then, to above-mentioned 6 debug registers DR* zero clearings (step 203); Then, judge whether single-step debug unusual (step 204) according to status register DR6; If, then change single-step debug abnormality processing (step 212) over to, if not, then save register cs, pc, esp (step 205) then hang up current task, wait for user's on-the site analysis (206); Forbid task preemption, open interruption and obtain the current details (step 207) of breakpoint, notify debug machine to do corresponding processing (step 208) then, whether decision hangs up current task (step 209) according to breakpoint information again, allow task preemption (step 210) subsequently, recovery context, function return (step 211); At last, carry out function call and return, recover stack frame and 6 debug registers (step 212).
Fig. 5 is a real-time monitoring Interrupt Process sub-process of the present invention, is the sub-process flow diagram of Fig. 4.
In embedded system, especially in engineering release, do not allow to interrupt any task executions, can only write down the method for field data, ex-post analysis by software automatically.The present invention improved the processing of general-purpose built-in type operating system interrupt INT 1, replaced processing in the empty frame of Fig. 4 with the treatment scheme of Fig. 5:
At first according to DR6 and definite memory address addr and the breakpoint trigger condition flag (step 301) that monitors of DR7; 32 place values according to memory address addr are searched in monitoring condition, seek breakpoint record (step 302) is set; Judge whether to find record (step 303) is set, if, then further judge whether to satisfy triggering times condition (step 304), if satisfy, the call back function and the recorded information (step 305) that provide of invoke user then, what judge then whether call back function return is 0K (step 306), if, then find next available interrupt spot recording areas (step 307), then judge that whether monitoring trigger condition flag triggers (step 308) when writing internal memory, if, then write down monitored memory value (4 byte) (step 309), write down current task ID then, task name, the tick value, register, information (step 310) such as debug registers; Write down the content (step 311) of current stack ESP some bytes afterwards, then analyze stack and write down function calling relationship and parameter (step 312).
Described field data mainly comprises following content:
(1) monitored memory value;
(2) ID of current task, task name (may start some temporary duties in system's operational process and finish specific function, logger task title in the time of logger task ID can navigate to correct task in the time of can guaranteeing the ex-post analysis problem);
(3) time of current system;
(4) current general-purpose register, debug registers value;
(5) memory value in the current stack;
(6) by analyzing current function calling relationship tabulation and the function parameter that storehouse obtains.
Fig. 6 is that 80 * 86 running stack internal memories distribute.
There are an agreement in structure and use to storehouse in the code that compiler produces, and one of them important notion is stack frame (stack frame).Stack frame is exactly a storage block in the running stack, it according to certain rule description current function calls information, the corresponding linear function of stack frame calls.
As seen from Figure 6, p_ebp on-the-spot EBP (Extend Base Pointer) register value when interrupt producing, ebp[n] the EBP register value of pop down when expression n layer functions calls, ret[n] return address of expression n layer functions.All ebp[n] formed a chained list, head pointer is p_ebp.If find ebp[n in the analytic process] or ret[n] be zero, show to arrive top layer father function, stop to analyze.By can obtain the return address of several layers function to the analysis of current stack.Return address information according to function can obtain corresponding function name in symbol table.By can obtain on-the-spot function calling relationship tabulation to recalling of running stack, for faults analysis provides strong foundation.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (12)
1. an embedded system of monitoring internal memory in real time comprises,
One embedded system with a plurality of debug registers is handled device;
One processor interrupt control module is used to control described processor, and the execution that realization is read and write and instruction to the internal memory of being monitored is characterized in that:
By described processor interrupt control module linear address and relevant control bit are set in the debug registers of described processor, make described processor can when satisfying a trigger condition, trigger the debugging aborted automatically; And
Field data is analyzed and write down to described processor interrupt control module to the information in the described debug registers when satisfied one is provided with condition.
2. embedded system as claimed in claim 1 is characterized in that, described processor interrupt control module also comprises:
One background processing module is used to receive the background user order and sends it to foreground;
One foreground real-time monitoring proxy task module is connected to described background processing module, is used to receive the order that sends from described background processing module, and according to described order the internal memory monitoring point is set; And
One foreground debugging aborted processing module is connected to described foreground real-time monitoring proxy task module, is used for analyzing the interrupt spot of described internal memory monitoring point and writes down field data to a buffer area when satisfying described trigger condition;
The described buffer area of described foreground real-time monitoring proxy task module timing scan, and the field data that writes down in the described buffer area sent to the backstage, empty described buffer area then.
3. embedded system as claimed in claim 2 is characterized in that:
Described foreground real-time monitoring proxy task module also is used for communication, the initialization debugging exception handler between initialization buffer area, the initialization AM/BAM and replaces the debugging exception handler of described system default.
4. embedded system as claimed in claim 2 is characterized in that, described a plurality of debug registers also comprise:
The debugging breakpoint register is used to preserve the linear address of each breakpoint of described interruption;
The debugging control register is used to preserve described trigger condition;
Debug status register is used to write down the debugging mode when interrupting producing;
Control bit relevant in the described debugging control register also is set in the described debugging breakpoint register; And
Interrupt one of them when interruption and I/O operated when described trigger condition comprised interruption when the content of interruption when instructing execution, specified memory is modified, read/write internal memory;
Described foreground real-time monitoring proxy task module is also revised control corresponding position in the described debugging control register according to the described condition that is provided with.
5. embedded system as claimed in claim 4 is characterized in that:
Described foreground debugging aborted processing module is at first preserved the upper and lower literary composition of current system operation after satisfying described trigger condition, judge according to described debug status register whether this is handled is the interruption that hardware register triggers then; If not, then carry out the single-step debug abnormality processing; If then continue to carry out the interruption that described hardware register triggers.
6. embedded system as claimed in claim 5 is characterized in that:
Described foreground debugging aborted processing module is provided with conditional information analysis according to described in the described debug registers, and carries out the field data record;
Described field data comprises: monitored memory value; The identifying information of current task, task name; The time of current system; Current general-purpose register, debug registers value; Memory value in the current stack; By analyzing current function calling relationship tabulation and the function parameter that storehouse obtains.
7. embedded system real-time monitoring disposal route, described embedded system comprises the processor with debug registers, it is characterized in that,
Comprise the steps:
Step 1 utilizes embedded system to handle the debug registers of device and the interrupt control routine module is read and write and instruction to the internal memory of being monitored execution thereof;
Step 2 is utilized linear address and relevant control bit is set in described debug registers, and it is unusual to make described processor trigger debugging automatically when satisfying a trigger condition;
Step 3, to take over the debugging of described processor when condition is set unusual and write down field data satisfying one for described interrupt control routine module.
8. method as claimed in claim 7 is characterized in that, described step 1 further comprises step:
Step 11 is carried out a series of internal memory monitoring initialization;
Step 12 waits the background user order, if receive the background user order, then according to actual conditions the internal memory monitoring point is set; And
Step 13 if do not receive the background user order, then scans buffer area, and interrupt spot information is wherein sent to the backstage.
9. method as claimed in claim 8 is characterized in that:
Described a series of internal memory monitoring initialization step also comprises communication, the initialization foreground debugging exception handler of initialization buffer area, initialization AM/BAM and the step of replacing the debugging exception handler of acquiescence.
10. method as claimed in claim 7 is characterized in that, described trigger condition comprises:
Instruction is carried out, the content of specified memory is modified, specified memory is had on read/write and the I/O port to operate one of them.
11. method as claimed in claim 7 is characterized in that, described step 3 further comprises:
Step 31 is preserved the upper and lower literary composition of current system operation;
Step 321 is determined the address and the trigger condition of monitored internal memory according to the information in the described debug registers, if satisfy described associated trigger condition, then the call back function that provides of invoke user reads field data;
Step 322 is sought usable record district record field data according to described call back function rreturn value.
12. method as claimed in claim 11 is characterized in that, described field data comprises: monitored memory value; The identifying information of current task, task name; The time of current system; Current general-purpose register, debug registers value; Memory value in the current stack; By analyzing current function calling relationship tabulation and the function parameter that storehouse obtains.
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| CN104142885B (en) * | 2013-05-09 | 2019-01-11 | 百度在线网络技术（北京）有限公司 | A kind of method and apparatus for carrying out abnormality test to tested program |
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