CN100373131C - The Phase Detection Circuit of Incremental Rotary Encoder - Google Patents

Abstract

A phase detection circuit of an incremental rotary encoder in the field of electronic technology, comprising: a shaping circuit, an exclusive OR logic circuit, an RCD debounce protection circuit and a JK master-slave trigger circuit. The shaping circuit shapes the two-way pulse waveforms generated by the incremental rotary encoder; the RCD debounce protection circuit performs filtering and delay processing on the shaped two-way pulses; the exclusive-or logic circuit performs exclusive-or on the pulses processed by the above circuits , remove the overlapping part of the two pulses, so that the two pulses become a single pulse; the JK master-slave trigger circuit recognizes the pulses processed by the above circuit to judge the rotation direction of the incremental rotary encoder, which is clockwise or counterclockwise direction rotation. The invention can separate the output pulses of the dual-channel rotary encoder with a phase difference of 90°, which is convenient for direction judgment and counting, greatly simplifies the program of a single-chip microcomputer or other main control microprocessors, improves the reliability of counting, and is fast. At the same time, it has good portability.

Description

The Phase Detection Circuit of Incremental Rotary Encoder

technical field

The invention relates to a circuit in the field of electronic technology, in particular to a phase detection circuit of an incremental rotary encoder.

Background technique

At present, with the continuous emergence of electronic products and emerging digital products, their appearance is beautiful, while the traditional adjustment knob—potentiometer is an analog component with a narrow adjustment range and poor consistency, which can no longer meet the needs. In modern digital products, the man-machine interface design is mostly implemented with a single knob and a button, that is, the parameter to be modified is selected by switching the button, and the incremental rotary encoder is adjusted to modify the parameter. For different parameters, there are different ranges, so using a single knob to adjust requires the knob to be "non-memory", so incremental rotary encoders are widely used. The output of the incremental rotary encoder is a pulse signal, that is, the digital signal can be easily recognized by the computer, with small error and high precision, and can adapt to different adjustment ranges. However, most of the recognition of incremental rotary encoder signals now uses "software" to achieve the purpose of "phase identification", which will increase the burden on single-chip microcomputers or other main control microprocessors, and software phase identification requires continuous exploration. To determine the conditions for logical judgment, otherwise it will cause miscounting, resulting in errors.

After searching the existing technical documents, it was found that the article "Realization of a High-precision Rotary Encoder Single-chip Microcomputer Counting Circuit" published in "Computer Automatic Measurement and Control" 2000, Vol8, No.3, P51-52, this article introduces A single-chip microcomputer counting circuit for an incremental rotary encoder is proposed, which includes a direction recognition circuit and a bidirectional counting circuit. But this counting circuit is more complicated, uses a large amount of chips, adopts the mode of parallel bus to connect single-chip microcomputer, has taken up a large amount of ports, wasted the resource of single-chip microcomputer.

Contents of the invention

The purpose of the present invention is to provide a kind of phase detection circuit of incremental rotary encoder for the deficiencies and defects in the prior art, so that it can be easily connected with single-chip microcomputer or other microprocessor chips such as DSP, effectively Identify the direction of rotation, complete counting, and the hardware circuit is greatly simplified.

The present invention is realized through the following technical solutions, and the present invention includes: a shaping circuit, an exclusive OR logic circuit, an RCD debounce protection circuit and a J-K master-slave flip-flop circuit. Among them, the shaping circuit shapes the two-way pulse waveforms generated by the incremental rotary encoder to make the irregular waveforms regular, which is convenient for the identification of subsequent circuits; the RCD debounce protection circuit performs filtering and delay processing on the shaped two-way pulses so that The pulse is more suitable for the requirements of the follow-up circuit; the XOR logic circuit performs XOR on the pulse processed by the RCD debounce protection circuit, and removes the overlapping part of the two pulses, so that the two pulses become a single pulse; the J-K master-slave flip-flop circuit passes through The pulses processed by the above circuit are identified to determine the rotation direction of the incremental rotary encoder, that is, clockwise or counterclockwise, and make the waveform output by the incremental rotary encoder easier to identify by other digital chips.

The shaping circuit is composed of four 2-input OR gates 74LS32 and resistors R4 and R5. The A-phase signal output by the incremental rotary encoder is connected to 9 and 10 pins of 74LS32, and the B-phase signal is connected to 12 and 13 pins of 74LS32 for buffering, shaping, and output by 8 and 11 pins of 74LS32. Resistors R4 and R5 are current limiting resistors. One end of the resistor R4 is connected to A, and the other end is grounded. One end of the resistor R5 is connected to B, and the other end is grounded.

The RCD debounce protection circuit is composed of resistors R1, R2, R3, capacitors C1, C2, C3, and diodes D1, D2, D3. One end of the resistors R1, R2, R3 is respectively connected to the anodes of the diodes D1, D2, D3, and the other end is connected to the positive ends of the capacitors C1, C2, C3. The negative ends of the capacitors C1, C2, and C3 are grounded. The capacitor is charged through the resistor, and when the pulse high level disappears, the capacitor is discharged through the resistor and the diode, so as to achieve the function of debounce.

In order to accurately determine the direction of the incremental rotary encoder, to avoid the phenomenon that the phase of the two pulses output by the incremental rotary encoder is not strictly advanced or lagging caused by the inconsistency of components, so the design Anti-jitter protection circuit, the characteristic of this circuit is that the filter constant of the three must be greater than the pulse period of the incremental rotary encoder.

The exclusive OR logic circuit is composed of four 2-input OR gates 74LS32 and four 2-input NAND gates 74LS132. 74LS32 realizes OR logic, 74LS132 realizes NOR logic, and pin 1 and pin 2 of 74LS32 are connected with pin 1 and pin 2 of 74LS132 respectively. Pin 3 of 74LS32 is connected to pin 5 of 74LS132; pin 3 of 74LS132 is connected to pin 4 of 74LS132, and is output by pin 6 of 74LS132, thus realizing the logical XOR function.

When the incremental rotary encoder is toggled, it outputs two pulses A and B. If it is toggled clockwise, the phase of A is 1/4 period ahead of B, otherwise the phase of A is behind 1/4 period of B. Utilizing this characteristic of the incremental rotary encoder, it can be judged by detecting the sequence relationship of the two pulse phases, but this processing requires high real-time detection. If the pulses with advanced phases can be retained and the pulses with lags can be removed, then only a single pulse can be detected to determine the toggle direction of the incremental rotary encoder, which saves the time of the system. Based on this requirement, the present invention designs an XOR logic circuit.

The J-K master-slave flip-flop circuit is realized by using a 74LS78 chip. In order to detect the dialing direction of the incremental rotary encoder and count the pulses generated by the incremental rotary encoder, a J-K master-slave flip-flop 74LS78 circuit is designed.

The invention has the advantage that the hardware circuit is greatly simplified, and only two signal lines are needed to connect with other digital circuits, so as to realize the judgment of the rotation direction of the rotary incremental rotary encoder. Therefore, the program of the single-chip microcomputer or other main control microprocessor can be greatly simplified, the reliability of counting can be improved, and the speed is fast. At the same time, the present invention has good portability, as long as Q1 and Q2 [13 pins and 8 pins of 74LS78] output by the present invention are connected with other digital circuits.

Description of drawings

Fig. 1 is the schematic circuit diagram of the present invention.

Detailed ways

As shown in FIG. 1 , the present invention includes: a shaping circuit 1 , an exclusive OR logic circuit 2 , an RCD debounce protection circuit 3 and a J-K master-slave flip-flop circuit 4 . Among them, the shaping circuit 1 shapes the two-way pulse waveforms generated by the incremental rotary encoder to make the irregular waveforms regular, which is convenient for the identification of subsequent circuits; the RCD debounce protection circuit 3 performs filtering and delay processing on the shaped two-way pulses So that the pulse is more suitable for the requirements of the subsequent circuit; the XOR logic circuit 2 performs XOR on the pulse processed by the RCD debounce protection circuit 3, and removes the overlapping part of the two pulses, so that the two pulses become a single pulse; J-K master-slave trigger The device circuit 4 recognizes the pulses processed by the above circuit to determine the rotation direction of the incremental rotary encoder, that is, clockwise or counterclockwise, and makes the waveform output by the incremental rotary encoder more convenient for other digital chips. identify.

The shaping circuit is composed of four 2-input OR gates 74LS32 and resistors R4 and R5. The A-phase signal output by the incremental rotary encoder is connected to 9 and 10 pins of 74LS32, and the B-phase signal is connected to 12 and 13 pins of 74LS32 for buffering, shaping, and output by 8 and 11 pins of 74LS32. Resistors R4 and R5 are current limiting resistors. One end of the resistor R4 is connected to A, and the other end is grounded. One end of the resistor R5 is connected to B, and the other end is grounded.

The RCD debounce protection circuit is composed of resistors R1, R2, R3, capacitors C1, C2, C3, and diodes D1, D2, D3. One end of the resistors R1, R2, R3 is respectively connected to the anodes of the diodes D1, D2, D3, and the other end is connected to the positive ends of the capacitors C1, C2, C3. The negative ends of the capacitors C1, C2, and C3 are grounded. Capacitors C1, C2, and C3 are charged through resistors R1, R2, and R3. When the pulse high level disappears, capacitors C1, C2, and C3 are discharged through resistors R1, R2, and R3 and diodes D1, D2, and D3, thereby achieving debounce effect.

The exclusive OR logic circuit is composed of four 2-input OR gates 74LS32 and four 2-input NAND gates 74LS132. 74LS32 realizes OR logic, 74LS132 realizes NOR logic, and pin 1 and pin 2 of 74LS32 are connected with pin 1 and pin 2 of 74LS132 respectively. Pin 3 of 74LS32 is connected to pin 5 of 74LS132; pin 3 of 74LS132 is connected to pin 4 of 74LS132, and is output by pin 6 of 74LS132, thus realizing the logical XOR function.

The J-K master-slave flip-flop circuit is realized by using a 74LS78 chip. In order to detect the dialing direction of the incremental rotary encoder and count the pulses generated by the incremental rotary encoder, a J-K master-slave flip-flop 74LS78 circuit is designed. 74LS78 is a dual master-slave J-K flip-flop. Pin 2 and pin 6 are the prefabricated end SD; pin 5 is the common clearing end CD; pin 1 is the common clock CLK; pin 3 and pin 7 are input J1 and J2; pin 14 and pin 7 are input K1 and K2. The 74LS78 is powered by a 5V power supply.

Four 2-input OR gate 74LS32, four 2-input NAND gate 74LS132, dual master-slave J-K flip-flop 74LS78 integrated control chip, each integrated control chip is produced by ST Company.

Claims (6)

1. the phase discriminator of an incremental rotary encoder, comprise: shaping circuit (1), XOR circuit (2), RCD disappear and tremble holding circuit (3) and J-K master-slave flip-flop circuit (4), it is characterized in that, the two-way pulse waveform that shaping circuit (1) produces incremental rotary encoder is carried out shaping makes irregular waveform rule, is convenient to the identification of subsequent conditioning circuit; RCD disappear tremble holding circuit (3) thus filtering delay-time is carried out in the two-way pulse after the shaping handles and to make pulse be more suitable for the requirement of subsequent conditioning circuit; XOR circuit (2) to RCD the pulse of trembling after holding circuit (3) is handled that disappears carry out XOR, remove two-way pulse overlap part, make the two-way pulse become single pulse; J-K master-slave flip-flop circuit (4) thus to the pulse after handling by foregoing circuit discern judge incremental rotary encoder sense of rotation promptly clockwise or rotation counterclockwise, and make the digit chip identification of being more convenient for of the waveform of incremental rotary encoder output.

2. the phase discriminator of incremental rotary encoder according to claim 1, it is characterized in that, described shaping circuit (1), form by 42 inputs or door 74LS32 and resistance R 4, R5, the A phase signals of incremental rotary encoder output is received 9,10 pin of 74LS32, B connects with signal, and 12,13 pin of 74LS32 cushion, shaping, 8,11 pin output by 74LS32, resistance R 4, R5 are current-limiting resistances, resistance R 4 one ends are connected the A phase signals, other end ground connection, resistance R 5 one ends are connected the B phase signals, other end ground connection.

3. the phase discriminator of incremental rotary encoder according to claim 1, described XOR circuit (2), form by 42 inputs or door 74LS32,42 input nand gate 74LS132,74LS32 realizes or logic, 74LS132 realizes NAND Logic, 1 pin of 74LS32,2 pin link to each other with 1 pin, 2 pin of 74LS132 respectively, and 3 pin of 74LS32 link to each other with 5 pin of 74LS132; 3 pin of 74LS132 link to each other with 4 pin of 74LS132, through the 6 pin output of 74LS132.

4. the phase discriminator of incremental rotary encoder according to claim 1; it is characterized in that; described RCD disappears and trembles holding circuit (3); by resistance R 1; R2; R3; capacitor C 1; C2; C3; diode D1; D2; D3 forms; resistance R 1; R2; R3 one end respectively with diode D1; D2; the anode of D3 links to each other; the other end and capacitor C 1; C2; the anode of C3 links to each other; capacitor C 1; C2; the negativing ending grounding of C3; capacitor C 1; C2; C3 is by resistance R 1; R2; the R3 charging; when pulse high level disappears, capacitor C 1; C2; C3 is by resistance R 1; R2; R3 and diode D1; D2; the D3 discharge.

5. the phase discriminator of incremental rotary encoder according to claim 1, it is characterized in that, described J-K master-slave flip-flop circuit (4), adopt the 74LS78 chip to realize, 74LS78 is two principal and subordinate's J-K flip flops, and 2 pin, 6 pin are prefabricated end SD, 5 pin are public removing end CD, 1 pin is common clock CLK, and 3 pin, 7 pin are input J1, J2, and 14 pin, 7 pin are input K1, K2 end.

6. the phase discriminator of incremental rotary encoder according to claim 5 is characterized in that, 74LS78 adopts the power supply of 5V power supply.

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