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CN100367240C - Method and integrated circuit capable of reading and writing data simultaneously - Google Patents

Method and integrated circuit capable of reading and writing data simultaneously Download PDF

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Publication number
CN100367240C
CN100367240C CNB200310124070XA CN200310124070A CN100367240C CN 100367240 C CN100367240 C CN 100367240C CN B200310124070X A CNB200310124070X A CN B200310124070XA CN 200310124070 A CN200310124070 A CN 200310124070A CN 100367240 C CN100367240 C CN 100367240C
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address
write
read
data
cache
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CN1507051A (en
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孙教民
徐英豪
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

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  • General Engineering & Computer Science (AREA)
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Abstract

提供一种在相同时间读和写数据的集成电路和方法。该集成电路具有分离的输入和输出端口并在时钟信号的周期内输入写地址和读地址。该电路包括分别包含多个子存储块的存储块，分别对应存储块的高速缓冲存储块、和标记存储控制单元。标记存储控制单元以响应写地址或读地址控制从存储块和高速缓冲存储块中读数据和对存储块和高速缓冲存储块中写数据。特别地，如果读地址的高位地址和写地址的高位地址彼此相同，在相同的时间执行从存储块和高速缓冲存储块中读取数据并将数据写入存储块和高速缓冲存储块中。

Figure 200310124070

An integrated circuit and method for reading and writing data at the same time is provided. The integrated circuit has separate input and output ports and inputs a write address and a read address within a cycle of a clock signal. The circuit includes storage blocks respectively including a plurality of sub-storage blocks, cache memory blocks respectively corresponding to the storage blocks, and a tag storage control unit. The flag storage control unit controls reading data from and writing data to and from the memory block and the cache memory block in response to the write address or the read address. Specifically, if the upper address of the read address and the upper address of the write address are the same as each other, reading data from the memory block and the cache memory block and writing data into the memory block and the cache memory block are performed at the same time.

Figure 200310124070

Description

Can read while write the method and the integrated circuit of data
It is the U.S. Provisional Patent Application No.60/426 on November 14th, 2002 that the application requires the applying date, and 575 is right of priority, is incorporated herein and with reference to its full content.
Technical field
The present invention relates to integrated circuit, be specifically related to use the integrated circuit of the input and output port read and write simultaneously data of separating and the method for the data of read and write simultaneously.
Background technology
Each impulsive synchronization transmission read data or write data of conventional synchronous random access memory energy and clock signal.
By each rising edge and negative edge transmission data in clock signal, double data rate (DDR) RAM brings up to data transmission rate the twice of existing transfer rate.Yet in the memory device of routine, by a pin input and output data.When by input of public input and output (I/O) port and output data, can not input or output by independent control data.Therefore, the frequency limited that inputs or outputs of data.
Because the bandwidth of memory device becomes more and more important, has the memory device that separates the I/O port so produced.That is, separate input pin and output pin with independent control data input and output.Because have that the memory device that separates the I/O port can receive read command, reads the address, write order, write address and in the one-period of clock signal write data, so can improve running frequency.
Yet for to read or write data in the one-period of clock signal, having the memory device that separates the I/O port must twice storage unit access.
That is,, be used to activate the required time of word line just to have limited clock signal frequency because twice activation is used for the word line of read and write data in clock signal period.
Fig. 1 is the sequential chart that is used to explain the operation with the memory device that separates the I/O port.
Because the relation between address and word line and input data and output data postpone changes according to the circuit structure of memory device, will not consider in Fig. 1.
With reference to figure 1, in the same one-period of clock signal clk, import write address and read the address.Address A0, A2, A4 and A6 in the input of clock signal clk rising edge are address RADD, and address A1, the A3, A5 and the A7 that import at the clock signal clk negative edge are write address WADD.
What RES represented to be used to select to read address RADD reads to select signal, and WES represents to be used to select, and write address WADD's write the selection signal.
Word line AWL0 is read address RADD A0 and is activated, and in corresponding word line AWL0 output data Q0.In addition, after corresponding write address WADD A1 activated word line AWL1, input data D1 was transfused to.
Therefore, because the activation that is used for the word line AWL0 of data read and is used for the word line AWL1 that data write has limited the length in the cycle of clock signal clk.That is, owing to be necessary that sequential access has the storage unit of different addresses in the cycle of clock signal clk, the cycle that shortens clock signal clk is difficult.
Summary of the invention
The invention provides a kind of can by in clock signal period in turn from the storage unit read data and the data write storage unit is improved the integrated circuit of the operating frequency of clock signal.
The present invention also provide a kind of by in clock signal period in turn from the storage unit read data with increase the method for the running frequency of clock signal to the storage unit write data.
According to one aspect of the invention, provide a kind of have separate input and output port and in clock signal period to its input write address with read the integrated circuit of address, this integrated circuit comprises: the storage block that comprises a plurality of sub-storage blocks respectively, the caches piece of difference corresponding stored piece, and respond write address or read the address and from storage block and caches piece sense data or data are write the marker stores control module of storage block and caches piece, if it is mutually the same wherein reading the high address of address and the high address of write address, this marker stores control module just writes storage block and caches piece from storage block and caches piece sense data or with data simultaneously.
Corresponding respectively write address is decoded with two that read the address different sub-storage blocks.
This integrated circuit further comprises write address decoding path separated from one another and reads the address decoder path, and sub-storage block connects write address decoding path and reads the address decoder path.
In the sub-storage block in storage block, has a storage unit of the corresponding caches piece of storage unit of identical high address.The size of caches piece (volume) is equal to or greater than the size of sub-storage block.
Marker stores control module storage is used for determining whether cache addresses and caches piece effectively effectively determine information, and cache addresses is the address of sub-storage block that shows the data of corresponding caches piece and its storage.
When while read and write data, flag memory cell is indicated the data manipulation based on high-order read and write address simultaneously.In one case, high-order read and write address is identical, but the two is different from cache addresses.In this situation, the marker stores control module is read the storage block sense data of address and data is write the caches piece from correspondence.
Under second kind of situation, high-order read and write address is identical, and write address or to read the address be identical with cache addresses.In this case, on the caches piece, carry out operation, and on storage block, carry out other operation corresponding to the identical address of cache addresses.Under the third situation, all be identical if read address, write address and cache addresses, then the identical time from caches piece sense data with and data are write storage block.
Under the 4th kind of situation, a high position reads the address and high-order write address is inequality, but write address or to read the address identical with cache addresses.In this case, on the caches piece, carry out the operation of corresponding identical address, and on storage block, carry out operation corresponding and other address that cache addresses is inequality with cache memory.
Input or output data at single data rate (SDR) or double data rate (DDR) (DDR).
According to a further aspect in the invention, a kind of integrated circuit with input and output port of separation is provided, integrated circuit comprises: the storage block that comprises a plurality of sub-storage blocks respectively, corresponding stored piece and corresponding cache memory control signal and it is read or write a plurality of caches pieces of data respectively, corresponding stored piece and generation are used to control the corresponding write address of sub-storage block respectively, read the address, or a plurality of decoding units of the decoded signal of decoding control signal, reception is write and is selected signal or read to select signal, receive write address or read the address and produce the cache memory control signal or decoding control signal with read or write based on write address in clock signal period with read the address marker stores control module of whether identical data each other.
Decoding unit comprises a plurality of decoding circuits corresponding to sub-storage block.Decoding circuit is connected in the write address decoding path that is separated from each other and reads the address decoder path, and sub-storage block is connected to write address decoding path and reads the address decoder path.
According to a further aspect in the invention, provide a kind of in integrated circuit the method for read and write data, this integrated circuit comprises the input and output port of separation, the a plurality of storage blocks that have a plurality of sub-storage blocks respectively, and the corresponding stored piece and in clock signal period to its input write address with read the caches piece of address, this method comprises that (a) determines in clock signal period write address and reads whether the address all is transfused to or write address or read one of address and whether be transfused to, (b) if write address and read the address and all be transfused to, whether the high address (upper address) of determining write address is identical with the high address of reading the address, (c) if the high address of write address is identical with the high address of reading the address, determine write address and whether read the address identical with cache addresses, if and (d) write address and read the address and cache addresses is all inequality, read the storage block sense data of address and data write the caches piece from correspondence.
Step (d) comprises further whether the data that (d1) determine to be stored in the caches piece are effective, (d2) invalid then read the storage block sense data of address and data are write the caches piece if be stored in data in the caches piece from correspondence, (d3) upgrade information on the data write the caches piece, (d4) if the data that are stored in the high-speed memory piece are effective, just read sense data the storage block of address and the valid data that will be stored in the high-speed memory piece write storage block, and (d5) data are write caches piece and upgrade information on the data that write the caches piece from correspondence.
Cache addresses show corresponding caches piece the address of sub-storage block.
Step (c) further comprises (c1) if write address or to read the address identical with cache addresses, on the caches piece, carry out the operation of corresponding identical address with cache memory, and on storage block, carry out the operation of corresponding and cache addresses other address inequality, if and (c2) write address with to read the address all identical with cache addresses, sense data from the caches piece then, data are write storage block, and upgrade the information on the data that write storage block.
Step (b) further comprises (b1) if the high address of write address is inequality with the high address of reading the address, determine write address and whether read the address identical with cache addresses, (b2) if write address or to read one of address identical with cache addresses, then on the caches piece, carry out the operation of corresponding identical address and on storage block, carry out operation corresponding and other address that cache addresses is inequality with cache memory, (b3) if write address or to read the address all identical with cache addresses, sense data from the caches piece, data are write storage block and upgrade information on the data write storage block, if and (b4) write address or read the address and cache addresses all inequality, on the write address of the storage block of corresponding selection and two that read the address different sub-storage blocks, carry out data write operation and data reading operation.
Step (a) further comprises (a1) if import write address or read one of address, whether the address of determining input is identical with cache addresses, (a2) if the address of input is identical with cache addresses, then on the caches piece, carry out the operation of corresponding identical Input Address with cache addresses, if and address and the cache addresses (a3) imported are inequality, on storage block, carry out the operation corresponding and Input Address that cache addresses is inequality.
In the different sub-storage block of storage block, has a storage unit of the corresponding caches piece of memory cell of identical low order address.
The size of caches piece is equal to or greater than the size of sub-storage block.
Description of drawings
By being described in detail with reference to the attached drawings exemplary embodiment, above-mentioned and further feature of the present invention and advantage will be more obvious, wherein:
Fig. 1 is the sequential chart of operation that is used to explain the memory device of the input/output end port with separation;
Fig. 2 is the block scheme according to the integrated circuit of first embodiment of the invention;
Fig. 3 is the block scheme according to the integrated circuit of second embodiment of the invention;
Fig. 4 is the process flow diagram of the method for read and write data when representing according to first embodiment of the invention;
Fig. 5 is the process flow diagram that is used for the step 440 of key drawing 4;
Fig. 6 is the process flow diagram that is used for the step 445 of key drawing 4;
Fig. 7 is the process flow diagram that is used for the step 455 of key drawing 4; With
Fig. 8 is the sequential chart that is used to explain according to the operation of integrated circuit of the present invention.
Embodiment
Accompanying drawing with reference to the preferred embodiment of the present invention shown in it will be described the present invention more fully.In the accompanying drawings, identical Reference numeral is used for reference to corresponding all similar elements.
Fig. 2 is the block scheme according to the integrated circuit 200 of first embodiment of the invention.
With reference to figure 2, integrated circuit 200 comprises: storage block MB1, MB2, MB3 and MB4, and each in them all has a plurality of sub-storage block SMB1 to SMB M; Caches piece CMB1, CMB2, CMB3 and the CMB4 of corresponding stored piece MB1, MB2, MB3 and MB4; With marker stores control module 210.The integrated circuit 200 of Fig. 2 has the input/output end port of separation, and in clock signal period with write address WADD with read address RADD and input to integrated circuit 200.
Storage block MB1, MB2, MB3 and MB4 have identical configuration, and caches piece CMB1, CMB2, CMB3 and CMB4 have identical configuration.Therefore, hereinafter, storage block MB2 and caches piece CMB2 are only described.
Write address WADD and read address RADD and form by high address and low order address respectively.The high address is used for selecting a sub-storage block of a plurality of sub-storage blocks.
If it is mutually the same then read and write the cycle that data shorten clock signal respectively simultaneously in storage block and caches piece that the present invention is primarily aimed at write address WADD and reads address RADD.
Just, if write address WADD and to read address RADD mutually the same is necessary to visit identical storage block, for example, the identical sub-storage block of MB2, for example, SMB2, reading of data and in the caches piece CMB2 of the sub-storage block SMB2 of correspondence, write data in sub-storage block SMB2.
If data are written into storage block MB2, reading of data in the caches piece CMB2 of corresponding stored piece MB2 then.Therefore, can read simultaneously and write data and shorten clock signal period.
Therefore, in storage block MB2 with identical low order address (lower address), the storage unit of the necessary corresponding caches piece CMB2 of the storage unit of sub-storage block SMB1 to SMB M.In addition, owing to can read and write data in identical sub-storage block, the size of caches piece must be equal to or greater than the size of sub-storage block.
Marker stores control module 210 reads the data that are stored among storage block MB1, MB2, MB3 and MB4 and caches piece CMB1, CMB2, CMB3 and the CMB4 or data is write storage block MB1, MB2, MB3 and MB4 and caches piece CMB1, CMB2, CMB3 and CMB4.
If write address WADD and to read address RADD mutually the same, the serve as a mark cache addresses of storage control unit 210 of reading of data and data are write among the caches piece CMB2 in the sub-storage block of storage block MB2 then, the address that is written into the sub-storage block of the storage block MB2 that the data of caches piece CMB2 should deposit in is stored.
Just, cache addresses is the high address that is used for the chooser storage block, this sub-storage block be stored in the data of caches piece CMB2 should stored place.
Visit the cache addresses that is stored in the marker stores control module 210 by the low order address that uses Input Address, accessed cache addresses is compared with the high address of Input Address.
If next write address WADD and the next one are read the mutually the same and next write address WADD of address RADD and the next one and read address RADD and write address WADD the preceding and read address RADD the preceding identical, it is necessary then carrying out data write operation in caches piece CMB2.Whether in this case, must determine to have write the data of caches piece CMB2 effective.
If it is effective to have write the data of caches piece CMB2, just in the sub-storage block of corresponding stored piece MB2, read or write data, the data of corresponding next write address WADD are written into caches piece CMB2.The effectively definite information that shows the validity of the data that deposit caches piece CMB2 in is deposited in the marker stores control module 210.
If write address WADD and read address RADD and differ from one another then decodes with two that read address RADD different sub-storage blocks to corresponding write address WADD respectively.
Therefore, integrated circuit 200 must have write address decoding path (not shown) separated from one another and read address decoder path (not shown).In addition, sub-storage block SMB1 to SMB M must connect write address decoding path respectively and read the address decoder path.
Input or output data by input pin and output pin from single data rate (SDR) or double data rate (DDR) (DDR).
Marker stores control module 210 control store piece MB2 and caches piece CMB2 also carry out the read and write operation of data.The operation of marker stores control module 210 will be described with reference to figure 3 and 4.
Fig. 3 is the block scheme that shows according to the integrated circuit 300 of second embodiment of the invention.
Integrated circuit 300 comprises storage block, caches piece, decoding unit and the marker stores control module 310 that has a plurality of sub-storage block SMB1 to SMB M respectively.
The caches piece is the corresponding stored piece respectively, writes data to respond predetermined speed buffering control signal CCLS from caches piece reading of data or to it.Decoding unit is corresponding stored piece and produce decoded signal DS respectively, and it controls sub-storage block SMB1 to SMB M to respond predetermined decoding control signal DCLS.
In order to simplify, Fig. 3 has only shown a decoding unit 320 of a storage block MB2 of a plurality of sub-storage blocks, a plurality of decoding units and a caches piece CMB2 of a plurality of caches pieces.Operation according to the integrated circuit 300 of second embodiment will be described with reference to storage block MB2, caches piece CMB2 decoding unit 320 and marker stores control module 310.
Marker stores control module 310 receives to write and selects signal WES or read to select signal RES, receive write address WADD or read address RADD, if and the write address WADD that in clock signal period, imports and to read address RADD mutually the same, then produce speed buffering control signal CCLS or decoding control signal DCLS so that write and reading of data in the identical time.Although not shown, read to select signal RES and write selection signal WES to be applied to storage block MB2 and caches piece CMB2.
Because if the address RADD that reads of the write address WADD of input and input differs from one another then that to read two different sub-storage blocks of address RADD necessary decoded for corresponding respectively input write address WADD and input, so decoding unit comprises the decoding circuit (not shown) of corresponding sub-storage block SMB1 to the SMB M of a plurality of difference.
Therefore, decoding circuit is connected in write address decoding path (not shown) separated from one another and reads address decoder path (not shown), and sub-storage block SMB1 to SMB M is connected in write address decoding path and reads the address decoder path.
Fig. 4 is the process flow diagram of the method for read and write data when showing according to the embodiment of the invention.Fig. 5 is the process flow diagram that is used for the step 440 of key drawing 4, and Fig. 6 is the process flow diagram that is used for the step 445 of key drawing 4, and Fig. 7 is the process flow diagram that is used for the step 455 of key drawing 4.
Hereinafter, will the integrated circuit of the data of read and write simultaneously and the method for the data of read and write simultaneously be described with reference to figs. 2 to Fig. 7.
In step 410, whether determine in clock signal period write address and read the address all to be transfused to.Select signal WES and read to select signal RES to carry out this and determine by writing of Fig. 3.
Here, input write address WADD when writing selection signal WES at low level, address RADD is read in input when reading to select signal RES at low level.Yet, perhaps can import write address WADD and read address RADD when writing when selecting signal WES and reading to select signal RES in a high position.
Marker stores control module 310 receives to write and selects signal WES and read to select signal RES and receive write address WADD and read address RADD.
If write address WADD and read address RADD and be received in step 420, determines whether the high address of write address WADD is identical with the high address of reading address RADD.
Write address WADD and read address RADD and have the information that is used in reference to the stator storage block in they high positions.Therefore, if import write address WADD and read address RADD, specify sub-storage block by confirming write address WADD and the high address of reading address RADD.
If whether the high address of write address WADD and to read the high address of address RADD mutually the same in step 430, is determined write address WADD and reads address RADD identical with the cache addresses of being scheduled to.
If the high address of write address WADD is identical with the high address of reading address RADD, write address WADD with read address RADD and specify identical sub-storage block.
Marker stores control module 310 storages cache addresses wherein.Cache addresses shows the address of the sub-storage block of corresponding caches piece CMB2.If write address WADD is identical with cache addresses, data must be written into caches piece CMB2.
If write address, is read the storage block reading of data of address and data is write the caches piece from correspondence in step 440 with to read the address not identical with cache addresses.5 more detailed description steps 440 with reference to the accompanying drawings.
If write address determines with to read the address not identical with cache addresses whether the data that deposit in are effective in step 510 in the caches piece.
If write address WADD is not with to read address RADD identical with cache addresses, then data must be written in the identical sub-storage block of storage block MB2 or read from the identical sub-storage block of storage block MB2.Can not in identical sub-storage block, activate write word line and readout word line in the identical time.Therefore, owing to this reason is used caches piece CMB2.
If the data that are stored in the caches piece are invalid, in step 540, read the storage block of address reading of data and data are write the caches piece from correspondence.
If data must write sub-storage block or read the prioritized data read operation from sub-storage block.Therefore, read reading of data the sub-storage block of storage block MB2 of address RADD from correspondence.Because the data that are stored among the caches piece CMB2 are invalid, data just are written into caches piece CMB2.
Marker stores control module 310 is provided to decoding unit 320 with decoding control signal PCLS.Then, in decoding unit 320 decoding circuit of reading address RADD of homographic solution decoding circuit by producing the decoded signal DS corresponding sub-storage block of decoding.Output is stored in the data in the sub-storage block.The MDOUT of Fig. 3 represents to be stored in by its output the path of the data among the storage block MB2.Q represents output pin.Output pin Q and input pin D are separated from one another.
Marker stores control module 310 produces speed buffering control signal CCLS and data is write caches piece CMB2.
Be updated owing to be stored in the data of caches piece CMB2, in step 550, upgrade the information on the data that write caches piece CMB2.Carry out the renewal of the data message of speed buffering by marker stores control module 310.
If be stored in the data of caches piece CMB2 and be effectively, in step 520, read reading of data the storage block of address, and read the data that are stored in caches piece CMB2 and data are write corresponding storage block from correspondence.
Because prioritized data read operation when data must all write and read, read the sub-storage block of storage block MB2 of address RADD reading of data with the decoding control signal DCLS of response from 310 generations of marker stores control module from correspondence from identical sub-storage block.
Owing to be stored in the data of caches piece CMB2 is effectively, just read the data that are stored in caches piece CMB2 and read, and the data that read is written in the sub-storage block of corresponding reading of data.Then, in step 530, data are written into caches piece CMB2 with response speed buffering control signal CCLS, and the information on the data that write caches piece CMB2 is updated.Carry out the high speed buffer data information of upgrading by marker stores control module 310.
Carry out the operation of data write and read in the identical time.That is,, can activate write word line and readout word line in the identical time because data are written into sub-storage block and read from caches piece CMB2.Therefore, clock signal period shortens manyly than the custom integrated circuit that activates write word line and readout word line in turn.
In step 445, identical with cache addresses one of in determining whether to have only write address and reading the address, perhaps write address is carried out the operation of data write and read then with whether read the address all identical with cache addresses.To step 445 be described in more detail with reference to figure 6.
If have only in determining write address and reading the address one identical with cache addresses, then execution in step 610.On the caches piece, carry out operation according to the address identical with cache addresses, and on storage block, carry out according to other operation of cache addresses other address inequality.
Just, if it is identical with cache addresses to read address RADD, and write address and cache addresses are inequality, then reading of data from caches piece CMB2.Marker stores control module 310 is provided to caches piece CMB2 to carry out data reading operation with speed buffering control signal CCLS.The data that read are shown in CDOUT among Fig. 3.
Marker stores control module 310 produces decoding control signal DCLS to carry out data write operation on storage block MB2.
If write address identical with cache addresses and read address RADD and cache addresses inequality, data are written into caches piece CMB2 and sense data from storage block MB2.
If write address is with to read the address all identical with cache addresses, in step 620, reading of data and data are write storage block from the caches piece, and upgrade the information on the data that write storage block.
If write address is with to read the address all identical with cache addresses, data must be written into caches piece CMB2 or read from caches piece CMB2.Yet, can not be written into sub-storage block or the same in the identical time with data from the reason of sub-storage block sense data, data can not be write caches piece CMB2 or sense data from caches piece CMB2.
Therefore, reading of data writes data the sub-storage block of corresponding write address with response decoding control signal DCLS then with response speed buffering control signal CCLS from caches piece CMB2.Owing to data should be write caches piece CMB2 but data are write sub-storage block, therefore the data that are stored among the caches piece CMB2 are invalid.Therefore, update stored in information on the data among the caches piece CMB2 by marker stores control module 310.
If the high address of write address and the high address of reading the address differ from one another in step 420, then in step 450, determine write address and whether read the address identical with cache addresses.
In step 455, determine write address or read whether to have in the address one identical with cache addresses or whether write address and determine to carry out the operation of data write and read with to read the address all identical with cache addresses according to this.With reference to figure 7, more detailed description step 455.
If write address with read the address in have only one identical with cache addresses, in step 710, on the caches piece, carry out the respective operations of the address identical, and on storage block, carry out operation corresponding and other address that cache addresses is inequality with cache addresses.
Just, if read the identical write address WADD of address RADD and cache addresses with cache addresses inequality from caches piece CMB2 reading of data with response speed buffering control signal CCLS.In addition, marker stores control module 310 produces decoding control signal DCLS to carry out data write operation on storage block MB2.
If write address WADD is with to read address RADD all identical with cache addresses, then reading of data and data are write storage block from the caches piece is upgraded the information on the data that write storage block in step 720.
Data write and read operation if write address with to read the address all identical with cache addresses, then must be carried out on caches piece CMB2.Yet, owing to can not also data can not be write caches piece CMB2 or reading of data from caches piece CMB2 in this same cause of read and write data on sub-storage block of identical time.
Therefore, then data are write the sub-storage block of corresponding write address with response decoding control signal DCLS from caches piece CMB2 reading of data with response speed buffering control signal CCLS.Owing to data should be write caches piece CMB2 but data are write sub-storage block, the data that are stored among the caches piece CMB2 are just invalid.Therefore, update stored in information on the data among the caches piece CMB2 by marker stores control module 310.
If write address or read the address all with the cache addresses result who determines as step 450 inequality, in step 460, on the write address of corresponding stored piece respectively and two that read the address different sub-storage blocks, carry out the data write and read and operate (step 460).
In this situation, write address with read address RADD and specify two different sub-storage blocks.Owing to specify two sub-storage blocks of difference, by using the decoding circuit (not shown) execution data read and write operation of corresponding sub-storage block respectively.
Owing to comprise the separation decoding circuit that is used to separate the numeral storage block and write address decoding path and read the address decoder path separated from one another, can carry out data write operation and from sub-storage block, carry out data reading operation in identical time antithetical phrase storage block if the sub-storage block of storage block differs from one another.
If in step 410, import write address or read the address, in step 465, determine whether the address of input is identical with cache addresses.
If the address of input is identical with cache addresses, in step 470, on the caches piece, carry out the operation of corresponding Input Address.In this case, input write address WADD or read one of address RADD in clock signal period.
If the address and the cache addresses of input are inequality, on storage block MB2, carry out the operation of corresponding other address.
Just, if the write address WADD of input write address WADD and input is identical with cache addresses, then on caches piece CMB2, carry out data write operation.If input read address RADD and input to read address RADD identical with cache addresses, then on caches piece CMB2, carry out data reading operation.Here, marker stores control module 310 produces speed buffering control signal CCLS to carry out the operation of data write or read on caches piece CMB2.
If the address and the cache addresses of input are inequality, in step 475, on storage block, carry out the operation corresponding and Input Address that cache addresses is inequality.
Fig. 8 is the sequential chart that is used to explain according to the operation of integrated circuit of the present invention.
With reference to figure 8, the cycle of the clock signal clk of Fig. 8 is half of cycle of the clock signal clk of Fig. 1.Just, the frequency of the clock signal clk of Fig. 8 is the twice of frequency of the clock signal clk of Fig. 1.
In the prior art, owing in the cycle of clock signal clk, activate word line that is used for data write operation and the word line that is used for data reading operation successively, just be difficult to shorten the cycle of clock signal clk.Yet, according to integrated circuit and the method in identical time read and write data of the present invention, owing in the cycle of clock signal clk, activate word line WL1 that is used for data reading operation and the word line WL2 that is used for data write operation, therefore can shorten the cycle of clock signal clk in the identical time.
The present invention can be used for input port and output port be separate and in clock signal period, can receive write address and read the two integrated circuit of address.According to the present invention, just can be with single data rate (SDR) or double data rate (DDR) (DDR) to input pin input data with from the output pin output data, input pin and output pin are separated from one another.
As mentioned above, be used for storage block being divided into a plurality of sub-storage blocks at the integrated circuit of identical time read and write data, also comprise each sub-storage block of decoding decoding circuit, write address decoding path, be connected in all sub-storage blocks read the address decoder path and under the identical time in clock signal period from storage block and caches piece reading of data or to they write datas, improve the clock signal running frequency thus.
Illustrating and describing the present invention particularly with reference to its exemplary embodiment, be to be understood that do not breaking away under the present invention and the spirit and scope that claim limited thereof that those of ordinary skills can carry out various variations in form and details.

Claims (32)

1.一种具有分离的数据输入端口和数据输出端口并在时钟信号周期内对其输入写地址和读地址的集成电路，该集成电路包括：1. An integrated circuit having separate data input ports and data output ports and inputting a write address and a read address to it within a clock signal cycle, the integrated circuit comprising: 多个各自包含多个子存储块的存储块；a plurality of memory blocks each comprising a plurality of sub-memory blocks; 分别对应存储块的多个高速缓冲存储块；和a plurality of cache memory blocks respectively corresponding to memory blocks; and 从存储块和高速缓冲存储块读取数据或将数据写入存储块和高速缓冲存储块以响应写地址和读地址的标记存储控制单元，a tag storage control unit that reads data from or writes data to the memory block and the cache memory block in response to a write address and a read address, 其中如果读地址的高位地址与写地址的高位地址彼此相同，则标记存储控制单元促使集成电路在相同时间从存储块读取数据并将数据写入高速缓冲存储块；并且如果读地址的高位地址与写地址的高位地址彼此相同，则标记存储控制单元促使集成电路在相同时间从高速缓冲存储块读取数据并将数据写入存储块。Wherein if the high-order address of the read address and the high-order address of the write address are identical to each other, the tag storage control unit causes the integrated circuit to read data from the memory block and write the data to the cache memory block at the same time; and if the high-order address of the read address If the upper addresses of the write address and the write address are identical to each other, the tag storage control unit causes the integrated circuit to read data from the cache memory block and write data to the memory block at the same time. 2.根据权利要求1所述的集成电路，其中当写地址和读地址彼此不同时分别对应写地址和读地址的两个不同的子存储块被解码。2. The integrated circuit of claim 1, wherein two different sub-memory blocks respectively corresponding to the write address and the read address are decoded when the write address and the read address are different from each other. 3.根据权利要求1所述的集成电路，进一步包括彼此分离的写地址解码路径和读地址解码路径、连接写地址解码路径和读地址解码路径的子存储块。3. The integrated circuit according to claim 1, further comprising a write address decoding path and a read address decoding path separated from each other, a sub memory block connecting the write address decoding path and the read address decoding path. 4.根据权利要求1所述的集成电路，其中，在存储块中的子存储块中，在具有相同低位地址的各个子存储块中的存储单元对应高速缓冲存储块的相同存储单元。4. The integrated circuit according to claim 1, wherein, among the sub-blocks in the memory block, the memory cells in the respective sub-blocks having the same lower address correspond to the same memory cells of the cache block. 5.根据权利要求1所述的集成电路，其中高速缓冲存储块的尺寸等于或大于每一子存储块的尺寸。5. The integrated circuit of claim 1, wherein a size of the cache block is equal to or greater than a size of each sub-block. 6.根据权利要求1所述的集成电路，其中标记存储控制单元存储用于确定存储在高速缓冲存储块中的数据是否有效的有效确定信息和显示对应高速缓冲存储块的子存储块的地址的高速缓冲存储器地址。6. The integrated circuit according to claim 1 , wherein the tag storage control unit stores validity determination information for determining whether data stored in the cache memory block is valid and a display address of a sub memory block of the corresponding cache memory block Cache address. 7.根据权利要求6所述的集成电路，其中，当选择一个子存储块的写地址的高位地址与选择一个子存储块的读地址的高位地址相同时，标记存储控制单元促使集成电路从对应读地址的子存储块中读取数据并将数据写入高速缓冲存储块，当无论写地址和读地址与高速缓冲存储器地址都不相同时在相同时间内读取或写入数据。7. The integrated circuit according to claim 6, wherein, when the upper address of the write address for selecting a sub-storage block is the same as the upper address of the read address for selecting a sub-storage block, the tag storage control unit causes the integrated circuit to start from the corresponding Read data in the sub memory block of the read address and write the data into the cache memory block, and read or write data at the same time when both the write address and the read address are different from the cache memory address. 8.根据权利要求6所述的集成电路，其中标记存储控制单元当选择一个子存储块的写地址的高位地址与读地址的高位地址相同时，当写地址和读地址之一与高速缓冲存储器地址相同时，在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的地址的操作并在存储器块上执行对应于与高速缓冲存储器地址不相同的地址的操作；并且当写地址与读地址都与高速缓冲存储器地址相同时，从高速缓冲存储块上读取数据并将数据写入存储块。并且在相同时间读取数据或写入数据。8. The integrated circuit according to claim 6, wherein when the high order address of the write address of a selected sub memory block is the same as the high order address of the read address by the tag storage control unit, when one of the write address and the read address is the same as that of the cache memory When the addresses are the same, an operation corresponding to the same address as the cache address is performed on the cache block and an operation corresponding to an address different from the cache address is performed on the memory block; and when the write address is the same as the read address When both are the same as the cache address, the data is read from the cache block and written to the memory block. And read data or write data at the same time. 9.根据权利要求6所述的集成电路，其中标记存储控制单元，当选择一个子存储块的写地址的高位地址与读地址的高位地址不相同时，当写地址和读地址中的一个与高速缓冲存储器地址相同时，在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的地址的操作并在存储器块上执行对应于与高速缓冲存储器地址不相同的其它地址的操作；并如果写地址与读地址都与高速缓冲存储器地址相同，从高速缓冲存储块上读取数据然后将数据写入存储块，如果无论写地址和读地址与高速缓冲存储器地址都不相同，从分别对应读地址和写地址的两个不同的子存储块中取并写入数据。9. The integrated circuit according to claim 6, wherein the tag storage control unit, when the high address of the write address of a selected sub memory block is different from the high address of the read address, when one of the write address and the read address is the same as When the cache addresses are the same, perform operations on the cache block corresponding to addresses identical to the cache address and perform operations on the memory block corresponding to other addresses not identical to the cache address; and if the write Both the address and the read address are the same as the cache memory address. Read data from the cache memory block and then write the data to the memory block. If both the write address and the read address are different from the cache memory address, the corresponding read addresses Fetch and write data in two different sub-storage blocks with the write address. 10.根据权利要求1所述的集成电路，其中以单数据率SDR或双数据率DDR输入并输出数据。10. The integrated circuit of claim 1, wherein data is input and output at a single data rate (SDR) or double data rate (DDR). 11.一种具有分离的数据输入和输出端口的集成电路，该集成电路包括：11. An integrated circuit having separate data input and output ports, the integrated circuit comprising: 各自包含多个子存储块的多个存储块；a plurality of memory blocks each comprising a plurality of sub-memory blocks; 分别对应存储块并对其读或写数据以响应高速缓冲控制信号的多个高速缓冲存储块；a plurality of cache memory blocks respectively corresponding to the memory blocks and to which data are read or written in response to the cache control signal; 分别对应存储块并产生用于控制子存储块以响应写地址、读地址和解码控制信号的解码信号的多个解码单元；以及a plurality of decoding units respectively corresponding to the storage blocks and generating decoding signals for controlling the sub-storage blocks in response to write addresses, read addresses and decoding control signals; and 接收写选择信号或读选择信号的标记存储控制单元接收写地址或读地址并产生解码控制信号的高速缓冲控制信号以便根据写地址读地址之比来读并写数据。A tag memory control unit receiving a write select signal or a read select signal receives a write address or a read address and generates a cache control signal that decodes the control signal to read and write data according to a ratio of the write address to the read address. 12.根据权利要求11所述的集成电路，其中解码单元各自包括分别对应子存储块的多个解码电路。12. The integrated circuit according to claim 11, wherein the decoding units each include a plurality of decoding circuits respectively corresponding to the sub memory blocks. 13.根据权利要求12所述的集成电路，其中解码电路连接于彼此分离的写地址解码路径和读地址解码路径，且子存储块分别连接于写地址解码路径和读地址解码路径。13. The integrated circuit according to claim 12, wherein the decoding circuit is connected to a write address decoding path and a read address decoding path which are separated from each other, and the sub memory blocks are respectively connected to the write address decoding path and the read address decoding path. 14.根据权利要求11所述的集成电路，其中，当写地址和读地址彼此不相同时，分别对应写地址和读地址的两个不同子存储块被解码。14. The integrated circuit of claim 11, wherein when the write address and the read address are different from each other, two different sub-memory blocks respectively corresponding to the write address and the read address are decoded. 15.根据权利要求11所述的集成电路，其中，在一个存储块中的子存储块中，在具有相同低位地址的各个子存储块中的存储单元对应一个高速缓冲存储块的相同存储单元。15. The integrated circuit according to claim 11, wherein, among the sub-blocks in one block, the memory cells in the respective sub-blocks having the same lower address correspond to the same memory cells of one cache block. 16.根据权利要求11所述的集成电路，其中，高速缓冲存储块的尺寸等于或大于每个子存储块的尺寸。16. The integrated circuit of claim 11, wherein a size of the cache block is equal to or greater than a size of each sub-block. 17.根据权利要求11所述的集成电路，其中标记存储控制单元存储用于确定存储在高速缓冲存储块中的数据是否有效和指示对应高速缓冲存储块的子存储块的地址的高速缓冲存储器地址的有效确定信息。17. The integrated circuit according to claim 11 , wherein the tag storage control unit stores a cache memory address for determining whether data stored in the cache memory block is valid and an address of a sub-memory block corresponding to the cache memory block effective confirmation information. 18.根据权利要求17所述的集成电路，其中，当选择的一个子存储块的写地址的高位地址与选择的一个子存储块的读地址的高位地址相同时，标记存储控制单元促使集成电路从对应读地址的子存储块中读取数据并将数据写入高速缓冲存储块，当无论写地址和读地址与高速缓冲存储器地址都不相同时在相同时间内读或写数据。18. The integrated circuit according to claim 17, wherein, when the upper address of the write address of the selected sub-storage block is the same as the upper address of the read address of the selected one of the sub-storage blocks, the tag storage control unit prompts the integrated circuit Reading data from a sub-memory block corresponding to a read address and writing data into a cache memory block, reading or writing data at the same time when both the write address and the read address are different from the cache memory address. 19.根据权利要求17所述的集成电路，其中的标记存储控制单元当选择一个子存储块的写地址的高位地址与读地址的高位地址相同时，当写地址和读地址之一与高速缓冲存储器地址相同时，产生高速缓冲控制信号以在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的地址的操作并产生解码控制信号以在存储器块上执行对应于与高速缓冲存储器地址不相同的地址的操作，以及当写地址与读地址都与高速缓冲存储器地址相同时，产生高速缓冲控制信号以从高速缓冲存储块中读取数据并产生解码控制信号以将数据写入存储块，并且同时读数据或写数据。19. The integrated circuit according to claim 17, wherein when the high address of the write address of a sub-storage block is selected by the mark storage control unit to be the same as the high address of the read address, when one of the write address and the read address is the same as the cache memory When the memory address is the same, a cache control signal is generated to perform an operation on the cache block corresponding to the same address as the cache memory address and a decode control signal is generated to perform an operation on the memory block corresponding to an address different from the cache memory address operation of the address, and when both the write address and the read address are identical to the cache memory address, generate a cache control signal to read data from the cache memory block and generate a decode control signal to write data into the memory block, and Read data or write data at the same time. 20.根据权利要求17所述的集成电路，其中标记存储控制单元，当选择一个子存储块的写地址的高位地址与读地址的高位地址不相同时，当写地址和读地址之一与高速缓冲存储器地址相同时，产生高速缓冲控制信号以在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的地址的操作并产生解码控制信号以在存储器块上执行对应于与高速缓冲存储器地址不相同的其它地址的操作，以及当写地址与读地址都与高速缓冲存储器地址相同时，产生高速缓冲控制信号从高速缓冲存储块上读取数据；产生解码控制信号以便将数据写入存储块，并且如果写地址和读地址与高速缓冲存储器地址都不相同，则产生解码控制信号以从分别对应读地址和写地址的两个不同的子存储块中读和写数据。20. The integrated circuit according to claim 17, wherein the tag storage control unit, when the upper address of the write address of a selected sub-storage block is different from the upper address of the read address, when one of the write address and the read address is the same as the high-speed When the cache address is the same, generate a cache control signal to perform an operation on the cache block corresponding to the same address as the cache address and generate a decode control signal to perform an operation on the memory block corresponding to an address different from the cache address The same operation of other addresses, and when both the write address and the read address are the same as the cache memory address, generate a cache control signal to read data from the cache memory block; generate a decoding control signal to write data into the memory block, And if the write address and the read address are not the same as the cache address, a decoding control signal is generated to read and write data from two different sub-memory blocks respectively corresponding to the read address and the write address. 21.根据权利要求11所述的集成电路，其中以单数据率SDR或双数据率DDR输入和输出数据。21. The integrated circuit of claim 11, wherein data is input and output at a single data rate (SDR) or double data rate (DDR). 22.一种在集成电路中读数据和写数据的方法，所述集成电路包含分离的输入和输出端口、各自具有多个子存储块的多个存储块、以及分别对应存储块并在时钟信号周期内对其输入写地址和读地址的多个高速缓冲存储块，该方法包括：22. A method of reading data and writing data in an integrated circuit comprising separate input and output ports, a plurality of memory blocks each having a plurality of sub-memory blocks, and corresponding to the memory blocks respectively and during clock signal cycles A plurality of cache memory blocks to which write addresses and read addresses are input within the method comprising: 步骤a：确定在时钟信号周期内是否写地址和读地址都被输入或写地址和读地址之一被输入；Step a: determining whether both the write address and the read address are input or one of the write address and the read address is input within the period of the clock signal; 步骤b：当写地址和读地址两个都被输入时，确定写地址的高位地址与读地址的高位地址是否相同；Step b: When both the write address and the read address are input, determine whether the high address of the write address is the same as the high address of the read address; 步骤c：当写地址的高位地址与读地址的高位地址相同时，确定写地址和读地址中是否至少一个与高速缓冲存储器地址相同；以及Step c: when the upper address of the write address is the same as the upper address of the read address, determine whether at least one of the write address and the read address is identical to the cache memory address; and 步骤d：当写地址和读地址与高速缓冲存储器地址都不同时，从对应读地址的存储块中读取数据并将数据写入高速缓冲存储块中。Step d: When the write address and the read address are different from the cache memory address, read data from the memory block corresponding to the read address and write the data into the cache memory block. 23.根据权利要求22所述的方法，其中步骤d进一步包括：23. The method of claim 22, wherein step d further comprises: 步骤d1：确定存储在高速缓冲存储块中的数据是否有效；Step d1: determining whether the data stored in the cache block is valid; 步骤d2：当存储在高速缓冲存储块中的数据无效时，从对应读地址的存储块中读取数据并将数据写入高速存储器块；Step d2: When the data stored in the cache memory block is invalid, read the data from the memory block corresponding to the read address and write the data into the high-speed memory block; 步骤d3：更新写入高速缓冲存储块的数据上的信息；Step d3: updating the information on the data written to the cache block; 步骤d4：当存储在高速缓冲存储块中的数据有效时，从对应读地址的存储块上读取数据并将高速缓冲存储块中存储的有效数据写入存储块；以及Step d4: When the data stored in the cache memory block is valid, read the data from the memory block corresponding to the read address and write the valid data stored in the cache memory block into the memory block; and 步骤d5：将数据写入高速缓冲存储块并更新写入高速缓冲存储块的数据上的信息。Step d5: Write data into the cache block and update information on the data written into the cache block. 24.根据权利要求22所述的方法，其中高速缓冲存储器地址显示对应高速缓冲存储块的子存储块的地址。24. The method of claim 22, wherein the cache address shows an address of a sub-block of the corresponding cache block. 25.根据权利要求22所述的方法，其中步骤c进一步包括：25. The method of claim 22, wherein step c further comprises: 步骤c1：当写地址和读地址之一与高速缓冲存储器地址相同时，在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的地址的操作并在存储块上执行对应于与高速缓冲存储器地址不相同的地址操作；以及Step c1: When one of the write address and the read address is the same as the cache memory address, perform an operation on the cache block corresponding to the same address as the cache memory address and perform an operation on the memory block corresponding to the cache memory address address operations where the address is not the same; and 步骤c2：当写地址和读地址都与高速缓冲存储器地址相同时，从高速缓冲存储块上读取数据、将数据写入存储块，并更新写入存储块的数据上的信息。Step c2: When both the write address and the read address are the same as the cache memory address, read data from the cache memory block, write data into the memory block, and update information on the data written into the memory block. 26.根据权利要求22所述的方法，其中步骤b进一步包括：26. The method of claim 22, wherein step b further comprises: 步骤b1：当写地址的高位地址与读地址的高位地址不相同时，确定写地址和读地址与高速缓冲存储器地址是否相同；Step b1: When the upper address of the write address is different from the upper address of the read address, determine whether the write address and the read address are the same as the cache memory address; 步骤b2：当写地址或读地址与高速缓冲存储器地址相同时，在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的地址的操作并在存储块上执行对应于与高速缓冲存储器地址不相同的其他的地址操作；Step b2: When the write address or the read address is the same as the cache memory address, perform the operation on the cache block corresponding to the same address as the cache memory address and perform the operation on the memory block corresponding to the cache memory address different from The same other address operations; 步骤b3：当写地址和读地址都与高速缓冲存储器地址相同时，从高速缓冲存储块上读取数据，并将数据写入存储块，并更新写入存储块的数据上的信息；以及Step b3: when both the write address and the read address are identical to the cache memory address, read data from the cache memory block, write the data into the memory block, and update information on the data written into the memory block; and 步骤b4：当写地址和读地址都于高速缓冲存储器地址不相同时，在对应被选存储块的写地址和读地址的两个不同子存储块上执行数据写操作和数据读操作。Step b4: When both the write address and the read address are different from the cache memory address, perform data write operation and data read operation on two different sub-memory blocks corresponding to the write address and read address of the selected memory block. 27.根据权利要求22所述的方法，其中步骤a进一步包括：27. The method of claim 22, wherein step a further comprises: 步骤a1：当只输入写数据或读数据中的一个时，确定输入地址与高速缓冲存储器地址是否相同；Step a1: When only one of write data or read data is input, determine whether the input address is the same as the cache memory address; 步骤a2：当输入地址与高速缓冲存储器地址相同时，在高速缓冲存储块上执行对应于与高速缓冲存储器地址相同的输入地址的操作；以及Step a2: when the input address is the same as the cache memory address, perform an operation on the cache memory block corresponding to the same input address as the cache memory address; and 步骤a3：当输入地址与高速缓冲存储器地址不相同时，在存储块上执行对应于与高速缓冲存储器地址不相同的输入地址的操作。Step a3: When the input address is different from the cache memory address, perform an operation on the memory block corresponding to the input address different from the cache memory address. 28.根据权利要求22所述的方法，其中，在存储块的不同子存储块中，在具有相同低位地址的各个子存储块中的存储单元对应高速缓冲存储块的相同存储单元。28. The method according to claim 22, wherein, among different sub-memory blocks of the memory block, memory cells in respective sub-memory blocks having the same lower order address correspond to the same memory cells of the cache memory block. 29.根据权利要求22所述的方法，其中高速缓冲存储块的尺寸等于或大于每个子存储块的尺寸。29. The method of claim 22, wherein a size of the cache block is equal to or greater than a size of each sub-block. 30.根据权利要求22所述的方法，其中以单数据率SDR或双数据率DDR输入和输出数据。30. The method of claim 22, wherein the data is input and output in single data rate (SDR) or double data rate (DDR). 31.一种集成电路，包括：31. An integrated circuit comprising: 分离的输入和输出数据端口；Separate input and output data ports; 包括多个子存储块的存储块；a memory block comprising a plurality of sub-memory blocks; 以存储至少与子存储块相同数据量的高速缓冲存储块；和a cache block to store at least the same amount of data as the sub-block; and 标记存储器控制单元，其标记对应于子存储器块的地址的高速缓冲存储块的有效条目，当读和写操作寻址相同的子存储器块时通过使用至少一个操作的高速缓冲存储块来同时协调读和写操作。A tag memory control unit that tags valid entries of a cache block corresponding to an address of a sub-memory block, coordinating reads simultaneously by using at least one of the operated cache blocks when read and write operations address the same sub-memory block and write operations. 32.一种在集成电路中同时执行读和写操作的方法，该方法包括：32. A method of simultaneously performing read and write operations in an integrated circuit, the method comprising: 将存储块分割成多个子存储块；Divide the storage block into a plurality of sub-storage blocks; 保持高速缓冲存储块足够大以存储至少与子存储块相同数量的数据；keep the cache block large enough to store at least the same amount of data as the sub-block; 在具有对应子存储块地址的高速缓冲存储块中标记有效条目；以及marking a valid entry in the cache block with the corresponding sub-block address; and 当读和写操作都寻址相同存储块时，通过使用一个操作的高速缓冲存储块并且在可能时通过在不同子存储块上同时执行操作来同时执行读和写操作。When both read and write operations address the same memory block, the read and write operations are performed simultaneously by using one operating cache block and, if possible, by performing the operations simultaneously on different sub-memory blocks.
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