CN100365931C - Static discharge preventer using integration circuit - Google Patents
Static discharge preventer using integration circuit Download PDFInfo
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- CN100365931C CN100365931C CNB2004100504245A CN200410050424A CN100365931C CN 100365931 C CN100365931 C CN 100365931C CN B2004100504245 A CNB2004100504245 A CN B2004100504245A CN 200410050424 A CN200410050424 A CN 200410050424A CN 100365931 C CN100365931 C CN 100365931C
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- 230000003068 static effect Effects 0.000 title claims description 39
- 230000010354 integration Effects 0.000 title description 2
- 230000000694 effects Effects 0.000 claims description 7
- 230000009467 reduction Effects 0.000 claims description 6
- 238000012545 processing Methods 0.000 abstract description 18
- 230000002159 abnormal effect Effects 0.000 abstract description 5
- 230000009471 action Effects 0.000 abstract description 5
- 230000001131 transforming effect Effects 0.000 abstract 3
- 230000000737 periodic effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Abstract
The present invention relates to an electrostatic discharge (ESD) preventer which can form a stabler system for ESD phenomena by utilizing an integrating circuit. The ESD preventer utilizing an integrating circuit of the present invention is composed of an integrating circuit, a voltage transforming part and a central processing unit CUP, wherein the integrating circuit receives various clock source input signals (clock source) generated inside a system, and detects abnormal clock signals in the state of electric shock caused by ESD; the voltage transforming part is used for reducing the level of the abnormal clock signals detected by the integrating circuit; the central processing unit CUP receives the abnormal clock signals output by the voltage transforming part, and controls the refreshing action of the clock source which comprises the abnormal clock signals. The present invention with the structure can realize the stabler system for the ESD phenomena by utilizing the integrating circuit, so that the reliability of the system is improved.
Description
Technical field
The present invention relates to the anti-locking apparatus of a kind of static discharge, particularly utilize the anti-locking apparatus of static discharge of integrating circuit.
Background technology
Current, for television system (Television System), expansion along with Digital Television (Digital TV) function, the complexity of its system increases the challenge that brings significantly for the function that solves Digital Television in other words, as the countermeasure of head it off, use way with what current common employing hardware (H/W) and software (S/W) combined.
Particularly, for the complexity of system, along with the use to integrated circuit (IC) increases, current proportion with software way solution static discharge ESD (Electro Static Discharge) countermeasure technology increases.
As the game method of static discharge ESD, current have two kinds: a kind of is with (Zener) voltage stabilizing didoe (Zener Diode), or utilizes the hardware approach of low pass filter (Low Pass Filler) and ground connection GND separation etc.; Another kind is the software approach that refreshes (Refresh) after integrated circuit (IC) register (Register) is periodically tested.Wherein, what current use was maximum is exactly, to self having the integrated circuit (IC) register of refresh function, and the software approach of testing with periodic intervals.
For by the minimized all problems that cause generation by static discharge ESD of software approach, to cause the malfunctioning situation of running software that occurs by static discharge ESD electric current, program deadlock (deadlock) (Loch Up) state can not occur, and should system be set to normal automatically the recovery this moment.
To system's external noise,, should form by the following stage: the fault (Fault) that internal system produces is carried out detection-phase with software for internal system has the very strong anti-characteristic of doing sorrow (antinoise); System is carried out recovery phase with normal stable status.
For this reason, software should be with certain rule detection internal system abnormal condition, and before system's misoperation or fault produce, detects error rapidly.
But with the software approach of periodic intervals affirmation buffer status, because the generation static discharge ESD time is very short, it is limited therefore detecting static discharge ESD with software approach.That is,, therefore can not normally carry out refresh activity, so can not prevent system's misoperation to static discharge ESD because formation static discharge ESD that can not be complete detects.
Summary of the invention
The present invention develops for the problem that solves above-mentioned existence, and its purpose is to provide a kind of anti-locking apparatus of static discharge that utilizes integrating circuit.This device utilizes integrating circuit can constitute more stable system to static discharge ESD phenomenon.
In order to achieve the above object, it is to be made of following part that the present invention utilizes the anti-locking apparatus of the static discharge of integrating circuit: the signal (ClockSource) of the inner various clocks source input that produces of receiving system, and cause the integrating circuit that the unusual clock signal under the surge state is provided with by static discharge (to call ESD in the following text) for detection; The voltage transformating part that the unusual clock signal level that detects by integrating circuit for reduction (Down) is provided with; Receive the unusual clock signal of voltage transformating part output, and the clock source that comprises unusual clock signal refreshed that (Refresh) action is controlled and the central processing unit CPU that is provided with.
Above-mentioned central processing unit CPU is to receive unusual clock signal by interruptive port (Interrupt Port).
And, in order to achieve the above object, it is to be made of following part that the present invention utilizes the anti-locking apparatus of the static discharge of integrating circuit: the signal (Clock Source) of the inner various clocks source input that produces of receiving system, and be to detect to cause the integrating circuit that the unusual clock signal under the surge state is provided with by static discharge (to call ESD in the following text); The voltage transformating part that the unusual clock signal level that detects by integrating circuit for reduction (Down) is provided with; In order to keep the combinational circuit that is provided with from the unusual clock signal of voltage transformating part output by certain hour; Receive the unusual clock signal of combinational circuit output, and the clock source (ClockSource) that comprises unusual clock signal refreshed that (Refresh) action is controlled and the central processing unit CPU that is provided with.
Above-mentioned central processing unit CPU is to receive unusual clock signal by input/output end port (Input/OutputPort).
Advantageous effect of the present invention is as follows:
Utilizing the anti-locking apparatus of static discharge of integrating circuit as above-mentioned explanation the present invention is to utilize integrating circuit, can constitute more stable system to static discharge ESD phenomenon, therefore has the effect that improves system reliability.
If the colleague, do not break away from that change of many kinds and modification are arranged in the technological thought scope of the present invention is understandable by above-mentioned explanation so.
Other purpose of the present invention, characteristic and doubtful point are appreciated that by the detailed description of reference drawings and Examples.
Description of drawings
Fig. 1 is that the present invention utilizes the static discharge device of integrating circuit to constitute block diagram.
Fig. 2 is the clock transient phenomenon oscillogram that static discharge ESD phenomenon causes.
Fig. 3 is that the present invention utilizes the embodiment of the anti-locking apparatus of static discharge of integrating circuit to constitute block diagram.
To accompanying drawing major part symbol description
10,100: buffer 20,200: integrating circuit
30,300: voltage transformating part 40,400: central processing unit CPU
500: combinational circuit
Embodiment
To the exemplary embodiments that the present invention utilizes the static discharge of integrating circuit to prevent locking apparatus, as follows with reference to description of drawings:
It is to be made of following part that the present invention utilizes the anti-locking apparatus of the static discharge of integrating circuit: by the signal (ClockSource) of the inner various clocks source input that produces of buffer 10 receiving systems, and the integrating circuit 20 that is provided with for the unusual clock signal that detects the surge state that causes by Electrostatic Discharge; The voltage transformating part 30 that the unusual clock signal level that detects by integrating circuit 20 for reduction (Down) is provided with; Receive the unusual clock signal of voltage transformating part 30 outputs, and the clock source that comprises unusual clock signal refreshed that (Refresh) action is controlled and the central processing unit CPU 40 that is provided with.
As the anti-locking apparatus of the static discharge that utilizes integrating circuit of above-mentioned formation is to confirm the various clocks source state that produces in system separately.
For example, as shown in the following table, digital television system is to use various clocks.
Table 1
| Inscape | Clock (KLOCK) |
| MPEG compress technique system | 27 |
| The central processing unit CPU system | 10MHz，60MHz |
| Video display processor | 74.25MHz |
| Transmit | 2.69MHz |
| Audio frequency | 48MHz，3MHz |
| Quadrature amplitude balance system ntsc video decoder | 13.5MHz，27MHz |
Be described in detail, at first, receive the various clocks source that integrating circuit 20 internal system produce, and in the clock source of input, detect the unusual clock signal under the surge state that causes by Electrostatic Discharge by buffer 10.
Unusual clock signal under the surge state that is caused by Electrostatic Discharge is different with the clock under the normal condition, is the signal that has the high-frequency state in the very short time.
For example, if audio frequency (Video) clock then as shown in Figure 2, has 3MHz under normal condition, change but under the surge state that causes by Electrostatic Discharge, have the clock of about 40 μ s times.
The present invention is for the unusual clock signal under the surge state of distinguishing the clock signal under the normal condition and being caused by Electrostatic Discharge, the integrating circuit 20 that utilizes resistance and electric capacity to form, to the high-frequency composition, control according to the resistance and the capacitance of integrating circuit.
For example, if constitute integrating circuit 20 with resistance and the 0.01 μ F electric capacity of 1k Ω, then integrating circuit 20 output levels to the clock signal under the normal condition are 1.8V; And the unusual clock signal under the surge state that is caused by Electrostatic Discharge is output as 40 to 50V.
Because the unusual clock signal in integrating circuit 20 under the surge state that is caused by Electrostatic Discharge of output has bigger level, therefore can reduce (Down) integrating circuit 20 output levels by voltage transformating part 30.
That is, voltage transformating part 30 is to utilize comparator or adjuster (Regulator) etc., and integrating circuit 20 output levels are transformed to the incoming level that accords with central processing unit CPU 40.
Above-mentioned central processing unit CPU 40 is to receive integrating circuit 20 output signals by interruptive port.
Above-mentioned central processing unit CPU 40 receives the signal through integrating circuit 20 outputs of voltage transformating part 30 inputs, promptly, if the unusual clock signal under the surge state that is caused by Electrostatic Discharge is transfused to, then detect Electrostatic Discharge and produce, and there is the refresh activity in the clock source of unusual clock signal in control.
Embodiment
The embodiment that the present invention utilizes the anti-locking apparatus of the static discharge of integrating circuit as shown in Figure 3, be to constitute:, and be to detect to cause the integrating circuit 200 that the unusual clock signal under the surge state is provided with by static discharge (to call ESD in the following text) by the signal (Clock Source) of the inner various clocks source input that produces of buffer 100 receiving systems by following part; The sustaining voltage transformation component 300 that the unusual clock signal level that detects by integrating circuit 200 for reduction (Down) is provided with; The combinational circuit 500 that is provided with for the unusual clock signal of keeping voltage transformating part 300 outputs by certain hour; Receive the unusual clock signal of combinational circuit 500 outputs, and the clock source (Clock Source) that comprises unusual clock signal refreshed that (Refresh) action is controlled and the central processing unit CPU 400 that is provided with.
As the anti-locking apparatus of the static discharge that utilizes integrating circuit of above-mentioned formation, as the foregoing description explanation, in various clocks source,, utilize integrating circuit 200 usually for the unusual clock signal under the surge state of distinguishing the clock signal under the normal condition and causing by Electrostatic Discharge.
The high-frequency unusual clock signal that is caused by Electrostatic Discharge that has by integrating circuit 200 detections reduces the incoming level that accords with central processing unit CPU 40 through voltage transformating part 300.
For present embodiment,, import by the general I/O I/O port of central processing unit CPU 400 with the output signal of integrating circuit 200.
If utilize the general input/defeated I/O outbound port of central processing unit CPU 400, then minimum the holding time of periodic job (Periodic Task) needs (approximately 10ms) time, therefore central processing unit CPU 400 is in order to detect the unusual clock signal that is caused by static discharge ESD, utilize combinational circuit 500, keep the state time of the unusual clock signal of exporting by integrating circuit 200 by certain hour.
Central processing unit CPU 400 is according to the unusual clock signal through 500 inputs of voltage transformating part 300 and combinational circuit, and the refresh activity in the clock source that produces static discharge ESD phenomenon is controlled.
The present invention is when the clock that is caused by static discharge ESD that detects various clocks source becomes, and has utilized integration Shen road to detect.
Claims (4)
1. utilize the anti-locking apparatus of static discharge of integrating circuit, it is characterized in that constituting by following part:
The inner various clocks source that produces of receiving system causes the integrating circuit that the unusual clock signal of I under the surge state is provided with for detecting by static discharge;
The voltage transformating part that the unusual clock signal level of I that detects by integrating circuit for reduction is provided with;
Receive the unusual clock signal of II of voltage transformating part output, and the refresh activity that comprises the unusual clock signal clock of I source is controlled and the CPU that is provided with.
2. according to the anti-locking apparatus of the static discharge that utilizes integrating circuit described in the claim 1, it is characterized in that:
Described CPU receives unusual clock signal by interruptive port.
3. utilize the anti-locking apparatus of static discharge of integrating circuit, it is characterized in that constituting by following part:
The inner various clocks source that produces of receiving system, and cause the integrating circuit that the unusual clock signal of I under the surge state is provided with by static discharge for detecting;
The voltage transformating part that the unusual clock signal level of I that detects by integrating circuit for reduction is provided with;
In order to keep the combinational circuit that is provided with from the unusual clock signal of II of voltage transformating part output by certain hour;
Receive the unusual clock signal of III of combinational circuit output, and the refresh activity in the clock source that comprises the unusual clock signal of I is controlled and the CPU that is provided with.
4. according to the anti-locking apparatus of the static discharge that utilizes integrating circuit described in the claim 3, it is characterized in that:
Described CPU is to receive unusual clock signal by input/output end port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100504245A CN100365931C (en) | 2004-09-16 | 2004-09-16 | Static discharge preventer using integration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100504245A CN100365931C (en) | 2004-09-16 | 2004-09-16 | Static discharge preventer using integration circuit |
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|---|---|
| CN1750397A CN1750397A (en) | 2006-03-22 |
| CN100365931C true CN100365931C (en) | 2008-01-30 |
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| CNB2004100504245A Expired - Fee Related CN100365931C (en) | 2004-09-16 | 2004-09-16 | Static discharge preventer using integration circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923160A (en) * | 1997-04-19 | 1999-07-13 | Lucent Technologies, Inc. | Electrostatic discharge event locators |
| US6031405A (en) * | 1997-10-07 | 2000-02-29 | Winbond Electronics Corporation | ESD protection circuit immune to latch-up during normal operation |
| US6191633B1 (en) * | 1997-09-12 | 2001-02-20 | Nec Corporation | Semiconductor integrated circuit with protection circuit against electrostatic discharge |
| CN1413049A (en) * | 2001-10-15 | 2003-04-23 | Lg电子株式会社 | Device and method for preventing liquid crystal display be locked in mobile terminal |
| US20040174489A1 (en) * | 2003-03-04 | 2004-09-09 | Chih-Chiang Su | Electronic device and ESD prevention method thereof |
-
2004
- 2004-09-16 CN CNB2004100504245A patent/CN100365931C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923160A (en) * | 1997-04-19 | 1999-07-13 | Lucent Technologies, Inc. | Electrostatic discharge event locators |
| US6191633B1 (en) * | 1997-09-12 | 2001-02-20 | Nec Corporation | Semiconductor integrated circuit with protection circuit against electrostatic discharge |
| US6031405A (en) * | 1997-10-07 | 2000-02-29 | Winbond Electronics Corporation | ESD protection circuit immune to latch-up during normal operation |
| CN1413049A (en) * | 2001-10-15 | 2003-04-23 | Lg电子株式会社 | Device and method for preventing liquid crystal display be locked in mobile terminal |
| US20040174489A1 (en) * | 2003-03-04 | 2004-09-09 | Chih-Chiang Su | Electronic device and ESD prevention method thereof |
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| Publication number | Publication date |
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| CN1750397A (en) | 2006-03-22 |
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Owner name: NANJING LG XINGANG DISPLAY CO., LTD. Free format text: FORMER OWNER: LG ELECTRONICS (SHENYANG) CO., LTD. Effective date: 20070427 |
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Effective date of registration: 20070427 Address after: 210038 No. 346 Yao Yao Avenue, Nanjing economic and Technological Development Zone, Jiangsu, China Applicant after: LG Electronics Nanjing Display Co., Ltd. Address before: 110179 35,40, hi tech Development Zone, Liaoning, Shenyang Applicant before: LG Electronic (Shenyang) Co., Ltd. |
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