CN100364094C - A chip integrated with a FinFET circuit and a nanoelectromechanical beam and its manufacturing method - Google Patents

Abstract

The present invention relates to a chip integrated with a nano electromechanical beam by a FinFET circuit and a making method thereof. The product of the present invention comprises a chip body. The present invention is characterized in that the chip body comprises an electromechanical region and a circuit region, wherein the electromechanical region comprises a fixed end which is arranged on the chip body, a nano electromechanical beam with fixed single end or fixed double ends and an electromechanical region electrode; the circuit region comprises a circuit system which is built by using a FinFET as a unit; a FinFET unit comprises a source, drain, Fin and a grid; the grid crosses the Fin; the circuit region is connected with the electromechanical region by a metal lead wire; in the electromechanical region, the metal lead wire is connected with the fixed end or an electrode of the electromechanical region; in the circuit region, the metal lead wire is connected with the grid or the source or the drain of the FinFET unit of a circuit system; external connection ports of the circuit region and the electromechanical region are respectively communicated with external connection wiring. The present invention can be used for making an NEMS with high performance; besides, the integration level and the production efficiency of systems are greatly improved, and the production cost of industrialization is reduced. The present invention is mainly applied to fields, such as little-change environment of sensing, radio frequency, detection, etc.

Description

A chip integrated with a FinFET circuit and a nanoelectromechanical beam and its manufacturing method

technical field

The invention relates to a chip and a manufacturing method thereof, in particular to a chip integrated with a FinFET (Fin Field Effect Transistor) circuit and a nanoelectromechanical beam and a manufacturing method thereof. The method of the present invention organically combines deep submicron high-speed integrated circuits with nano-electromechanical systems (Nano-Electromechanical Systems, hereinafter referred to as NEMS) devices, can better solve the problem of signal extraction and processing of NEMS devices, and greatly improves the integration of the system degree and production efficiency.

Background technique

After entering the deep submicron scale, FinFET, a new type of MOS transistor structure with excellent performance, has been paid more and more attention, and has become an important development direction of transistors with broad prospects. Based on NEMS technology, new concepts of sensing, computing, communication, storage, execution and other devices can be realized, and its performance can break through the limits of existing conventional devices such as MEMS (micro-electromechanical systems) devices, and it has been improved by orders of magnitude. Including my country, NEMS It has become an important research hotspot worldwide. Nanoelectromechanical beams, a basic NEMS device structure, have very high resonance frequencies due to their scale effects and surface effects, and their motion or state is very sensitive to small changes in the environment. That is to say, nanoelectromechanical beams can be used to generate high-frequency vibrations, and can also be used for sensitivity and detection of small changes in the environment, so they have important applications in the fields of sensing, radio frequency, and detection. But one of the challenges in the development of NEMS is that it is difficult to extract and process signals.

Contents of the invention

In view of the above-mentioned signal extraction and processing problems of NEMS devices, the purpose of the present invention is to provide a chip integrating FinFET circuit and nano-electromechanical beam and its manufacturing method.

In order to achieve the above object, the present invention adopts the following technical solutions: a chip integrated with a FinFET circuit and a nanoelectromechanical beam, which includes a chip body, characterized in that: the chip body includes an electromechanical area and a circuit area, and the electromechanical area It includes a fixed end arranged on the chip body, a single-ended or double-ended fixed nanoelectromechanical beam and an electromechanical area electrode; the circuit area includes a circuit system constructed with FinFET as a unit, and the FinFET unit includes source and drain , Fin and gate, the gate spans the Fin, the circuit area and the electromechanical area are connected by metal leads, and the metal leads connect the fixed end of the electromechanical area or the electrodes of the electromechanical area and the The gate or source or drain of the FinFET unit in the circuit system in the circuit area, the external ports of the circuit area and the electromechanical area are respectively connected to external wiring.

A method for manufacturing a FinFET circuit and nanoelectromechanical beam integrated chip is characterized in that it includes the following steps: (1) selecting and cleaning the chip substrate; (2) coating photoresist on the surface of the substrate, and photoetching out circuit area, and doping the circuit area; (3) coating photoresist on the surface of the substrate, photoetching out the electromechanical area, and doping the electromechanical area; (4) doping the electromechanical area in the circuit The source, drain and Fin of the FinFET are formed in the electromechanical region, and the nanoelectromechanical beam, the fixed terminal and the electrode of the electromechanical region are formed in the electromechanical region; (5) silicon dioxide is formed by the overall thermal oxidation, and gate material is deposited on the surface of the silicon dioxide, and make a gate pattern; (6) apply photoresist on the whole, photoetch out the circuit area, and dope the circuit area; (7) deposit silicon dioxide on the whole, and open the silicon dioxide layer holes, exposing the external terminal of the FinFET circuit and the nanoelectromechanical beam, and the lead terminal connecting the circuit area and the electromechanical area; (8) depositing metal as a whole, and photoetching the metal lead pattern to complete the electrical connection between the FinFET circuit and the nanoelectromechanical beam. connection, and circuit wiring; (9) corroding all the silicon dioxide covering the nanoelectromechanical beam, releasing the nanoelectromechanical beam structure, and obtaining a chip product.

The source, drain and Fin of the FinFET are formed in the circuit area, and the photoresist ashing technology is adopted in the process of forming the nano-electromechanical beam, the fixed terminal and the electrode of the electromechanical area in the electromechanical area. The specific steps are as follows: (1) adopt Photoresist ashing technology forms nano-electromechanical beams and Fin micro-masks; (2) photoresist photolithography is used to form a mask including the fixed end of the nano-beams, the electrode mask of the electromechanical area, and the mask of the source and drain of the FinFET (3) form a composite mask through the mask pattern and the micromask, etch to form the source, drain and Fin of the FinFET in the circuit area, as well as electrodes in the electromechanical area, fixed terminals and unreleased nanoelectromechanical beams.

The source, drain and Fin of the FinFET are formed in the circuit area, and the side wall technology is used in the process of forming the nano-electromechanical beam, the fixed terminal and the electrode of the electromechanical area in the electromechanical area. The specific steps are as follows: (1) Deposit a layer of two Silicon oxide and a layer of polysilicon, polysilicon patterns are obtained after photolithography; (2) deposit a layer of silicon dioxide, and dry etch the silicon dioxide, thereby forming a sidewall structure composed of silicon dioxide; (3) engraving Etch polysilicon, leaving the side wall structure; (4) dry etching the silicon dioxide layer below to expose the silicon surface; (5) use photoresist photolithography to etch away the unnecessary side wall structure; (6) Use photoresist photolithography to form a mask pattern on the single crystal silicon device layer, use the mask pattern and the sidewall structure to form a composite mask, and perform etching to form the source and drain of the FinFET in the circuit region , Fin, and electromechanical region electrodes, fixed ends and unreleased nanoelectromechanical beams; (7) remove the silicon dioxide sidewall structure by dry etching.

In the process of forming the Fin of the FinFET in the circuit region and the nanoelectromechanical beam formed in the electromechanical region, one of electron beam exposure or common photolithography techniques is used to form the source and drain of the FinFET in the circuit region, and in the Common photolithography technology is used in the process of forming the fixed end of the electromechanical area and the electrode of the electromechanical area.

The grid pattern is formed by one of electron beam exposure, photoresist ashing and common photolithography.

The gate pattern is formed by sidewall technology, and the specific steps are as follows: (1) gate doping is performed on polysilicon by ion implantation; (2) a layer of silicon dioxide and a layer of polysilicon are deposited successively, and the polysilicon pattern is obtained after photolithography; (3) Deposit a layer of silicon dioxide, and dry-etch the silicon dioxide to form a sidewall structure made of silicon dioxide; (4) etch polysilicon, leaving a sidewall structure; (5) dry method Etch the silicon dioxide layer below to expose the silicon surface; (6) use photoresist photolithography to etch away unnecessary side wall structures; (7) photolithography forms the mask pattern of the gate, with the mask The pattern and the sidewall structure constitute a compound mask, and the polysilicon layer is etched to form a gate pattern.

One of the dry, sublimation, or wet methods is used to etch all of the silicon dioxide surrounding the nanoelectromechanical beams.

Because the present invention adopts the above technical scheme, it has the following advantages: 1. The present invention integrates the FinFET circuit and the nano-electromechanical beam on one chip, so that the deep submicron high-speed integrated circuit and the nano-electromechanical system device are organically combined, making the present invention The invented product integrates all the advantages of the two technologies, has extremely high performance indicators such as extremely high resonance frequency and sensitivity, and has broad application prospects. 2. Through process integration, the present invention creatively proposes a complete set of process methods for integrating FinFET circuits and nano-electromechanical beams in parallel processing using the same process, and realizes the integration of nano-electromechanical beams and peripheral signal lead-out circuits and signal amplification processing circuits. Chip integrated manufacturing, which better solves the difficult problem of NEMS device signal extraction and processing, facilitates the design, production and testing of NEMS, and will play a positive role in promoting the development of NEMS. 3. The present invention not only has great potential for producing higher-performance NEMS, but also greatly improves the integration degree and production efficiency of the system, and reduces the cost of industrial production. The invention has important applications in the fields of various sensing, radio frequency, detection of small changes in the environment, and the like.

Description of drawings

Fig. 1～Fig. 22 is the top view and cross-sectional view of technological process of the present invention

Fig. 23 is a three-dimensional schematic diagram of a device processed by the present invention (the silicon dioxide protective layer is not drawn).

24 to 36 are another embodiment of the process flow of the present invention (using sidewall technology to form nanoelectromechanical beams and Fin).

Figures 37 to 43 are yet another embodiment of the process flow of the present invention (using sidewall technology to form nanoelectromechanical beams, Fin and gate patterns)

Detailed ways

Example 1:

Using SOI (a layer of silicon oxide sandwiched between two layers of silicon) chip substrates, using photoresist ashing technology to make Fin and nano-electromechanical beams, using ordinary photolithography technology to make gate patterns, the specific steps are as follows:

1. Select SOI silicon wafer as the chip substrate 1 and clean it;

2. As shown in Figure 1 and Figure 2, use photoresist 3 photolithography (i.e. the usual photoetching method, hereinafter the same) to go out the circuit area 2, with photoresist 3 as a mask, ion implantation method (hereinafter the same) Same) Doping 4 to the circuit region 2, and then removing the photoresist 3;

3. As shown in Fig. 3 and Fig. 4, use the photoresist 5 to photoetch the electromechanical region 6, then use the photoresist 5 as a mask to dope the electromechanical region 6 7, and then remove the photoresist 5;

4. As shown in Fig. 5 and Fig. 6, the photoresist ashing technology is used to form the micromask 8 of the nanoelectromechanical beam and Fin;

5. Use photoresist photolithography to form the fixed end of the nano-electromechanical beam, the electrode of the electromechanical area, and the mask pattern of the source and drain of the FinFET;

6. As shown in Fig. 7 and Fig. 8, through the above-mentioned mask pattern and micromask 8 to form a composite mask, the single crystal silicon device layer is etched by dry method to form the source 9, drain 10 and Fin11 of the FinFET in the circuit area , and the fixed end 12 of the electromechanical area, the unreleased nanoelectromechanical beam 13 and the electrode 14 of the mechanical area, and then remove the photoresist and the micromask 8;

7. As shown in FIG. 9 and FIG. 10, the whole is thermally oxidized, and silicon dioxide 15 is grown as the gate dielectric of the FinFET;

8. Deposit a layer of gate material 16 on the surface of silicon dioxide 15, such as polysilicon, metal silicide or metal;

9. As shown in Fig. 11 and Fig. 12, use photoresist photolithography to etch the pattern of gate 17 by dry method, and then remove the photoresist;

10. As shown in Fig. 13 and Fig. 14, use photoresist 18 to photoetch out circuit region 19, use photoresist 18 as a mask to dope 20 to circuit region 19, and then remove photoresist 18;

11. As shown in FIG. 15 and FIG. 16 , deposit silicon dioxide 21 as a whole to form a circuit protection layer;

12. As shown in Fig. 17 and Fig. 18, through-holes are etched on the silicon dioxide 21 to expose the external terminals 22, 23, 24, 25 of the FinFET circuit and the nanoelectromechanical beam, and the connection between the circuit area and the electromechanical area lead terminals 26, 27, and then remove the photoresist;

13. As shown in Fig. 19 and Fig. 20, metal is deposited, and the metal lead pattern 28 is photoetched, so as to realize the electrical connection between the FinFET circuit and the nanoelectromechanical beam, and the wiring of the circuit;

14. As shown in FIG. 21 and FIG. 22 , use photoresist 29 to photoetch on the silicon dioxide 21, open the electromechanical area 30, expose the area of the nanoelectromechanical beam 13, and wrap the entire nanoelectromechanical beam 13 by wet etching Silica 21, to release the structure.

15. Removing the residual photoresist 29 to obtain a chip (as shown in FIG. 23 ) integrated with FinFET circuits and nanoelectromechanical beams of the present invention.

In the above embodiments, step 1 and step 2 are doped separately due to different doping requirements, but the doping sequence can be changed. The type of doping impurity (such as phosphorus, arsenic, etc.) and the doping dose can be changed.

Example 2:

In this embodiment, an SOI chip substrate is used, Fin and nanoelectromechanical beams are formed by using sidewall technology, and polysilicon gate patterns are formed by electron beam exposure. The specific steps are as follows:

1. As shown in FIG. 24, select the SOI chip substrate 31, and clean the substrate;

2, same as embodiment 1 (as shown in Fig. 1, Fig. 2), photolithography goes out circuit region, and take photoresist as mask, remove photoresist after the circuit region is doped;

3, same as embodiment 1 (as shown in Fig. 3, Fig. 4), photolithography goes out electromechanical region, and take photoresist as mask, remove photoresist after electromechanical region is doped;

4. As shown in FIG. 25, deposit a layer of silicon dioxide 32 and a layer of polysilicon 33 successively, etch to obtain polysilicon patterns, and then remove the photoresist;

5. As shown in FIG. 26, deposit a layer of silicon dioxide, and dry etch the layer of silicon dioxide, thereby forming a sidewall structure 34 made of silicon dioxide;

6. As shown in FIG. 27 , etch the polysilicon 33 by dry or wet method, leaving the side wall structure 34;

7. As shown in FIG. 28, dry etch the silicon dioxide layer 32 below to expose the surface of the SOI substrate 31;

8. As shown in FIG. 29, use photoresist photolithography to etch away the unnecessary sidewall structure 34 by wet method, leaving the required sidewall structure 34, and then remove the photoresist;

9. As shown in Figure 30, use photoresist photolithography to form a mask pattern on the single crystal silicon device layer, use this pattern and the above-mentioned side wall structure to form a composite mask, and perform dry etching on the single crystal silicon device layer , forming the source, drain, Fin35 of the FinFET and the unreleased nanoelectromechanical beam 36 including the fixed end of the nanoelectromechanical beam and the mechanical region electrode 37;

10. As shown in FIG. 31 , remove the silicon dioxide sidewall structure 34 by dry etching;

11. As shown in FIG. 32, the whole is thermally oxidized, and silicon dioxide 38 is grown as the gate dielectric of the FinFET;

12. As shown in FIG. 33 , deposit a layer of polysilicon 39 on the surface of silicon dioxide 38 as a gate material;

13. As shown in FIG. 34 , the polysilicon gate pattern 40 of the FinFET is formed by electron beam exposure, and the polysilicon 39 is dry etched, and then the photoresist exposed by the electron beam is removed;

14. Same as in Embodiment 1 (as shown in Figures 13 to 20), use photoresist to photoetch out the circuit area, and dope the circuit area; deposit silicon dioxide 21 as a whole to form a circuit protection layer; Through-holes 22, 23, 24, 25, 26, 27 are etched on the silicon oxide 21 by photolithography, exposing the external terminals of the FinFET circuit and the nanoelectromechanical beam, as well as the lead terminals connecting the circuit area and the electromechanical area;

15. As shown in FIG. 35, metal is deposited, and the metal lead pattern 41 is photoetched, so as to realize the electrical connection between the FinFET circuit and the nanoelectromechanical beam and the wiring of the circuit;

16. As shown in Figure 36, photolithography is carried out on the silicon dioxide, the electromechanical area is opened, all the silicon dioxide covering the nanoelectromechanical beam 36 is etched by dry method, the structure is released, and the photoresist is removed to obtain the present invention product.

Example 3:

In this embodiment, if Fin, nanoelectromechanical beams, and polysilicon gate patterns are all formed by sidewall technology, steps 1 to 12 are the same as in embodiment 2 (as shown in Figures 24 to 33), and the remaining steps for:

13. As shown in FIG. 37 , the surface of the polysilicon 39 as the gate material is doped by ion implantation, that is, the gate doping is completed;

14. As shown in Figure 38, it is the same as Step 4 of Example 2, depositing a layer of silicon dioxide 42 and a layer of polysilicon 43 successively, and obtaining a polysilicon pattern after photolithography, and silicon dioxide and polysilicon are also marked in the figure Figure 44 below is used as a reference;

15. As shown in Figure 39 (Figure 39 is a cross-sectional side view at the dotted line in Figure 38), deposit a layer of silicon dioxide, dry-etch this layer of silicon dioxide, thereby forming a sidewall structure made of silicon dioxide 45;

16. As shown in FIG. 40 , dry or wet etch the polysilicon 43 to leave a sidewall structure 45 ;

17. As shown in FIG. 41 , dry-etch the underlying silicon dioxide layer 42 to expose the surface of the polysilicon 39;

18. As shown in FIG. 42, use photoresist photolithography to etch away the unnecessary side wall mask 45, and remove the photoresist;

19. As shown in FIG. 43, form a mask pattern of the gate by photolithography, and use the pattern and the above-mentioned side wall structure to form a composite mask, and perform dry etching on the polysilicon layer 39 to form a gate pattern 46;

20. As shown in Figure 44, the circuit area is etched out by photolithography, and the circuit area is doped with the side wall 45 on the polysilicon gate pattern 46 as a mask. The figure 46 under the side wall 45 is also marked in the figure, and the gate Figure 44 under the oxide layer is used as a reference;

21. Same as steps 11 to 13 of Embodiment 1 (as shown in Figures 15 to 20), deposit silicon dioxide as a whole to form a circuit protection layer; etch through holes on the silicon dioxide to expose the FinFET circuit and The external terminal of the nanoelectromechanical beam, and the lead terminal connecting the circuit to the electromechanical area; depositing metal, engraving the metal lead pattern, so as to realize the electrical connection between the FinFET circuit and the nanoelectromechanical beam and the wiring of the circuit;

22. Photolithography is carried out on the silicon dioxide, the electromechanical area is opened, all the silicon dioxide covering the nanoelectromechanical beam is etched by sublimation method, the structure is released, the photoresist is removed, and the product of the present invention is obtained.

In the above-mentioned embodiments, the SOI substrate can be replaced by an equivalent SOI substrate deposited by film, such as a silicon substrate+silicon dioxide+polysilicon structure, etc.; Beam exposure technology, sidewall technology, photoresist ashing method, ordinary photolithography and other technical methods and means; in the selection of gate materials, polysilicon, metal silicide or metal gates can be used; When all the silica is released from the structure, various conventional etching techniques such as dry, sublimation or wet methods can be used.

Claims (10)

1. A chip integrated with a FinFET circuit and a nano-electromechanical beam, which includes a chip body, is characterized in that: the chip body includes an electromechanical area and a circuit area, and the electromechanical area includes a fixed part arranged on the chip body. terminal, single-ended or double-ended fixed nanoelectromechanical beams and electrodes in the electromechanical area; the circuit area includes a circuit system constructed with FinFET as a unit, and the FinFET unit includes source, drain, Fin and gate, and the gate spans all Fin, the circuit area and the electromechanical area are connected by metal leads, and the metal leads are connected to the fixed end of the electromechanical area or the electrode of the electromechanical area and the FinFET unit in the circuit system of the circuit area The gate or source or drain of the circuit area and the external ports of the electromechanical area are respectively connected to external wiring. 2. A method for manufacturing a FinFET circuit and nanoelectromechanical beam integrated chip, characterized in that: it comprises the following steps: (1) Select and clean the chip substrate; (2) coating photoresist on the surface of the substrate, photoetching out the circuit area, and doping the circuit area; (3) coating photoresist on the surface of the substrate, photoetching out the electromechanical region, and doping the electromechanical region; (4) Forming the source, drain and Fin of FinFET in the circuit area, forming nano-electromechanical beams, fixed terminals and electrodes in the electromechanical area in the electromechanical area; (5) forming silicon dioxide by overall thermal oxidation, depositing gate material on the surface of the silicon dioxide, and making a gate pattern; (6) Coating photoresist as a whole, photoetching out the circuit area, and doping the circuit area; (7) Deposit silicon dioxide as a whole, and open a hole in the silicon dioxide layer, exposing the external connection end of the FinFET circuit and the nanoelectromechanical beam, and the lead end connecting the circuit area and the electromechanical area; (8) Deposit metal as a whole, lithographically produce metal lead patterns, and complete the electrical connection between the FinFET circuit and the nanoelectromechanical beam, as well as the wiring of the circuit; (9) Corroding all the silicon dioxide covering the nanoelectromechanical beam, releasing the nanoelectromechanical beam structure, and obtaining a chip product. 3. The manufacturing method of a kind of FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 2, it is characterized in that: the source, drain and Fin of FinFET are formed in described circuit area, and nanoelectromechanical beam is formed in described electromechanical area , the fixed terminal and the electrodes in the electromechanical area, the photoresist ashing technology is used, and the specific steps are as follows: (1) Using photoresist ashing technology to form nano-electromechanical beams and Fin micro-masks; (2) photoresist photolithography is used to form the mask pattern comprising the fixed end of the nano-beam, the electrode mask of the electromechanical area and the mask of the source and drain of the FinFET; (3) A composite mask is formed by the mask pattern and the micromask, and etching is performed to form the source, drain, and Fin of the FinFET in the circuit area, as well as electrodes in the electromechanical area, fixed terminals, and unreleased nanoelectromechanical beams. 4. The manufacturing method of a FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 2, wherein: the source, drain and Fin of the FinFET are formed in the circuit area, and the nanoelectromechanical beam is formed in the electromechanical area , the fixed end and the electrodes in the electromechanical area adopt side wall technology, the specific steps are as follows: (1) Deposit one layer of silicon dioxide and one layer of polysilicon successively, and obtain polysilicon pattern after photolithography; (2) Deposit a layer of silicon dioxide, and dry etch the silicon dioxide to form a sidewall structure made of silicon dioxide; (3) Etching the polysilicon, leaving the side wall structure; (4) dry etching the silicon dioxide layer below to expose the silicon surface; (5) Use photoresist photolithography to etch away unnecessary side wall structures; (6) use photoresist photolithography to form a mask pattern on the single crystal silicon device layer, form a composite mask with the mask pattern and the sidewall structure, etch to form the FinFET in the circuit area Source, drain, Fin, and electromechanical region electrodes, fixed terminals and unreleased nanoelectromechanical beams; (7) The silicon dioxide sidewall structure is removed by dry etching. 5. The manufacturing method of a FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 2, characterized in that: the process of forming the Fin of the FinFET in the circuit area and the nanoelectromechanical beam formed in the electromechanical area One of electron beam exposure or ordinary photolithography is adopted in the process of forming the source and drain of FinFET in the circuit area, and the fixed terminal and electrode of the electromechanical area are formed in the electromechanical area. 6. The manufacturing method of a kind of FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 2 or 3 or 4 or 5, it is characterized in that: the grid pattern adopts electron beam exposure, photoresist ashing, ordinary light A form of engraving technology. 7. The manufacturing method of a FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 2 or 3 or 4 or 5, wherein the gate pattern is formed by sidewall technology, and the specific steps are as follows: (1) Gate doping of polysilicon by ion implantation; (2) A layer of silicon dioxide and a layer of polysilicon are deposited successively, and polysilicon patterns are obtained after photolithography. (3) Depositing a layer of silicon dioxide, dry etching the silicon dioxide, thereby forming a side wall structure composed of silicon dioxide; (4) Etching the polysilicon, leaving the side wall structure; (5) dry etching the silicon dioxide layer below to expose the silicon surface; (6) Use photoresist photolithography to etch away unnecessary side wall structures; (7) Forming a gate mask pattern by photolithography, using the mask pattern and the sidewall structure to form a composite mask, and etching the polysilicon layer to form a gate pattern. 8. The manufacturing method of a kind of FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 2 or 3 or 4 or 5, it is characterized in that: when corroding all silicon dioxide that wraps nanoelectromechanical beam, adopt dry method, One of the sublimation method or wet method. 9. The manufacturing method of a kind of FinFET circuit and nanoelectromechanical beam integrated chip as claimed in claim 6, is characterized in that: when corroding all silicon dioxide that wraps nanoelectromechanical beam, adopt dry method, sublimation method or wet method kind of. 10. The manufacturing method of a kind of FinlFET circuit and nano-electromechanical beam integrated chip as claimed in claim 7, is characterized in that: when corroding all silicon dioxide that wraps nano-electromechanical beam, adopt in method, sublimation method or wet method kind of.

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