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CN100359543C - 具有可寻址显示元件的矩阵显示器以及方法 - Google Patents

具有可寻址显示元件的矩阵显示器以及方法 Download PDF

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CN100359543C
CN100359543C CNB2004100644452A CN200410064445A CN100359543C CN 100359543 C CN100359543 C CN 100359543C CN B2004100644452 A CNB2004100644452 A CN B2004100644452A CN 200410064445 A CN200410064445 A CN 200410064445A CN 100359543 C CN100359543 C CN 100359543C
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display
display element
logic circuit
switch
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CN1591535A (zh
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肯·K·富
罗伯特·J·贝罗
平基·尤
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Motorola Mobility LLC
Google Technology Holdings LLC
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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示装置包括排列在矩阵中的多个显示元件(500)，每一显示元件包括显示像素(510)，所述显示像素耦合到开关(530)，每一显示元件包括可寻址锁存器(540)，所述锁存器具有输出，该输出耦合到该开关的控制输入，该可寻址锁存器具有行地址输入(532)和列地址输入(556)。在一种操作模式中，通过选择性地寻址显示元件，以第一速率激活至少一些显示元件并且以小于该第一刷新速率的第二速率激活其他显示元件。

Description

具有可寻址显示元件的矩阵显示器以及方法
技术领域
本公开总的来说涉及矩阵显示装置，更具体地说，涉及包括适于用在例如电池供电的无线通信装置这样的低功率电子装置中的可寻址显示元件矩阵的显示装置，以及方法。
背景技术
许多现有的矩阵显示装置，例如具有无RAM驱动器集成电路(IC)的薄膜晶体管(TFT)显示器，都在以下四种控制信号上操作：Vsync；Hsync；Dotclk以及OE信号。垂直同步(Vsync)信号或其他信号控制每一帧。水平同步(Hsync)信号或其他信号控制每一行。像素时钟(Dotclk)信号或其他信号控制每一像素。并且数据输出启用(OE)信号或其他信号确定输入数据是有效还是无效。当OE信号有效时同步于Vsync、Hsync和Dotclk信号写入数据。
现有技术图1说明了以60帧/秒(fps)使用的传统4×4矩阵TFT显示器的时序波形。在垂直时序波形中，Vsync脉冲指示新帧的开始。在每帧内，有四个Hsync脉冲对应于四个水平行的每一行。在水平时序波形中，Hsync脉冲指示新行的开始。在每一行内，有四个Dotclk脉冲对应于每一行中的四个像素中的每一个。OE信号在高时有效，指示输入是有效的显示数据。
通常已知通过调整OE时序信号来仅激活显示器的一部分，以便显示器部分无效。在现有技术图2中，OE时序信号仅在显示器的2和3水平行上有效，而在显示器的1和4行上无效，在这种情况下行1和4无效。根据垂直时序轴上的OE信号有效的时间，显示器的有效部分可以从任意行开始。部分屏幕的大小可以根据OE有效脉冲的持续时间在一行到全屏之间变化。OE信号无效的显示区域是非显示区域，在那里不显示图像。
在仔细考虑了下面的详细描述以及下面描述的附图的情况下，本公开的各方面、特点和优点对于本领域普通技术人员来说将变得更加明确。
附图说明
图1是一种用于全部有效显示器的现有技术的矩阵显示时序图。
图2是一种用于部分有效和部分无效显示部分的现有技术的矩阵显示时序图。
图3是具有以不同速率或频率寻址的有效显示元件的矩阵显示装置的示意图说明。
图4是示例性的可寻址显示元件的示意图。
图5是示例性的可寻址显示元件的更详细的示意图。
图6是一个包括多个单独可寻址显示元件的示例性显示装置。
图7是一个用于示例性矩阵显示装置的示例性时序图。
图8是一个具有控制时序和驱动器元件的显示装置的示例性示意图。
具体实施方式
图3说明了一种示例性显示装置300，例如，其可以是薄膜晶体管显示器，包括4×4(n×m)可寻址显示元件阵列。在其他实施例中也可以采用其他的显示器类型。根据本公开的一个方面，通常至少一些显示元件被以第一速率激活或寻址，例如刷新，而其他显示元件被以第二速率激活或寻址。例如，在图3中，四个中心有效显示元件310、312、314和3 16被以60帧/秒(fps)的速率寻址，而其余显示元件被以15fps的较低速率寻址。在一些实施例中，通过以低于其他显示元件的较低速率寻址至少一些显示元件，可以降低显示装置的功率消耗，这是因为功率与显示元件的寻址频率成正比。
图4说明了示例性的可寻址显示元件400，显示元件400通常包括耦合到开关420的显示像素410，例如，显示像素可以是液晶显示器(LCD)，或发光二极管(LED)，电子发光器(EL)等等，可以通过可寻址逻辑电路430启用和禁用所述开关。示例性的显示元件包括行电极450和列电极，它们都耦合到逻辑电路430。示例性的显示元件还包括到可寻址逻辑电路的行或列地址输入，其例子在下面进一步讨论。示例性的显示像素410包括与其并联放置的电容器，它们两个都耦合到偏压电极470。通常，开关420在逻辑电路输入满足逻辑条件时激活显示像素410。
图5是示例性的可寻址显示器元件500的更详细框图，其包括显示像素510和相应的并联电容器520。显示像素510耦合到开关530，例如，耦合到场效应管(FET)的源极或漏极。在其他的实施例中也可以使用其他的开关元件。示例性的逻辑电路包括可寻址锁存器540，该锁存器的输出耦合到开关530的控制输入。示例性的锁存器包括行地址比较器542和列地址比较器544，他们两个都具有耦合到逻辑门的输入上的输出，例如，逻辑门可以是AND门546。该示例性逻辑门的输出耦合到开关530，用于启用和禁用该开关。在图5中，还有电容器548，其耦合到开关530的输入并且耦合到逻辑门546的输出。示例性的AND门546的开关启用输出对电容器548充电，该电容器启用逻辑控制开关，从而激活显示元件。当显示元件被激活时，数据可以被写入显示元件的像素，例如，刷新像素或将新的数据写到像素中。在一个实施例中，像素电容器520的电容比开关启用电容器548的电容大得多。
在图5的一个示例性可寻址显示元件中，通过把行和列地址输入以及行电极和列电极输入应用到显示元件逻辑电路来激活显示元件，该显示元件逻辑电路如上所述控制逻辑控制开关530。比较器542比较行地址输入552和行电极输入，并且比较器544比较列地址输入556和列电极输入558。两个比较器542和544的输出通过启用和禁用开关530来控制显示像素的激活，其示例性操作在上面已经讨论了。在示例性实施例中，只有当行地址比较器的输出和列地址比较器的输出都是真时，才把数据写入显示元件像素。
来自行地址比较器和列地址比较器的输出被输入到AND门，AND门提供启用或禁用信号给充电电容器548，用来打开或关闭用于相应显示像素的开关。如果AND门的输出是真，那么开关电容548被充电，从而启用开关530。启用的开关530允许对电容器520充电，电容器520激活该示例性显示像素510，以便它可以被刷新或更新。如果AND门546的输出是假，那么就不对电容器548充电，晶体管保持在OFF，并且数据不能被写入显示像素510。
图6是一个示例性的显示装置600，其包括多个单独的可寻址显示元件，例如，图4或5中所述的示例性类型的可寻址显示元件。图7说明了对应于图6中的有效像素地址(Addr)5、6、9和10的第0、1、2和3行和列的示例性波形。如下面进一步讨论的，外部提供行地址(00，01，10，11)和列地址(00，01，10，11)。代表行和列地址的位数随着行和列数的增加而增加。在图7中，  “t1”是解码像素行地址和列地址的持续时间。“t2”是对开关启用电容器充电的持续时间，例如，开关启用电容器可以是图5中的开关电容548。开关启用电容器启用显示元件开关，其操作将在下面讨论。图7中，“VC1”是开关启用电容器的充电电压，开关启用电容器可以是，例如，图5中的电容548，并且，“VC2”是像素电容器的充电电压，像素电容器可以是，例如，图5中的电容520。对开关启用电容充电所需要的时间小于像素电容器，因为开关启用电容器的电容实际上小于像素电容器的电容。在图7中，“VC2”通常对于每一有效像素是不同的，这是因为每一像素的亮度通常是不同的。可替换的可寻址显示元件可以具有不同的时序信号图。
图3说明了Vsync、Hsync、Dotclk和OE信号，这些信号被提供给示例性的显示元件矩阵的行和列。图3也说明了应用到显示元件矩阵的行和列地址输入。在图8的显示器和驱动器示意图中，时序信号产生器810产生显示器输入信号，例如图3中说明的Vsync、HsyncDotclk和OE，(或等效信号)以及行地址和列地址输入。耦合到时序信号产生器的输出上的驱动器集成电路(IC)处理来自时序信号产生器的输入，并且输出高电压的行和列波形给显示器矩阵840，例如，图6中说明的薄膜晶体管显示矩阵阵列。
在图8中，基带处理器830经并行或串行接口产生用于时序信号产生器810的控制信号。通过提供包括可寻址显示元件矩阵的显示装置，例如包括图4和5所说明的那些元件的显示装置，可以通过寻址特定的显示元件激活显示器的所选部分。根据改变的显示需求，可以动态选择和改变有效显示部分的大小和位置。例如，可以重新配置显示器以基于有效窗口的大小来降低功率消耗。这些特点在低功率应用中很有用，例如，在包括电池供电的蜂窝电话的移动无线通信装置中以及希望降低功率消耗的装置中。在其他应用中，功率消耗未必是问题，并且可能主要希望选择性地控制显示元件的激活。
该示例性矩阵显示装置以及，更具体的说，它的显示元件可以被以不同的频率激活，以便例如用新的数据重写或刷新。在一些应用中，可能或希望以不同的速率激活显示元件组，例如降低功率消耗或降低处理和/或存储资源。全部功率消耗通常与频率成正比。在一个应用中，如图3所示，例如有效和背景窗口可以以不同的频率被寻址。即使有效和背景窗口的帧更新速率不同，该操作对用户也应该透明。根据下面的计算，与不包括降低一些显示元件的激活速率的传统显示操作相比，可以得到大约50％的功率节省。在下面的例子中，以60帧/秒(fps)激活四个(4)前景像素，并且以15fps激活十二(12)个背景像素。
功率(前景)＝60*4CS*V2   (@60fps)
功率(背景)＝15*12CS*V2  (@15fps)
总功率＝420 CS*V2
CS是像素电容器，例如，图4中的电容器440。通过比较，没有降低激活速率的功率，即所有16个显示元件都以60fps扫描的功率是60*16CS*V2＝960 CS*V2。比值是420/960＝44％。这种操作尤其在例如蜂窝手机这样的有待机操作模式的应用中是合乎需要的。
在其他实施例或应用中，只激活显示器的一部分，而显示器的其他部分没有被激活。如上所述，这可以通过选择性地用行和列地址输入寻址期望的显示元件来执行。因此，在上面讨论的示例性操作模式中，这些激活速率的一种可以使得一些显示元件没有被激活。
尽管已经以一种确立发明人对其的所有权以及能使本领域普通技术人员制造和使用本公开的方式描述了本公开和本发明的最佳模式，应该理解并且认识到，有许多等效于在此公开的示例性实施例的方式，并且在不脱离本发明的范围和精神的情况下可以进行修改和变形，本发明不受示例性实施例的限制而只受附加的权利要求的限制。

Claims (17)

1.一种激活具有n×m的显示元件阵列的显示装置中的显示元件的方法，每一显示元件都耦合到逻辑电路控制开关，该方法包括：
把行地址输入和行电极输入应用到该显示元件的逻辑电路控制开关的控制逻辑电路；
把列地址输入和列电极输入应用到该显示元件的逻辑电路控制开关的控制逻辑电路；
当该行地址和行电极输入以及当该列地址和列电极输入满足条件时，用逻辑电路控制开关激活该显示元件。
2.如权利要求1的所述方法，进一步包括：
比较该行地址输入和该行电极输入，
比较该列地址输入和该列电极输入，
基于比较结果用逻辑电路控制开关激活该显示像素。
3.如权利要求2的所述方法，其中，控制该逻辑电路控制开关包括用充电电容器启用和禁用该逻辑电路控制开关。
4.如权利要求1的所述方法，进一步包括：
以第一刷新速率激活该显示装置的至少一些显示元件，
以不同于第一刷新速率的第二刷新速率激活该显示装置的其他显示元件。
5.一种在包括n×m的可寻址显示元件阵列的显示装置中的方法，该方法包括：
以第一速率激活显示前景图像的至少一些显示元件；
以第二速率激活显示背景图像的其他显示元件，
该第二刷新速率小于该第一刷新速率；
当行地址和行电极输入以及当列地址和列电极输入满足条件时，用相应的逻辑电路控制的显示元件开关激活显示元件。
6.如权利要求5的所述方法，进一步包括：
比较该行地址输入和该行电极输入，
比较该列地址输入和该列电极输入，
使用比较结果用逻辑电路控制的显示元件开关激活该显示元件。
7.如权利要求6的所述方法，其中，用由比较结果控制的开关启用充电电容器启用和禁用该逻辑电路控制的显示元件。
8.如权利要求5的所述方法，其中，以第二速率激活其他显示元件包括不激活另一些显示元件。
9.一种显示装置，其包括：
排列在矩阵中的多个显示元件，
每一显示元件包括显示像素，该显示像素耦合到开关，
每一显示元件包括可寻址锁存器，所述锁存器具有输出，该输出耦合到所述开关的控制输入，
所述可寻址锁存器具有行地址输入和列地址输入，
所述可寻址锁存器具有行电极输入和列电极输入。
10.如权利要求9的所述装置，其中，
每一显示元件的可寻址锁存器包括具有相应输出的行地址逻辑电路和列地址逻辑电路，所述输出耦合到可寻址锁存器的输出，
所述行地址输入耦合到所述行地址逻辑电路，所述列地址输入耦合到所述列地址逻辑电路。
11.如权利要求9的所述装置，其中，
每一显示元件的可寻址锁存器包括第一和第二比较器，该第一比较器具有行地址输入和行电极输入，该第二比较器具有列地址输入和列电极输入，
每一显示元件包括逻辑装置，该逻辑装置具有第一输入，该第一输入耦合到相应的第一比较器的输出，并且该逻辑装置具有第二输入，该第二输入耦合到相应第二比较器的输出。
12.如权利要求11的所述装置，其中，该逻辑装置是AND门，可寻址锁存器的输出是该逻辑装置的输出。
13.如权利要求11的所述装置，其中，像素电容与该显示像素并联，并且开关启用电容器耦合到该开关的输入。
14.如权利要求9的所述装置，其是薄膜晶体管显示装置。
15.一种用在包括n×m的可寻址显示元件阵列的显示装置中的方法，该方法包括：
通过单独地寻址将要被激活的显示元件来选择性地激活显示元件，激活所述显示元件包括；
把行地址输入和行电极输入应用到相应显示元件的控制逻辑电路；
把列地址输入和列电极输入应用到相应显示元件的控制逻辑电路；
当控制逻辑电路输入满足条件时，用逻辑电路控制开关激活该显示元件；
通过以第一频率寻址至少一些显示元件并且以第二频率寻址其他显示元件来降低功率消耗，第二频率小于第一频率。
16.如权利要求15的所述方法，进一步包括：
用该控制逻辑电路比较该行地址输入和该行电极输入，
用该控制逻辑电路比较该列地址输入和该列电极输入，
通过使用比较结果启用逻辑电路控制开关来激活显示元件。
17.如权利要求16的所述方法，用受控制逻辑电路控制的开关启用电容器来启用和禁用该逻辑电路控制开关。
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GB2405522A (en) 2005-03-02
FI124688B (fi) 2014-12-15
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US7295199B2 (en) 2007-11-13
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US20050057552A1 (en) 2005-03-17
DE102004040987A1 (de) 2005-04-28
GB0418779D0 (en) 2004-09-22
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FI20041081L (fi) 2005-02-26
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DE102004040987B4 (de) 2007-11-08
RU2004125803A (ru) 2006-02-10

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