CN100356779C

CN100356779C - Memory storage method capable of improving image processing efficiency

Info

Publication number: CN100356779C
Application number: CNB2003101235203A
Authority: CN
Inventors: 张义树; 黄昭智
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2003-12-24
Filing date: 2003-12-24
Publication date: 2007-12-19
Anticipated expiration: 2023-12-24
Also published as: CN1633165A

Abstract

The present invention provides a memory storage method for improving the efficiency of image processing. The method comprises: storing a plurality of first macroblocks corresponding to a first picture area of a picture in a first storage area of a memory; storing a plurality of second macroblocks corresponding to a second picture area of the picture in a second storage area of the memory; and storing at least one second macroblock corresponding to a portion of the second picture area adjacent to the first picture area in the first storage area.

Description

Can promote the memory storage method of image processing efficient

Technical field

The present invention relates to a kind of memory storage method, particularly a kind of memory storage method that can promote image processing efficient.

Background technology

Along with the lifting of electronic circuit arithmetic speed, need the sound processing of a large amount of computings to become many subjects under discussion of being attracted attention then.The user also improves accordingly to the raising that image resolution requires.With high definition TV (HDTV, High-Definition Television) specification, the resolution of its picture can reach individual pixel of 1088 (vertically) of 1920 (laterally) *.On the other hand, in the image processing process of carrying out moving picture expert group (MPEG, Moving Picture Experts Group) specification or other compensation (motioncompensation) computing of need taking exercises, often to carry out the reading of block image (block based image) of different motion vector (motionvector) to an internal memory (as DRAM (Dynamic Random Access Memory)--DRAM, Dynamic Random access Memory).Yet, just must stride to be listed as in the above-mentioned image processing process and read, to obtain required motion vector to this internal memory when this internal memory one row (row) pairing picture width during less than the width of a high resolution pictures (HDTV specification as the aforementioned).For example the every row of a DRAM have 256 characters (word), and its corresponding picture width is 1024 pixels, then desire under the resolution of 1920*1088 pixel, to carry out the MPEG related operation will produce stride row read.And these are striden row and read the delay that control signal produced such as pairing RAS/CAS and can reduce image processing efficient.

Summary of the invention

Therefore main purpose of the present invention is to provide a kind of memory storage method that can promote image processing efficient, to address the above problem.

The invention provides a kind of memory storage method, be used for promoting image processing efficiency, this method has: store a plurality of first blocks corresponding to first picture area of a picture in first storage area of an internal memory; At a plurality of second blocks of second storage area of this internal memory storage corresponding to second picture area of this picture; And at least one second block of this first storage area storage corresponding to this second picture area part adjacent with this first picture area.

When the pairing picture width of this internal memory one row during less than the width of a high resolution pictures, must not stride row and read, just be obtained as the motion compensation required motion vectors (motion vector) of computing such as (motion compensation) to this internal memory.Therefore method of the present invention can promote image processing efficient.

The accompanying drawing summary

Fig. 1 can promote the schematic flow sheet of the memory storage method of image processing efficient for the present invention.

Fig. 2 is the schematic diagram of picture of the method for Fig. 1.

Fig. 3 is the schematic diagram of storage area of the method for Fig. 1.

The reference numeral explanation

200 pictures
200 pictures	210,220,222 picture areas
300 internal memories	210,220,222 picture areas
300 internal memories	310,320 storage areas
(1,1), (1,2) ..., (68,120) block	310,320 storage areas
(1,1), (1,2) ..., (68,120) block	L0, L1, L2 width

Embodiment

Please also refer to Fig. 1, Fig. 2 and Fig. 3, Fig. 1 can promote the schematic flow sheet of the memory storage method of image processing efficient for the present invention, and Fig. 2 is the schematic diagram of picture of the method for Fig. 1, and Fig. 3 is the schematic diagram of storage area of the method for Fig. 1.The invention provides a kind of memory storage method, be used for promoting image processing efficiency.The order of following steps and non-limiting scope of the present invention, this method is described as follows.

Step 10: a plurality of first blocks (1 that store corresponding to first picture area 210 of a picture 200 in first storage area 310 of an internal memory 300 (is DRAM (Dynamic Random Access Memory) at present embodiment--DRAM, Dynamic Random Access Memory), 1), (1,2) ..., (68,60);

Step 20: store in second storage area 320 of internal memory 300 a plurality of second blocks (1,61) corresponding to second picture area 220 of picture 200, (1,62) ..., (68,120); And

Step 30: store in first storage area 310 at least one second block (1,61) corresponding to this second picture area part 222 adjacent, (2,61) with this first picture area ..., (68,61).

In the present embodiment, these blocks (are Fig. 2 and block (1 shown in Figure 3,1), (1,2) ..., (68,120)) be the macro zone block (macroblock) that meets MPEG (Moving Picture Experts Group--moving picture expert group) specification, wherein each block is the individual pixel of 16 (vertically) of 16 (laterally) * (pixel is not shown in relevant indicators) corresponding to picture 200.And the picture 200 of present embodiment is HDTV (High-Definition Television--high definition TV) picture, and its resolution is individual pixel of 1088 (vertically) of 1920 (laterally) *, so picture 200 has individual block of 68 (vertically) of 120 (laterally) *.Wherein be stored in first block (1 of first storage area 310,1), (1,2) ..., (68,60) with second block (1,61), (2,61) ..., (68, putting in order 61) is corresponding block (1 corresponding to picture 200,1), (1,2) ..., the putting in order of (68,61).Be stored in addition second storage area 320 second block (1,61), (1,62) ..., (68,120) put in order be corresponding to picture 200 corresponding block (1,61), (1,62) ..., the putting in order of (68,120).

When reading this macro zone block (for example being the 16*16 pixel), neither can the generation striden reading of row to this internal memory, so, just avoided striding row because of these and read the delays that control signal produced such as pairing RAS/CAS.

In the present embodiment, the width of picture 200 (i.e. 120 blocks, corresponding to 1920 pixels) is greater than the width L0 of internal memory 300 each row (row) (i.e. 64 blocks, corresponding to 1024 pixels).And the width L2 of the width L1 of first storage area 310 (i.e. 61 blocks, corresponding to 976 pixels) and second storage area 320 (i.e. 60 blocks, corresponding to 960 pixels) is the width L0 that is less than or equal to internal memory 300 each row.As Fig. 3 and shown in Figure 2, the width L1 of first storage area 310 is width (i.e. 60 blocks for first picture area 210, corresponding to 960 pixels) add that these blocks (are block (1,1), (1,2) ..., (68,120)) in a block (as block (1,61), (2,61) ... or (68,61)) width (corresponding to 16 pixels).

The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. a memory storage method is used for promoting image processing efficiency, and this method includes:

At a plurality of first macro zone blocks of first storage area of internal memory storage corresponding to first picture area of a picture;

At a plurality of second macro zone blocks of second storage area of this internal memory storage corresponding to second picture area of this picture; And

At at least one second macro zone block of this first storage area storage corresponding to this second picture area part adjacent with this first picture area.

2. the method for claim 1, wherein this internal memory is a DRAM (Dynamic Random Access Memory).

3. the method for claim 1, wherein described a plurality of first and second macro zone blocks meet the MPEG specification.

4. the method for claim 1, wherein the width of this first storage area adds the width of the macro zone block in these macro zone blocks for the width of this first picture area.

5. the method for claim 1, wherein, first macro zone block that is stored in this first storage area and putting in order of second macro zone block are corresponding to the putting in order of the corresponding macro zone block of this picture, and the putting in order of second macro zone block that is stored in this second storage area is putting in order corresponding to the corresponding macro zone block of this picture.

6. the method for claim 1, wherein the width of the width of this first storage area and this second storage area is less than or equal to the width of these each row of internal memory.

The method of claim 1, wherein the width of this picture greater than the width of these each row of internal memory.