CN100356315C - Design method of number mixed multipler for supporting single-instruction multiple-operated - Google Patents
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Abstract
The present invention discloses a design method of a number mixed multiplier for supporting single instruction and multiple operands. The goal of the present invention is to enable a multiplier to work in a normal mode and an SIMD mode. The present invention has the technical scheme that a new mixing multiplier structure is designed; the new mixing multiplier structure is composed of an operand extending component, an encoder, two partial product generators, a correction value generating component, a partial product compression component and an adder, wherein the encoder is used for judging working modes and operand types; the operand extending component is used for extending operands; the two partial product generators respectively generate n/2+1 partial products to be sent to the partial product compression component; the correction value generating component generates a correction value for a high-order product in the SIMD mode; the partial product compression component compresses the partial products and the correction value into two 4n-order digitals; the adder is used for adding the two 4n-order digitals to obtain a 4n-order product. Under the normal mode, the 4n-order product is the product of two 2n-order operands; under the SIMD mode, the low 2n orders of the 4n-order product is the product of low n-order multiplication, and the high 2n orders of the 4n-order product is the product of high n-order multiplication.
Description
Technical field: the present invention relates to the method for designing of multiplier in digital signal processor (DSP) and the high-performance microprocessor, especially support the method for designing of the multiplier of single instrction multioperand (SIMD).
Background technology: multiplier is a vitals in DSP and the microprocessor, and in fields such as science calculating and digital signal processing, multiply operation is used in a large number.The tradition multiplier generally is made up of operand widening parts, code translator, partial product production part, partial product compression member and a totalizer.In the design of high-performance multiplier, it is a gordian technique that partial product produces.2 Booth coding circuits are owing to simplicity of design, and the partial product number of generation is few, is widely adopted in Multiplier Design at present.Along with the development of infotech, the processing of multi-medium datas such as video, audio frequency has become the important applied field of digital signal processing.The distinguishing feature that multi-medium data is handled is that a plurality of little data item are carried out same computing, in order to improve the ability that multi-medium data is handled, many processors have all increased the SIMD instruction, make processor carry out an instruction and can finish a plurality of short data computings.The realization of SIMD instruction has dual mode, and a kind of is that special SIMD parts are set, and these parts only can be carried out the SIMD operation, as the MMX parts in the Pentium II processor; Another kind is that traditional scalar operation device is improved, and makes it both keep the scalar operation ability, possesses the ability of carrying out the SIMD operation again, as Intel XScale
TMA kind of implementation method in back does not need that architecture is carried out big change just can make its multi-medium data processing power improve several times, therefore in the design of embedded microprocessors such as DSP, obtained using widely, all adopted this method as the design of the up-to-date DSP multiplier of TI (Texas Instrument) company and AD (analog device) company.Thisly not only support a long data multiply operation but also support the multiplier of a plurality of short data multiply operations to be called as mixed multiplier.Consider operand is represented in the computing machine characteristics and design complexities, mixed multiplier generally only supports two short data to carry out multiply operation simultaneously, a kind of very directly method that designs this mixed multiplier is that a plurality of multipliers are set, and shortcoming is that hardware spending is big; Another kind method is to adopt the flowing water technology, as Intel XScale
TM, its shortcoming is to have improved CPI, i.e. the beat number of individual instructions execution.Therefore, high-performance, low-power consumption microprocessor Design press for a kind of new mixed multiplier efficiently.
Summary of the invention: the technical problem to be solved in the present invention provides a kind of new mixed multiplier, makes that under the situation that only increases a small amount of hardware expense, multiplier both can be operated in general mode, can be operated in the SIMD pattern again.Technical scheme is a kind of new mixed multiplier structure of design, by the current mode of operation of control signal indication multiplier, as long as the summation that adds up just can obtain the product of general mode and SIMD pattern correspondence to partial product.Suppose that operand 1 and operand 2 are respectively multiplicand and multiplier, their word length is the 2n position, and the mixed multiplier of the present invention's design can be finished a 2n * 2n multiply operation under general mode; When being operated under the SIMD pattern, it all regards the operand of each 2n position the short operation number of two n positions as, at this moment can finish two n * n multiply operation simultaneously.
The concrete technical scheme of the present invention is: mixed multiplier is made up of operand widening parts, code translator, partial-product generator 1, partial-product generator 2, modified value production part, partial product compression member and totalizer.Code translator is according to the control signal judgment task pattern of input and the type of operand, and widening parts and the work of modified value production part are counted in control operation.The operand widening parts is expanded operand under the control of code translator, and multiplicand 1 and multiplier 1 after the expansion are delivered to partial-product generator 1, and multiplicand 2 and multiplier 2 are delivered to partial-product generator 2.Two each generation (n/2+1) individual partial products of partial-product generator are delivered to the partial product compression member.When the modified value production part produces the SIMD pattern under the control of code translator to the modified value of high-order product.The partial product compression member is compressed into (n+2) individual partial-product sum the number of two 4n positions from the modified value of modified value production part input.Totalizer obtains the product of a 4n position to the several additions from two 4n positions of partial product compression member input.
The operand widening parts of mixed multiplier is expanded operand 1 and operand 2, produces two multiplicands respectively and two multipliers are delivered to two partial-product generators.The length of multiplicand 1 and multiplicand 2 is the 2n+2 position, and under general mode, the low 2n position of multiplicand 1 and multiplicand 2 equals operand 1, simultaneously high two sign bits that are extended to operand 1; Under the SIMD pattern, the low n position of multiplicand 1 equals the low n position of operand 1, and n to the 2n+1 position of multiplicand 1 all is extended to the sign bit of the low n position of operand 1; The low n position of multiplicand 2 is the high n position that 0, the n to the 2n-1 position equals operand 1, and the highest two is the sign bit that 2n and 2n+1 position expand to the high n position of operand 1; The length of multiplier 1 and multiplier 2 all is the n+3 position, multiplier 1 mainly comes from the low n position of operand 2, multiplier 2 mainly comes from the high n position of operand 2, the operand widening parts also will respectively be expanded 1 prefix and 2 bit sign positions in the front and back of multiplier 1 and multiplier 2, the prefix of multiplier 1 is 0, the sign bit of multiplier 2 is consistent with the sign bit of operand 2 high n positions, and the prefix of the sign bit of multiplier 1 and multiplier 2 is different configurations under different mode of operations.
The present invention also adopts two Booth multiplication to produce partial product.The generation separated into two parts of mixed multiplier partial product is finished by partial-product generator 1 and partial-product generator 2 respectively, and they are equivalent to the partial-product generator of a 2n * n multiplier respectively, produces low level and high-order (n/2+1) individual partial product respectively.Under the SIMD pattern, the sign bit of low level product is can exert an influence to high-order product in 1 o'clock, and the present invention has designed a modified value production part and produced high-order product modified value the high 2n position of product is revised, and makes that the sign bit of low level product is 0.The method that adopts two Booth multiplication to produce partial product is:
A partial product is obtained through displacement and negate under controlling by multiplicand 3 adjacent bits in multiplier.After multiplicand was determined, the various combination of 3 adjacent bits can produce different partial products in the multiplier.Suppose that b is a multiplier; b
kIt is the k position of multiplier.In common two Booth multipliers, the multiplication of a 2n * 2n need produce n+1 partial product.The 1st partial product is by [b
1, b
0, 0] and control produces, and (the individual partial product of 1＜k＜n+1) is by [b for k
2k-1, b
2 (k-1), b
2k-3] the control generation, n+1 partial product is by [s, s, b
2n-1] control produces, b wherein
2n-1Be the most significant digit of multiplier, s is a sign bit, when multiplier is signed number, and s=b
2n-1, when multiplier is unsigned number, s=0.The power q that supposes partial product partial product when adding up the to move right figure place of (to high-order direction displacement), then the power q of k partial product
k=2 (k-1).
The partial product production part is made up of partial-product generator 1 and partial-product generator 2.The input of partial-product generator 1 is multiplicand 1 and multiplier 1, and the input of partial-product generator 2 is multiplicand 2 and multiplier 2.Partial-product generator 1 produces (n/2+1) individual partial product of low level, and partial-product generator 2 produces high-order (n/2+1) individual partial product.Partial-product generator 2 is determined the value of its Senior Three sign bit of first partial product according to mode of operation.
When mixed multiplier is operated in general mode, the 1st to n/2 partial product of partial-product generator 1 and general multipliers the 1st identical respectively to the production method and the power of n/2 partial product; (n/2+1) individual partial product of partial-product generator 1 is 0.Partial-product generator 2 the 1st identical respectively to the production method and the power of (n+1) individual partial product to (n/2+1) of (n/2+1) individual partial product and general multipliers.Therefore when general mode, the partial product of mixed multiplier and general multipliers is just the same, and (n+2) individual partial product of mixed multiplier is added up promptly obtains the product of a 2n * 2n multiplication.At this moment, the prefix of the sign bit of multiplier 1 and multiplier 2 all is changed to b
N-1
When mixed multiplier was operated in the SIMD pattern, the high n position of the multiplicand 1 of partial-product generator 1 expanded to the symbol of operand 1 low n position, and two sign bits of multiplier 1 expand to the sign bit of operand 2 low n positions; Produce the 1st identical during with general mode to the control code of n/2 partial product; The 1st is identical during with general mode to the power of n/2 partial product; (n/2+1) individual partial product is by [s, s, b
N-1] control generation, wherein b
N-1Be the most significant digit of low n position multiplier, s is a sign bit, when the low level multiplier is signed number, and s=b
N-1, when the low level multiplier is unsigned number, s=0; The power of (n/2+1) individual partial product is n.Under the SIMD pattern, the low n position of the multiplicand 2 of partial-product generator 2 is changed to 0, and high n position remains unchanged, and the prefix of multiplier 2 is 0; The control code of the 1st partial product of the generation of partial-product generator 2 is by [b
N-1, b
n, b
N-1] become [b
N+1, b
n, 0]; The remainder of partial-product generator 2 is identical when amassing with general mode; The power of partial-product generator 2 all partial products remains unchanged.In fact, under the SIMD pattern, each partial-product generator all is equivalent to the partial-product generator of the multiplier of a 2n * n.The long-pending low portion that is positioned at the partial product of partial-product generator 1 of the live part of low n positional operand multiplication; The long-pending high-order portion that is positioned at the partial product of partial-product generator 2 of the live part of high n positional operand multiplication.
Because the low n position of the partial product of partial-product generator 2 is 0, the n position even the 1st minimum partial product of power all will move right when adding up, therefore the partial product of partial-product generator 2 can not exert an influence to the result of low 2n position, and the low 2n position of the result after adding up is exactly the product of low level n * n multiplication.Though the partial product of high-order multiplication can not exert an influence to the low level product, the sign bit of low level multiplication partial product can produce carry to high-order product when adding up.Therefore,, must add a modified value, eliminate of the influence of the sign bit of low level product high-order product to the result of high 2n position in order to obtain correct result.The sign bit of low level product or be 0 entirely, or be 1 entirely.If can make the sign bit of low level product expand to the most significant digit of high-order product, when the sign bit of low level product was 0, the low level product can not exert an influence to high-order product, and this moment, the lowest order at high-order product added one 0; When the sign bit of low level product is 1, as long as add one 1, just can make the symbol at high-order product place of low level product become 0 at the lowest order of high-order product, can not exert an influence to high-order product yet.For the sign bit that makes the low level multiplication expands to the most significant digit of high-order product, add (2 in the highest (n-1) position of high-order product
N-1-1).Therefore, the modified value under the SIMD pattern is made up of two parts, be added in high-order product lowest order 0 or 1 and be added in (2 on height (n-1) position
N-1-1), this modified value is produced under the control of code translator by the modified value production part.
The partial product compression member is compressed into the high-order result's of (n+2) individual partial-product sum of two partial-product generators generations modified value (under general mode, this modified value is complete 0) number of two 4n positions.This two numbers addition, finally obtain the product of a 4n position by totalizer.Under general mode, it is exactly the product of two 2n positional operands; Under the SIMD pattern, low 2n position is the product of low n position multiplication, and high 2n position is the product of high n position multiplication.
Adopt the present invention can produce following technique effect:
1. the present invention has made full use of the hardware resource in the multiplier, with less hardware spending, the partial product production part is divided into two partial-product generators, the production part of a modified value of design, increase corresponding circuit in the partial product compression member, the ability that makes the processing short operation count multiply operation is doubled.
2. do not feed back between each parts of multiplier that adopt the present invention to design, be divided into several flowing water station easily, to obtain higher performance.
Description of drawings:
Fig. 1 is the building-block of logic of general multipliers;
Fig. 2 is the dot product figure of common 16 multiplier partial products;
Fig. 3 is the dot product figure that adopts the partial product of 16 mixed multiplier that the present invention realizes;
Fig. 4 is that modified value produces principle schematic;
Fig. 5 is the building-block of logic that adopts the mixed multiplier of the present invention's design;
Embodiment:
Fig. 1 is the logical diagram of general multipliers, and general multipliers is made up of operand widening parts, code translator, partial product production part, partial product compression member and totalizer.The operand widening parts carries out to operand 1 and operand 2 under the control of code translator that sign extended becomes multiplicand and multiplier is input to the partial product production part, the partial product production part produces (n+1) individual partial product, partial product compression member handle (n+1) individual partial product is compressed into the number of two 4n positions, by a totalizer this two numbers summation is obtained the product of a 4n position at last.
Fig. 2 is the dot product figure of common 16 multiplier partial products of a power of having considered partial product, and the most significant digit of partial product is on the right side, and lowest order is in the left side.E among the figure is the symbol of partial product, and whether the S indicating section is long-pending passes through the negate supplement, when partial product needs the negate supplement, is not the complement code that is converted to its radix-minus-one complement immediately, represents but add 1 redundant form by the lowest order of radix-minus-one complement at it.Fig. 3 is the dot product figure of partial product that adopts 16 (2n) the position mixed multiplier of the present invention's design, and wherein 1-5 partial product is by partial-product generator 1 generation, and n/2+1=5 partial product is 0.6-10 partial product produced by partial-product generator 2.The 6th partial product is equivalent to the 5th partial product among Fig. 3, at this moment its Senior Three position E when general mode
1E
2E
3=E10; When the SIMD pattern, the 6th partial product is the 1st partial product of high-order portion multiplication, its Senior Three position
Expression E's is non-.This is because when adopting 2 Booth codings, the method difference of the 1st partial-product sum remainder product code expansion.
Describe with 16 multiplication principle that to be example produce modified value of the present invention among Fig. 4.Realize the multiplication of low portion among Fig. 3 among the figure with 1 16 multiplier, method is 8 of the sign bit of the multiplicand of low level multiplication and multiplier expansions, can obtain the partial product shown in Fig. 4 (a).After the partial product addition among Fig. 4 (a), can obtain the result of Fig. 4 (b), wherein S=0 or 1.The partial product of the low level multiplication in the I zone among the partial product among Fig. 4 (a) and Fig. 3 is compared, can find that Fig. 4 (a) has just added 32 ' hfe00_0000, " fe " is 71 hexadecimal representation among the area I I on right side among Fig. 4 (a).When the sign bit of low portion product among Fig. 3 was 0, the present invention added 32 ' hfe00_0000 to the partial product of area I among Fig. 3; When the sign bit of low portion product is 1, the present invention adds 32 ' hfe01_0000 to the partial product of area I among Fig. 2, can make among Fig. 3 the net result of partial product in the area I become result among Fig. 4 (c), promptly the sign bit of low level product can not exert an influence to high-order product.Added value 32 ' hfe00_0000 or 32 ' hfe01_0000 are modified value.
Fig. 5 is the structural drawing that adopts the mixed multiplier of the present invention's design, and it is made up of operand widening parts, code translator, partial-product generator 1, partial-product generator 2, modified value production part, partial product compression member and totalizer.Compare with general multipliers, the operand widening parts of mixed multiplier under the SIMD pattern, also be extended to sign bit to the n to the of multiplicand 1 (2n-1) position except carrying out general sign extended, and the low n position of multiplicand 2 will be changed to 0; Multiplier 1 and multiplier 2 also are to be produced by the operand widening parts.The partial product of mixed multiplier is produced by two partial-product generators, the individual partial product of each generation (n/2+1), and partial-product generator 2 need be determined the value of its Senior Three position of first partial product according to mode of operation.The modified value production part produces high-order result's modified value according to the sign bit of control signal and multiplicand 1 and multiplier 1.The partial product compression member is compressed into the high-order result's of (n+2) individual partial-product sum of two partial-product generators generations modified value the number of two 4n positions.By a totalizer this two number is sued for peace at last and obtain the product of a 4n position, under general mode, it is exactly the product of two 2n positional operands; Under the SIMD pattern, low 2n position is the product of n position multiplication, and high 2n position is the product of high n position multiplication.
Claims (4)
1. mixed multiplier of supporting the single instrction multioperand, comprise the operand widening parts in its mixed multiplier structure, code translator, partial-product generator, partial product compression member and totalizer, adopt two Booth multiplication to produce partial product, it is characterized in that also designing in the mixed multiplier structure modified value production part is arranged, the partial product production part is designed to two parts, by partial-product generator 1, partial-product generator 2 is formed, they are equivalent to the partial-product generator of a 2n * n multiplier respectively, produce low level and n/2+1 high-order partial product respectively, by a current mode of operation of control signal indication multiplier, code translator is according to the type of control signal judgment task pattern and operand, widening parts and the work of modified value production part are counted in control operation, the operand widening parts is under the control of code translator, operand is expanded, multiplicand 1 and multiplier 1 after the expansion are delivered to partial-product generator 1, multiplicand 2 and multiplier 2 are delivered to partial-product generator 2, partial-product generator 1 and partial-product generator 2 respectively produce n/2+1 partial product, deliver to the partial product compression member, when the modified value production part produces the SIMD pattern under the control of code translator to the modified value of high-order product, high 2n position to product is revised, and makes that the sign bit of low level product is 0; The partial product compression member is compressed into the high-order result's of n+2 partial-product sum of two partial-product generators generations modified value the number of two 4n positions, by totalizer this two numbers addition, finally obtain the product of a 4n position, under general mode, it is exactly the product of two 2n positional operands; Under the SIMD pattern, low 2n position is the product of low n position multiplication, and high 2n position is the product of high n position multiplication.
2. a kind of mixed multiplier of supporting the single instrction multioperand as claimed in claim 1, it is characterized in that described operand widening parts expands operand 1 and operand 2, produce two multiplicands respectively and two multipliers are delivered to two partial-product generators, the length of multiplicand 1 and multiplicand 2 is the 2n+2 position, under general mode, the low 2n position of multiplicand 1 and multiplicand 2 equals operand 1, simultaneously high two sign bits that are extended to operand 1; Under the SIMD pattern, the low n position of multiplicand 1 equals the low n position of operand 1, and n to the 2n+1 position of multiplicand 1 all is extended to the sign bit of the low n position of operand 1; The low n position of multiplicand 2 is the high n position that 0, the n to the 2n-1 position equals operand 1, and the highest two is the sign bit that 2n and 2n+1 position expand to the high n position of operand 1; The length of multiplier 1 and multiplier 2 all is the n+3 position, multiplier 1 mainly comes from the low n position of operand 2, multiplier 2 mainly comes from the high n position of operand 2, the operand widening parts also will respectively be expanded 1 prefix and 2 bit sign positions in the front and back of multiplier 1 and multiplier 2, the prefix of multiplier 1 is 0, the sign bit of multiplier 2 is consistent with the sign bit of operand 2 high n positions, and the prefix of the sign bit of multiplier 1 and multiplier 2 is different configurations under different mode of operations.
3. a kind of mixed multiplier of supporting the single instrction multioperand as claimed in claim 1, when it is characterized in that adopting two Booth multiplication to produce partial product, the input of partial-product generator 1 is multiplicand 1 and multiplier 1, the input of partial-product generator 2 is multiplicand 2 and multiplier 2, partial-product generator 1 produces n/2+1 partial product of low level, partial-product generator 2 produces n/2+1 high-order partial product, and partial-product generator 2 is determined the value of its Senior Three sign bit of first partial product according to mode of operation:
3.1 when mixed multiplier is operated in general mode, the 1st to n/2 partial product of partial-product generator 1 and general multipliers the 1st identical respectively to the production method and the power of n/2 partial product; N/2+1 partial product of partial-product generator 1 is 0, and the 1st to n/2+1 partial product of partial-product generator 2 is identical respectively with the production method and the power of n/2+1 to a n+1 partial product of general multipliers; Therefore when general mode, the partial product of mixed multiplier and general multipliers is just the same, and n+2 partial product of mixed multiplier added up promptly obtains the product of a 2n * 2n multiplication, and at this moment, the prefix of the sign bit of multiplier 1 and multiplier 2 all is changed to b
N-1
3.2 when mixed multiplier was operated in the SIMD pattern, the high n position of the multiplicand 1 of partial-product generator 1 expanded to the symbol of operand 1 low n position, two sign bits of multiplier 1 expand to the sign bit of operand 2 low n positions; Produce the 1st identical during with general mode to the control code of n/2 partial product; The 1st is identical during with general mode to the power of n/2 partial product; N/2+1 partial product is by [s, s, b
N-1] control generation, wherein b
N-1Be the most significant digit of low n position multiplier, s is a sign bit, when the low level multiplier is signed number, and s=b
N-1, when the low level multiplier is unsigned number, s=0; The power of n/2+1 partial product is n; Under the SIMD pattern, the low n position of the multiplicand 2 of partial-product generator 2 is changed to 0, and high n position remains unchanged, and the prefix of multiplier 2 is 0; The control code of the 1st partial product of the generation of partial-product generator 2 is by [b
N+1, b
n, b
N-1] become [b
N+1, b
n, 0]; The remainder of partial-product generator 2 is identical when amassing with general mode; The power of partial-product generator 2 all partial products remains unchanged; Under the SIMD pattern, each partial-product generator all is equivalent to the partial-product generator of the multiplier of a 2n * n, the long-pending low portion that is positioned at the partial product of partial-product generator 1 of the live part of low n positional operand multiplication, the long-pending high-order portion that is positioned at the partial product of partial-product generator 2 of the live part of high n positional operand multiplication.
4. a kind of mixed multiplier of supporting the single instrction multioperand as claimed in claim 1, it is characterized in that when the SIMD pattern method that the result to high 2n position revises is that result to high 2n position adds a modified value, concrete grammar is to make the sign bit of low level product expand to the most significant digit of high-order product, when the sign bit of low level product is 0, the low level product can not exert an influence to high-order product, and this moment, the lowest order at high-order product added one 0; When the sign bit of low level product is 1, add one 1 at the lowest order of high-order product, just can make the symbol at high-order product place of low level product become 0; For the sign bit that makes the low level multiplication expands to the most significant digit of high-order product, add 2 in the highest n-1 position of high-order product
N-1-1, therefore, the modified value under the SIMD pattern is made up of two parts, be added in high-order product lowest order 0 or 1 and be added in 2 on the high n-1 position
N-1-1, this modified value is produced under the control of code translator by the modified value production part.
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| CN101986263B (en) * | 2010-11-25 | 2012-08-22 | 中国人民解放军国防科学技术大学 | Method and microprocessor for supporting single instruction stream and multi-instruction stream dynamic switching execution |
| CN102253822B (en) * | 2011-08-17 | 2013-07-17 | 电子科技大学 | Modular (2<n>-3) multiplier |
| CN102360281B (en) * | 2011-10-31 | 2014-04-02 | 中国人民解放军国防科学技术大学 | Multifunctional fixed-point media access control (MAC) operation device for microprocessor |
| CN102591615A (en) * | 2012-01-16 | 2012-07-18 | 中国人民解放军国防科学技术大学 | Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device |
| EP3289477B1 (en) * | 2016-01-30 | 2021-08-25 | Hewlett Packard Enterprise Development LP | Dot product engine with negation indicator |
| CN110399117B (en) * | 2019-07-31 | 2021-05-28 | 上海燧原智能科技有限公司 | Hybrid multiplication and addition processing method and device |
| CN111008003B (en) * | 2019-09-24 | 2023-10-13 | 上海寒武纪信息科技有限公司 | Data processor, method, chip and electronic equipment |
| CN113031918B (en) * | 2019-12-24 | 2024-07-30 | 上海寒武纪信息科技有限公司 | Data processor, method, device and chip |
| CN116991359B (en) * | 2023-09-26 | 2023-12-22 | 上海为旌科技有限公司 | Booth multiplier, hybrid Booth multiplier and operation method |
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| 16×16位高速低功耗并行乘法器的实现 徐峰，邵丙铣.微电子学，第33卷第1期 2003 * |
| 一种高性能、低功耗乘法器的设计 郑伟，姚庆栋，张明，刘鹏，李东晓.浙江大学学报(工学版)，第38卷第5期 2004 * |
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