CN100353487C - How to make a capacitor - Google Patents
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- CN100353487C CN100353487C CNB2004100380026A CN200410038002A CN100353487C CN 100353487 C CN100353487 C CN 100353487C CN B2004100380026 A CNB2004100380026 A CN B2004100380026A CN 200410038002 A CN200410038002 A CN 200410038002A CN 100353487 C CN100353487 C CN 100353487C
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- 239000003990 capacitor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 144
- 230000008569 process Effects 0.000 claims abstract description 77
- 230000004888 barrier function Effects 0.000 claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 111
- 239000010949 copper Substances 0.000 claims description 97
- 229910052802 copper Inorganic materials 0.000 claims description 96
- 239000004020 conductor Substances 0.000 claims description 82
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 description 32
- 238000005516 engineering process Methods 0.000 description 18
- 239000004411 aluminium Substances 0.000 description 14
- 238000003466 welding Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 238000003701 mechanical milling Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 238000003892 spreading Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a method for manufacturing a capacitor, which comprises the following steps: a barrier layer, a second dielectric layer and a conductive layer are sequentially formed on the surfaces of the first dielectric layer and a conductive object arranged in the first dielectric layer, the barrier layer is directly contacted with the conductive object, an etching process is carried out to remove part of the barrier layer, the second dielectric layer and the conductive layer so as to form a capacitor, and a contact process is carried out to connect the conductive layer of the capacitor to a first terminal by using a first contact plug.
Description
Technical field
The present invention relates to the manufacture method of a kind of electric capacity (capacitor), refer in particular to a kind of metal-insulating body-metal capacitor (metal-insulator-metalcapacitor, manufacture method MIMC) that is applied in the process for copper (Cu process).
Background technology
In recent years, IC industry is constantly flourish, from early stage with regard to hot memory chip and central processing unit chip (CPU chip), and even answer the communication chip (communication chip) that the Mobile Communications epoch are produced at present, invariably towards multifunction, low priceization and small-sized development.In other words, the dealer drops into huge manpower and material resources one after another, in the hope of haveing breakthrough in the research and development of the Integration Design of chip and material and technology, and then reaches above-mentioned target.When making various chip, the metal interconnecting that is adopted is the aluminium line in early days.Yet, along with the requirement of product specification improves constantly, the process for copper technology becomes main flow gradually, this is because the resistance of copper is low, compare with the aluminium line, can be on smaller area the bigger electric current of bearing ratio, therefore postpone, improve the metal line reliability than being easier to realize reducing RC, dwindle purposes such as wiring area, reduction power consumption.Especially after the related process of process for copper and equipment tended to maturation gradually, such trend was more obvious.
And in the middle of the employed key part and component of integrated circuit (IC) products, electric capacity is very important a kind of assembly always.When making electric capacity, the selection of its material and technology very corrupt, all will have influence at last capacitance (capacitance value), reliability, discrete feature (dispersivebehavior) and the high frequency characteristics etc. of capacitance component, and then have influence on the general performance of chip.Especially when electric capacity is applied to communication chip, the characteristic of high frequency is important especially, because communication chip in fact can be regarded as a high-frequency integration chip (radio frequency integrated chip, RF integratedchip), normally be applied to the scope of high frequency, when the quality factor (qualityfactor) of capacitance component when stablizing inadequately, must produce the energy loss (energy loss) and the noise (noise) of not expecting, the performance of chip is had a greatly reduced quality.
Please refer to Fig. 1 to Fig. 5, on chip 10, make the method schematic diagram of electric capacity 38 for prior art.As shown in Figure 1, conventional method is made electric capacity on chip 10 method is that chip 10 is provided earlier, and as previously mentioned, metal interconnecting in the chip 10 is to utilize process for copper technology made, it is different because the structure on the chip 10 is looked the difference of the chip kind after finishing, therefore, do not do special explanation in the present invention.In addition because the penetrability of copper atom is very strong, and process for copper is the high technology of a contaminative, so electric capacity normally is made on the copper conductor 12 of the superiors, and copper conductor 12 is to be made within first dielectric layer 14.In fact, the copper conductor 12 and first dielectric layer 14 are to complete simultaneously via a cmp (CMP) technology.Then, carry out first depositing operation and form a separator 16 with the surface at chip 10, separator 16 is a silicon nitride layer, and covers copper conductor 12, in order to intercept the upwards diffusion of copper atom in the copper conductor 12.Then, forming first conductive layer, 18, the first conductive layers 18 on the surface of separator 16 is tantalum nitride layer (TaN layer) or titanium nitride layer (TiN layer), and forms via a sputter (sputtering) technology.Subsequently, on first conductive layer, 18 surfaces, be coated with after one deck photoresist (photoresistance) layer (not shown), utilize first light shield (mask) and first little shadow (photolithography) technology again, define the photoresist layer of patterning, be used for being used as bottom crown (bottom electrode plate) pattern 24.
As shown in Figure 2, carry out first etch process again, utilize bottom crown pattern 24 as shielding, etching first conductive layer 18 is up to the surface of separator 16, to form the bottom crown 26 of electric capacity (not shown) downwards.As shown in Figure 3, after removing bottom crown pattern 24, carry out second depositing operation and form second dielectric layer, 28, the second dielectric layers 28 with surface and include silicon oxide layer or silicon nitride layer, and cover bottom crown 26 at chip 10.Then forming second conductive layer, 32, the second conductive layers 32 on the surface of second dielectric layer 28 is tantalum nitride layer or titanium nitride layer, and forms via another sputtering process.Then, on second conductive layer, 32 surfaces, be coated with after another photoresist layer (not shown), utilize second light shield and second lithography process again, define the photoresist layer of patterning, be used for being used as top crown (top electrode plate) pattern 34.
As shown in Figure 4, carry out second etch process subsequently, utilize top crown pattern 34 as shielding, etching second conductive layer 32 and second dielectric layer 28 are up to the surface of first conductive layer 18 downwards, forming the top crown 38 and the capacitance dielectric layer 42 of electric capacity 36, and finish the making of electric capacity 36.As shown in Figure 5, after removing top crown pattern 34, carry out the 3rd depositing operation and form the 3rd dielectric layer 44, the three dielectric layers 44 with surface and cover electric capacity 36 at chip 10.Then, carry out a contact process, among the 3rd dielectric layer 44, form first contact plunger 46 and second contact plunger 48, respectively the top crown 38 and the bottom crown 26 of electric capacity 36 are connected to the first terminal 52 and second terminal 54 to utilize first contact plunger 46 and second contact plunger 48.In fact, the first terminal 52 and second terminal 54 are different aluminium welding pads (Al bonding pad), are used for being electrically connected different voltage.
Yet, the method of above-mentioned traditional fabrication electric capacity, need the twice light shield to define upper and lower pole plate pattern, in other words, promptly need to carry out twice gold-tinted and etch process, make technology very tediously long, and thereby increase cost, sometimes even can be because of complex steps cause the decline of product fine rate, and then influence the performance of the chip after finishing.In addition, also helpful to the characteristic of electric capacity in fact when the resistance of upper and lower pole plate is hanged down with regard to the characteristic of electric capacity itself, so, only utilize tantalum nitride or titanium nitride to be used as the material of upper and lower pole plate in the prior art, be not good selection.And with regard to the metal interconnecting of copper, though the resistance of itself is enough low, because the diffusion problem of copper atom unlikely utilizes the part of its structure to be used as pole plate again.Therefore, how to develop the method that a kind of new making metal-insulating body-metal capacitor, it does not only need to carry out twice gold-tinted and etch process, can utilize copper metal layer to be used as the part of pole plate again, produce electric capacity, or keep original twice gold-tinted and etch process, but can produce and have other advantage with good characteristic, for example the electric capacity of high capacity just becomes crucial problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of electric capacity, refers in particular to a kind of manufacture method of the metal-insulating body-metal capacitor in the process for copper that is applied to address the above problem.
For reaching above-mentioned purpose, the manufacture method of the electric capacity that most preferred embodiment provided according to the present invention, it is the method for in the semiconductor substrate, making at least one electric capacity, and the surface at this semiconductor-based end includes at least one first dielectric layer and is arranged at least one conducting objects among this first dielectric layer, this method includes the following step: form a barrier layer (barrier layer), one second dielectric layer and a conductive layer in regular turn on the surface at the described semiconductor-based end, and barrier layer contacts directly with conducting objects; Carry out barrier layer, second dielectric layer and the conductive layer of an etch process, and the barrier layer of patterning, second dielectric layer and conductive layer constitute electric capacity with the removal part; And carry out a contact process and utilize one first contact plunger to be connected to a first terminal with conductive layer with above-mentioned electric capacity.
According to specific embodiments of the present invention, in the said method, described electric capacity be metal-insulating body-metal capacitor (metal-insulator-metal capacitor, MIMC); Described conducting objects is to utilize process for copper to form, and its barrier layer that is patterned covers, as the part of the bottom crown of electric capacity; And described barrier layer is to be used for preventing that the copper atom in the conducting objects from spreading, and it includes a tantalum layer (Talayer), tantalum nitride layer or titanium nitride layer; Described second dielectric layer includes one silica layer, a silicon nitride layer or a high-k (high k) material layer; Described conductive layer includes titanium nitride layer or tantalum nitride layer; Described the first terminal includes an aluminium welding pad or a copper conductor; Described contact process can be a single mosaic technology (single damascene process) or a dual-damascene technics (dual damascene process).
In the method for the invention, after carrying out etch process, can also include a depositing operation in addition and form a separator and one the 3rd dielectric layer in regular turn with surface at the described semiconductor-based end.
Simultaneously, the present invention also provides a kind of manufacture method of electric capacity, it is the method for making at least one electric capacity in the semiconductor substrate, and the surface at this semiconductor-based end includes at least one first dielectric layer and is arranged at least one conducting objects among this first dielectric layer, this method includes the following step: form a barrier layer, one second dielectric layer, one first conductive layer, one the 3rd dielectric layer and one second conductive layer in regular turn on the surface at the described semiconductor-based end, and barrier layer contacts directly with conducting objects; Carry out one first etch process to remove second conductive layer and the 3rd dielectric layer of part; Carry out one second etch process to remove first conductive layer, second dielectric layer and the barrier layer of part, so that first patterning conducting layer, the 3rd dielectric layer and second conductive layer constitute first electric capacity, and first patterning conducting layer, second dielectric layer and barrier layer constitute second electric capacity; And carry out a contact process respectively first conductive layer of first electric capacity being connected to a first terminal via one first contact plunger, and second conductive layer of first electric capacity and conducting objects are connected to one second terminal via one second contact plunger.
According to specific embodiments of the present invention, described first electric capacity and second electric capacity are metal-insulating body-metal capacitor; Described conducting objects is to utilize a process for copper to form, and the barrier layer that is patterned covers, and is the part of the bottom crown of second electric capacity; Described barrier layer is to be used for preventing that the copper atom in the conducting objects from spreading, and can include a tantalum layer, tantalum nitride layer or titanium nitride layer; Described second dielectric layer and the 3rd dielectric layer include one silica layer, a silicon nitride layer or a high dielectric constant material layer; Described first conductive layer and second conductive layer include titanium nitride layer or tantalum nitride layer; Second conductive layer of described patterning and the 3rd dielectric layer expose the first partially patterned conductive layer; The described the first terminal and second terminal include aluminium welding pad or copper conductor; Described contact process is single mosaic technology or dual-damascene technics.
In said method of the present invention, after carrying out etch process, can also comprise a depositing operation in addition and form a separator and one the 4th dielectric layer in regular turn with surface at the described semiconductor-based end.
In a word, compare with the method for traditional fabrication electric capacity, because the method for making electric capacity of the present invention is to utilize copper conductor and barrier layer to be used as the bottom crown of electric capacity, therefore, under the prerequisite that satisfies the copper conductor that exposes part, copper conductor can successfully be connected to terminal, thus, only need to use one light shield just can define the electric capacity pattern, that is to say, only need carry out once gold-tinted and etch process, just can finish the making of electric capacity.Therefore, not only process quilt shortens, and can utilize copper conductor to be used as the part of bottom crown again, produces the better electric capacity of characteristic.Simultaneously, cost thereby reduction, the acceptance rate of product thereby promoted.In addition, under the situation that keeps original twice gold-tinted and etch process, more can produce electric capacity, and make the design of electric capacity more flexible with high capacity.When application method of the present invention is made electric capacity on certain chip, can promote the performance of chip.
Description of drawings
Fig. 1 to Fig. 5 is prior art is made electric capacity on chip a method schematic diagram.
Fig. 6 to Fig. 9 is the first embodiment of the present invention is made electric capacity on chip a method schematic diagram.
Figure 10 to Figure 15 is the second embodiment of the present invention is made electric capacity on chip a method schematic diagram.
Figure 16 is the schematic equivalent circuit of electric capacity shown in Figure 13.
Figure 17 is the third embodiment of the present invention is made electric capacity on chip a method schematic diagram.
Figure 18 is the fourth embodiment of the present invention is made electric capacity on chip a method schematic diagram.
Symbol description among the figure: 10,100,200,300,400 chips
12,102,202,302,334,336,402,444,446 copper conductors
14,104,204,304,404 first dielectric layers
16,122,236,315,425 separators, 18,212,412 first conductive layers
24 bottom crown patterns, 26 bottom crowns, 28,108,208,308,408 second dielectric layers
32,216,416 second conductive layers, 34 top crown patterns
36,118,234,314,424 electric capacity, 38 top crowns, 42 capacitance dielectric layers
44,124,214,414 the 3rd dielectric layers, 46,126,242 first contact plungers
48,128,244 second contact plungers, 52 the first terminals, 54 second terminals
106,206,306,406 barrier layers, 112,312 conductive layers, 116 electric capacity patterns
132,134,246,248 aluminium welding pads, 222 first patterns, 226 second patterns
228,418 first electric capacity, 232,422 second electric capacity 238 the 4th dielectric layers
316,322,426,432 silicon oxide layers 318,324,428,434 stop layer
326,436 grooves, 328,438 contact holes, 332,442 dual-damascene structures
Embodiment
Please refer to Fig. 6 to Fig. 9, on chip 100, making the method schematic diagram of electric capacity 118 in the first embodiment of the invention.As shown in Figure 6, the present invention makes electric capacity on chip 100 method is that chip 100 is provided earlier, and already present metal interconnecting is to utilize process for copper technology made on the chip 100, it is different because the structure on the chip 100 is looked the difference of chip kind, therefore, the present invention does not do special explanation, only demonstrates at least one copper conductor 102 of the superiors in Fig. 6 to Fig. 9, and copper conductor 102 is to be made within first dielectric layer 104.In fact, the copper conductor 102 and first dielectric layer 104 are to complete simultaneously via chemical mechanical milling tech.Then, form barrier layer 106, second dielectric layer 108 and conductive layer 112 in regular turn on the surface of chip 100, and barrier layer 106 is directly to contact with copper conductor 102.
As shown in Figure 7, carry out an etch process subsequently, make barrier layer 106, second dielectric layer 108 and the conductive layer 112 of copper conductor 102, patterning constitute an electric capacity 118 to remove barrier layer 106, second dielectric layer 108 and the conductive layer 112 of part.The barrier layer 106 of patterning and copper conductor 102 constitute the bottom crown of electric capacity 118, second dielectric layer 108 of patterning is the capacitance dielectric layer of electric capacity 118, the conductive layer 112 of patterning is the top crown of electric capacity 118, and electric capacity 118 is a metal-insulating body-metal capacitor.It should be noted that barrier layer 106, second dielectric layer 108 and the conductive layer 112 of patterning expose the copper conductor 102 of part, so that when follow-up contact process, can successfully copper conductor 102 be connected to the terminal (not shown).Simultaneously, being made in the barrier layer 106 on the copper conductor 102 in the present invention, is the diffusion that is used for preventing copper atom in the copper conductor 102, is intended for the part of bottom crown again.What deserves to be mentioned is that the barrier layer 106 of patterning almost completely covers the situation of copper conductor 102 in the present embodiment, can make copper conductor 102 good with contacting of barrier layer 106, and make the pole plate area of electric capacity bigger, is one preferred embodiment.
As shown in Figure 8, after removing electric capacity pattern 116, carry out a depositing operation subsequently, form separator 122 and the 3rd dielectric layer 124 in regular turn, and separator 122 and the 3rd dielectric layer 124 cover electric capacity 118 and copper conductor 102 with surface at chip 100.Separator 122 is generally silicon nitride layer, is used for preventing that the copper atom in the copper conductor 102 from upwards spreading.
As shown in Figure 9, then carry out a contact process, among the 3rd dielectric layer 124 and separator 122, form first contact plunger 126 and second contact plunger 128, utilizing first contact plunger 126 that the conductive layer 112 of electric capacity 118 is connected to aluminium welding pad 132 respectively, and utilize second contact plunger 128 that copper conductor 102 is connected to another aluminium welding pad 134.In fact, aluminium welding pad 132,134 is used to be used as terminal, so that the voltage that transmission is applied thereto respectively when formal running is to the upper and lower pole plate of electric capacity 118.Simultaneously, because copper conductor 102 is the part of electric capacity 118 bottom crowns, also can utilize the cabling of itself directly to be electrically connected to correspondent voltage, to omit the making of second contact plunger 128 and aluminium welding pad 134.In addition, the contact process in the present embodiment can be regarded as a single mosaic technology, because its execution mode is a conventional art, so do not repeat them here.
In the first embodiment of the present invention, only use one light shield to define the electric capacity pattern, in other words, only need carry out once gold-tinted and etch process, shortened whole making flow process significantly.And in the second embodiment of the present invention, be to keep original twice gold-tinted and etch process, to produce electric capacity with high capacity.Please refer to Figure 10 to Figure 15, Figure 10 to Figure 15 is a method schematic diagram of making electric capacity 234 in the second embodiment of the invention on chip 200.As shown in figure 10, the present invention makes electric capacity on chip method is that chip 200 is provided earlier, and already present metal interconnecting is to utilize process for copper technology made on the chip 200, it is different because the structure on the chip 200 is looked the difference of chip kind, therefore, do not do special explanation at this, in Figure 10 to Figure 15, only demonstrate at least one copper conductor 202 of the superiors, and copper conductor 202 is to be made within first dielectric layer 204.In fact, the copper conductor 202 and first dielectric layer 204 are to complete simultaneously via chemical mechanical milling tech.Then, form barrier layer 206, second dielectric layer 208, first conductive layer 212, the 3rd dielectric layer 214 and second conductive layer 216 in regular turn on the surface of chip 200, and barrier layer 206 is directly to contact with copper conductor 202.
As shown in figure 11, carry out first etch process then, utilize first pattern 222 as shielding, downward etching second conductive layer 216 and the 3rd dielectric layer 214 are up to the surface of first conductive layer 212.As shown in figure 12, after removing first pattern 222, coating one deck photoresist layer (not shown) on the surface of chip 200 utilized the second light shield (not shown) and second lithography process subsequently again, define the photoresist layer of patterning, be used for being used as second pattern 226.As shown in figure 13, then carry out second etch process, utilize second pattern 226 as shielding, downward etching first conductive layer 212, second dielectric layer 208 and barrier layer 206 are up to the surface of the copper conductor 202 and first dielectric layer 204.First patterning conducting layer 212, the 3rd dielectric layer 214 and second conductive layer 216 constitute first electric capacity 228, and first patterning conducting layer 212, second dielectric layer 208 and barrier layer 206 constitute second electric capacity 232, first electric capacity 228 and second electric capacity 232 are the structure of (connected in parallel) in parallel, and produce an equivalent electric capacity (equivalentcapacitor) 234.
It should be noted that, by the first light shield (not shown) and the second light shield (not shown) are done design in advance, after second etch technology is finished, second conductive layer 216 of patterning and the 3rd dielectric layer 214 of patterning expose the first partially patterned conductive layer 212, and second conductive layer 216 of patterning, the 3rd dielectric layer 214 of patterning, first patterning conducting layer 212, second dielectric layer 208 of patterning and the barrier layer 206 of patterning expose the copper conductor 202 of part, so that can successfully the copper conductor 202 and first conductive layer 212 be connected to the terminal (not shown) during follow-up contact process.In addition, being made in the barrier layer 206 on the copper conductor 202 in the present invention, is the diffusion that is used for preventing copper atom in the copper conductor 202, is intended for the part of second electric capacity, 232 bottom crowns again.What deserves to be mentioned is that the barrier layer 206 of patterning almost completely covers the situation of copper conductor 202 in the present embodiment, can make copper conductor 202 and patterning barrier layer 206 contact well, and make the pole plate area of electric capacity bigger, be one preferred embodiment.
As shown in figure 14, after removing second pattern 226, carry out a depositing operation subsequently, form separator 236 and the 4th dielectric layer 238 in regular turn, and separator 236 and the 4th dielectric layer 238 cover first electric capacity 228, second electric capacity 232 and copper conductor 202 with surface at chip 200.Separator 2 36 is generally silicon nitride layer, is used for preventing that the copper atom in the copper conductor 202 from upwards spreading.As shown in figure 15, carry out a contact process again, among the 4th dielectric layer 238 and separator 236, form first contact plunger 242 and second contact plunger 244, utilizing first contact plunger 242 that first conductive layer 212 of first electric capacity 228 is connected to aluminium welding pad 246 respectively, and utilize second contact plunger 244 that second conductive layer 216 and the copper conductor 202 of first electric capacity 228 are connected to another aluminium welding pad 248.In fact, aluminium welding pad 246,248 is used to be used as terminal, so that voltage to the first electric capacity 228 that transmission is applied thereto respectively when formal running and the upper and lower pole plate of second electric capacity 232.In addition, the contact process in the present embodiment can be regarded as a single mosaic technology.
Please refer to Figure 16, be the schematic equivalent circuit of electric capacity shown in Figure 13 234.Shown in Figure 13,15 and 16, electric capacity 234 shown in Figure 13 is the equivalent capacity of first electric capacity 228 and 232 parallel connections of second electric capacity among Figure 13.First patterning conducting layer 212 is the top crown of first electric capacity 228 and second electric capacity 232, the 3rd dielectric layer 214 of patterning is the capacitance dielectric layer of first electric capacity 228, second dielectric layer 208 of patterning is the capacitance dielectric layer of second electric capacity 232, second conductive layer 216 of patterning is the bottom crown of first electric capacity 228, the barrier layer 206 of patterning and copper conductor 202 constitute the bottom crown of second electric capacity 232, and first electric capacity 228 and second electric capacity 232 are metal one insulant-metal capacitance.The top crown of first electric capacity 228 and second electric capacity 232 (first conductive layer 212) is to be electrically connected to aluminium welding pad 246 via first contact plunger 242, and the bottom crown of first electric capacity 228 (second conductive layer 216) is the bottom crown (barrier layer 206 and copper conductor 202 by patterning are constituted) that is electrically connected to second electric capacity 232 via second contact plunger 244, so the capacitance of electric capacity 234 (C) is the capacitance (C1) that equals first electric capacity 228 and capacitance (C2) sum (sum) of second electric capacity 232.When first electric capacity 228 in the present embodiment and second electric capacity 232 all use same material, the capacitance of electric capacity 234 can reach the twice of the capacitance of single electric capacity at most, but in fact, by adjusting first electric capacity 228 and second electric capacity, 232 employed materials, the capacitance of electric capacity 234 can be further improved.
In addition, as previously mentioned, because the penetrability of copper atom is very strong, process for copper is the high technology of contaminative, so electric capacity is made on the copper conductor of the superiors usually in the prior art.Yet, because the present invention utilizes copper conductor and barrier layer to be used as the pole plate of electric capacity, and after the electric capacity etching is finished, make a separator at once and cover electric capacity and copper conductor, to prevent that copper atom in the copper conductor is to outdiffusion, therefore, electric capacity of the present invention also can be made between the copper interconnects of each layer.Please refer to Figure 17 to Figure 18, Figure 17 is a method schematic diagram of making electric capacity 314 in the third embodiment of the invention on chip 300, and Figure 18 is a method schematic diagram of making electric capacity 424 in the fourth embodiment of the invention on chip 400.As shown in figure 17, at first provide chip 300, include at least one copper conductor 302 on the chip 300, copper conductor 302 is to be made within first dielectric layer 304, and copper conductor 302 is not the copper conductor for the superiors.Form the electric capacity 314 that is constituted by barrier layer 306, second dielectric layer 308 and conductive layer 312 on the surface of chip 300 again, and barrier layer 306 is directly to contact with copper conductor 302.After electric capacity 314 completes, make a separator 315 earlier, then make the copper interconnects of last layer again, its step is identical with general traditional prior art.At first deposit one silica layer 316, utilize chemical mechanical milling tech that it is polished again, deposition is used as silicon nitride layer or silicon oxynitride layer, another silicon oxide layer 322 that stops layer 318 and is used as silicon nitride layer or the silicon oxynitride layer that another stops layer 324 in regular turn then.Utilize two sections etch process to produce upper strata groove 326 and lower floor contact hole 328 subsequently again, and make copper fill up upper strata groove 326 and lower floor contact hole 328, carry out another chemical mechanical milling tech at last, remove groove 326 and contact hole 328 copper in addition, to finish the making of dual-damascene structure 332.In the present embodiment, the conductive layer 312 of electric capacity 314 is connected to copper conductor 334, and copper conductor 302 is connected to another copper conductor 336.
As shown in figure 18, at first provide chip 400, include at least one copper conductor 402 on the chip 400, copper conductor 402 is to be made within first dielectric layer 404, and copper conductor 402 is not the copper conductor for the superiors.Form first electric capacity 418 that is constituted by first conductive layer 412, the 3rd dielectric layer 414 and second conductive layer 416 on the surface of chip 400 again, and second electric capacity 422 that is made of first conductive layer 412, second dielectric layer 408 and barrier layer 406, and barrier layer 406 is directly to contact with copper conductor 402.First electric capacity 418 and second electric capacity 422 are structure in parallel, and produce an equivalent electric capacity 424.After electric capacity 424 completes, make a separator 425 earlier, then make the copper interconnects of last layer again, its step is identical with general traditional prior art.At first deposit one silica layer 426, utilize chemical mechanical milling tech that it is polished again, deposition is used as silicon nitride layer or silicon oxynitride layer, another silicon oxide layer 432 that stops layer 428 and is used as silicon nitride layer or the silicon oxynitride layer that another stops layer 434 in regular turn then.Utilize the etch process of segmentation to produce upper strata groove 436 and lower floor contact hole 438 subsequently again, and make copper fill up upper strata groove 436 and lower floor contact hole 438, carry out another chemical mechanical milling tech at last, remove groove 436 and contact hole 438 copper in addition, to finish the making of dual-damascene structure 442.In this embodiment, first conductive layer 412 of first electric capacity 418 second conductive layer 416 and the copper conductor 402 that are connected to copper conductor 444, the first electric capacity 418 is connected to another copper conductor 446.
In addition, all visual actual conditions in the size of the pole plate of the electric capacity among the present invention, shape and position and adjusting, expose copper conductor partly can successfully copper conductor be connected to the prerequisite of terminal as long as satisfy, certain feasibility is all arranged, and all should be covered by within the scope of the present invention.Just when reality is implemented, must consider the contact resistance of barrier layer and copper conductor, technologic dislocation (misalignment), and the problems such as performance of integral capacitor.Simultaneously, method of the present invention is applicable to the structure of any copper, and not only copper conductor can constitute the bottom crown of electric capacity with barrier layer, and copper switching pad also can constitute the bottom crown of electric capacity with barrier layer.
Because the method for making electric capacity of the present invention, be to utilize copper conductor and barrier layer to be used as the bottom crown of electric capacity, therefore, satisfy expose part copper conductor successfully copper conductor is connected under the condition of terminal, only need to use one light shield just can define the electric capacity pattern, that is to say, only need carry out once gold-tinted and etch process, just can finish the making of electric capacity.Shortened whole making flow process.Simultaneously in the second embodiment of the present invention, keep original twice gold-tinted and etch process, to produce electric capacity with high capacity.When using method of the present invention, can make electric capacity with low cost, high yield and characteristic good in the actual production line.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to content of the present invention change and modify, and all should belong to protection scope of the present invention.
Claims (27)
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100380026A CN100353487C (en) | 2004-05-12 | 2004-05-12 | How to make a capacitor |
| US10/908,298 US20050255664A1 (en) | 2004-05-12 | 2005-05-05 | Method of forming a metal-insulator-metal capacitor |
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| CNB2004100380026A CN100353487C (en) | 2004-05-12 | 2004-05-12 | How to make a capacitor |
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| CN102420209A (en) * | 2011-06-17 | 2012-04-18 | 上海华力微电子有限公司 | Structure and method for increasing density of capacitors |
| CN103489928A (en) * | 2013-09-25 | 2014-01-01 | 北京中科微电子技术有限公司 | Capacitor structure and manufacturing method thereof |
| US9954051B2 (en) * | 2015-10-12 | 2018-04-24 | Applied Materials, Inc. | Structure and method of fabricating three-dimensional (3D) metal-insulator-metal (MIM) capacitor and resistor in semi-additive plating metal wiring |
| CN107068650A (en) * | 2016-11-25 | 2017-08-18 | 深圳天德钰电子有限公司 | Capacitor, the manufacture method of capacitor and semiconductor integrated circuit |
| CN110556357B (en) * | 2018-05-30 | 2021-07-30 | 世界先进积体电路股份有限公司 | Capacitor structure and method of making the same |
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