CN100352021C - Method for producing multi-bit memory cell - Google Patents
Method for producing multi-bit memory cell Download PDFInfo
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- CN100352021C CN100352021C CNB018134459A CN01813445A CN100352021C CN 100352021 C CN100352021 C CN 100352021C CN B018134459 A CNB018134459 A CN B018134459A CN 01813445 A CN01813445 A CN 01813445A CN 100352021 C CN100352021 C CN 100352021C
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H10D30/00—Field-effect transistors [FET]
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- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
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Abstract
一种制造多位存储器单元的方法。希望用作俘获载流子的存储层(3)置于源极区(6a)和漏极区(6b)之上，并且在沟道区上隔断，以防止源极区和漏极区上俘获的载流子扩散。存储层限制在面向沟道区的源极区和漏极区部分上的区域，并且全部掩埋在氧化物中。
A method of fabricating a multi-bit memory cell. It is desired that the storage layer (3) used for trapping carriers is placed over the source region (6a) and the drain region (6b) and is isolated on the channel region to prevent trapping on the source region and the drain region carrier diffusion. The storage layer is confined to the area on the portion of the source and drain regions facing the channel region and is entirely buried in oxide.
Description
Technical field
The present invention relates to a kind of method of making multi-bit memory cell, this multi-bit memory cell has self-adjustment ONO (oxide-nitride thing-oxide) district.
Background technology
In US 5 768 192, a kind of nonvolatile storage has been described.Wherein trapped electrons is distinguished in the source electrode of accumulation layer or drain electrode, and these electronics of catching determine transistorized threshold voltage.Transistor design becomes SONOS transistor (semiconductor-oxide-nitride thing-oxide-semiconductor), and the electric charge that source electrode or drain electrode exist separately can be counted as a bank bit respectively.Thereby, in each unit of this kind structure, can store two.For programming state, produce hot carrier in the raceway groove raceway groove; In close drain region, these electronics are injected into accumulation layer by semi-conducting material.In addition, the typical electrical potential difference of a 5V makes that word is capable to pass through grid along source electrode to drain directions.Itself meets 0V source area, meets 5V as the drain region of bit line.Add reverse voltage, also can trap-charge at source area.Grid voltage between source, leakage between the threshold voltage of the threshold voltage of the electrical potential difference of 1.2V and programming state and non-programming state enough reads the potential energy that is stored in the source electrode limit.Significant negative potential of grid and drain electrode add for example the voltage of 5V (word capable almost do not have stream), and the charge carrier of capturing is got back to source area and bank bit is wiped in the drain region by ordering about, its with respect to earth electrode (GIDL, grid induce leak) for just.
Recently, in the height integrated memory, source electrode is to the spacing 150nm only of drain electrode.If storage chip places under the rugged environment (high temperature especially, be generally 85 ℃, reach as in automobile, just being easy to), the number that, fills/put the cycle (can realize undoubtedly and lastingly) if its charge carrier of capturing no longer is enough to occupy in the dielectric nitride will reduce.So, this just feasible position that is stored in source electrode and drain electrode of reading respectively is difficult more.
In US 5 877 523, a kind of multi-stage separation flash memory in grating unit has been described, wherein used and constructed oxide skin(coating) and hope as the polysilicon layer of accumulation layer, in two parts, form floating gate electrode.The remainder dielectric layer.On this conductive layer (in order to form grid).Inject formation source electrode and drain electrode by dopant material.
In US 5 969 383, a kind of separate gate flush memory device has been described.Wherein made silicon dioxide, silicon nitride and silicon dioxide layer successively under all situations on the channel region part and on the part of drain region, the sandwich construction on the raceway groove has formed a control grid electrode.The programming of memory chip realizes by catch the charge carrier this point at silicon nitride layer.Select gate electrode to be arranged on the remainder of channel region.
In US 5 796 140, a kind of method of making memory cell has been described.Wherein source electrode and drain electrode form doped region, and keep apart mutually with channel region; The accumulation layer of wishing to be used as the storage charge carrier is manufactured on these zones between the boundary layer and buries wherein; Used gate electrode, and itself and semi-conducting material have been kept apart with dielectric layer; Therefore, except the zone that is positioned at interface between channel region and source electrode (or drain electrode) district, all the other accumulation layers are all removed.
In JP 2000-58680, a kind of semiconductor storage unit has been described.Wherein, oxide-nitride-oxide layer has also been used on the limit of gate electrode.
Summary of the invention
The objective of the invention is to illustrate a kind of method of making multi-bit memory cell.Even under mal-condition, this multi-bit memory cell also can guarantee to obtain bigger filling/the put number in cycle.
A technical scheme of above-mentioned purpose is a kind of method of making memory cell, the source area of memory and drain region form doped region in semiconductor body or in semi-conducting material one deck, doped region utilizes channel region separated from one another, one accumulation layer, prepare as storing charge carrier, be arranged on these districts between the boundary layer, accumulation layer, except being positioned at interface between channel region and source area or these districts on the interface between channel region and drain region separately, all be removed so that accumulation layer appears on source area and the drain region part and is cut off on channel region, one gate electrode, with dielectric layer itself and semi-conducting material are isolated, it is characterized in that: the first step, growing by oxide skin(coating) on the semiconductor body or on the semiconductor material layer, the series of layers that accumulation layer and oxide skin(coating) are formed forms a boundary layer; In second step, accumulation layer is shifted out from the zone that will be used as memory cell; In the 3rd step, in semi-conducting material, inject dopant material as source area and drain region; The 4th step, outside the zone that accumulation layer occupies, make one deck auxiliary layer, it has a pit and has ensuing needed enough precipitous edge of the 5th step in the accumulation layer zone; In the 5th step, in the pit of auxiliary layer edge, make at interval; In the 6th step, the accumulation layer of removal compartment is made and is made up dielectric layer and gate electrode; In the 7th step, use the conductive printed circuit electricity and lead the connection gate electrode.
Another technical scheme of above-mentioned purpose is a kind of method that is used for making memory cell, in this memory cell, source electrode and drain electrode form doped region in semiconductor body or in semiconductor material layer, be separated from each other by channel region, one accumulation layer, accumulation layer as the storage charge carrier is arranged on the zone between the boundary layer, accumulation layer, except being positioned at interface between channel region and source area or these districts on the interface between channel region and drain region separately, all be removed so that accumulation layer appears on source area and the drain region part and is cut off on channel region, utilize gate electrode, with dielectric layer itself and semi-conducting material are isolated, also the free edge of accumulation layer is buried simultaneously (this material and boundary layer material are same types) in the material, it is characterized in that: the first step, growth is by oxide skin(coating) on semiconductor body or semiconductor material layer, the series of layers that accumulation layer and oxide skin(coating) are formed; Second step, on this, to make auxiliary layer, and remove and prepare to be used as the regional exceptionally last of channel region, all the other are removed, so that the remainder of auxiliary layer has next step needed enough precipitous edge; In the 3rd step, on the edge that auxiliary layer opposes mutually, make at interval; In the 4th step, in semi-conducting material, introduce dopant material to form source area and drain region with making mask at interval; In the 5th step, remove auxiliary layer; The 6th step, oxide layer) certain applications are to accumulation layer, and for accumulation layer, are in freedom owing to remove the interval; In the 7th step, remove at interval; The 8th step, make dielectric layer, it covers the edge of channel region and accumulation layer at least; The 9th step, use conductive printed circuit, this conductive printed circuit flows through channel region.
Make multi-bit memory cell according to the present invention, the accumulation layer of wishing to be used for to capture source electrode and drain electrode charge carrier is limited in source area or the drain region in abutting connection with channel region.Accumulation layer is arranged between the boundary layer, and is buried in high energy band band gap material, so that the charge carrier of capturing in the accumulation layer on source area and drain region maintains the there respectively.
Nitride is preferable accumulation layer material; Oxide mainly is suitable for clad material.Be used under the silicon material system situation at memory cell, the memory cell in this example is the silicon nitride of the about 5eV of band gap, and covering is the silicon dioxide of the about 9eV of band gap.Accumulation layer can be has the different materials littler than covering band gap, the carrier electrons that can obtain whereby restriction, and difference in band gap should be big as far as possible.Therefore, as: tantalum oxide, the silication gold closes and intrinsic (mixing) conductor silicon can be with silicon dioxide as the accumulation layer material.The relative dielectric constant of silicon nitride is approximately 7.9.The substitution material that application has high dielectric constant (as: 15...18) can reduce as the whole thickness of storing of layer stacking, and this is an advantage.
In the method, the accumulation layer that is used to capture charge carrier is cleared out of a zone on source area and the drain region covering fully, in any case, all faces toward the raceway groove channel region.Afterwards, make also to make up and wish, and the accumulation layer that will be in vacant state is all the time buried (oxide is preferable) in the clad material as oxide gate and a gate electrode or a conductive printed circuit that word is capable.Accumulation layer on the raceway groove channel region is removed, and the SONOS transistor unit of Zhi Zuoing has had the memory block that places on source electrode separated from one another and the drain electrode in this way.
In a better specific embodiment, oxide gate not only is produced on the semi-conducting material of substrate channel region, and the vertical direction on the gate electrode edge, thereby has played extra electric insulation effect between the accumulation layer that links to each other with the method.The making of the vertical oxide layer on the gate electrode edge has also changed the distribution of electric field, to such an extent as to strengthen thermionic excitation and capture it there along the accumulation layer direction.Obviously improved the operating characteristic (especially programming state) of memory cell with the method.
Description of drawings
Fig. 1 represents the cross section of intermediate products of first embodiment of method of the present invention;
Fig. 2 represents the cross section after source area and drain region formation according to Fig. 1;
Fig. 3 represents the cross section after making up auxiliary layer according to Fig. 2;
Fig. 4 represents the cross section after forming sidewall spacers according to Fig. 3;
Fig. 5 represents the cross section after making up gate electrode according to Fig. 4;
Fig. 6 represents the cross section after the depositing electrically conductive printed circuit according to Fig. 5;
Fig. 7 represents the cross section of intermediate products of another embodiment of the inventive method;
Fig. 8 represents the cross section after forming auxiliary layer and the sidewall formation at interval at auxiliary layer according to Fig. 7;
Fig. 9 represents the cross section after removing auxiliary layer and part accumulation layer according to Fig. 8;
Figure 10 represents the cross section of the product of the inventive method.
Embodiment
With reference to the suitableeest easy manufacture method, according to the present invention, provide memory cell example more detailed description below, product is shown in the sectional view of Fig. 1 to 6 and Fig. 7 to 10 respectively in the middle of it.A large amount of these type of single memory unit compositions can be created on a slice chip.
Fig. 1 to 6 shows first example according to a kind of manufacture method of the present invention.The sectional view of Fig. 1 shows: the layer structure of growing semiconductor body 1, one deck or semi-conducting material on substrate.If semi-conducting material does not have desirable background doping, by original known mode, concentration is as required injected the so-called trap (as the p trap) that dopant material is made specified conductivity.In addition, Fig. 1 has shown in order to semiconductor body 1 is called the following oxide skin(coating) 2 (end oxide) of boundary layer down.On be the accumulation layer 3 (in this example, being silicon nitride here) of wishing in order to capture charge carrier.On this another layer oxide skin(coating) 4 (top oxide) as last boundary layer.Auxiliary layer 5 is as top layer, and is thicker than preceding one deck, and also is that nitride is preferable.Utilize one deck mask (making), use camera technique, make accumulation layer 3, go up oxide skin(coating) 4 and auxiliary layer 5, so that lateral limitation is wished the zone as memory cell according to the mode shown in the figure one as photo-induced corrosion resistant material.The mask of removal that shows among Fig. 1.
Then, auxiliary layer 5 is used as mask, makes source 6a and leaks 6b by the method for injecting dopant material in semi-conducting material.For example, when using the p doped substrate of making by silicon as semiconductor body, arsenic is to be fit to dopant material as this purpose.Furtherly,, also made lateral oxidation thing layer 7, utilized easier the finishing of oxidation manufacturing of substrate silicon according to Fig. 2.In doing so, material has experienced the growth of volume, so that lateral oxidation thing layer 7 is positioned on the accumulation layer 3.
Then, if desired, another layer auxiliary layer 8 (as also oxide) is deposited on a side of ground floor auxiliary layer 5.For example, make the planar surface of this auxiliary layer 8, smooth whole surface by CMP (chemico-mechanical polishing) method.Remove first auxiliary layer 5 then, the most handy wet chemistry methods is finished, and last oxide skin(coating) is as the etching cutoff layer.By this method, the intermediate products that obtain in Fig. 3, showing.
Then, make isolation shown in Figure 49 in original known mode.For this purpose, be preferably on the whole surface and back side deposit one layer thickness of ensuing anisotropic etching material (hope is used as the material of isolation) extremely uniformly, isolate 9 and remain on the inward flange of auxiliary layer 8 so that can demonstrate.Because isolate 9 parts that can be used to do the gate electrode that to do the back, advise that deposit herein is as being used for these doped polycrystalline silicon materials at interval.Then, carve last oxide layer 4, accumulation layer 3 and the following oxide layer 2 of removing zone between the isolation with isolating, and the each several part below staying at interval.Accumulation layer just has been limited in the zone (facing to grid) of source and drain edge like this.
Fig. 5 is presented on the semi-conducting material of substrate and isolates and make dielectric layer 10 on the side direction inner edge that forms.Surface oxidation by semi-conducting material is very easy to realize, especially when using silicon.Then, make and finish gate electrode by the method for deposition materials in the groove between isolating for this purpose.Preferably doped polycrystalline silicon herein can be used for this purpose.Show according to Fig. 5, for flat surface carries out CMP again one time.
Fig. 6 has shown the sectional view of deposit conductive printed circuit background storage location mode, and conductive printed circuit gate electrode (providing a word capable for memory cell configurations as it) is provided connects power supply 12.This conductive printed circuit is preferably also used doped polycrystalline silicon.By along the method that limits structure shown in Figure 6 perpendicular to the in-plane of figure, finish the structure of unit.This will realize by further photoetching process, and the material that etches away the gate electrode limit is until last oxide layer 4 times.Next, the most handy wet chemical etch method is carved and is removed accumulation layer 3.Oxidation again is to bury the free edge that accumulation layer 3 exists with oxide.Thereby as the result according to the inventive method, the edge is perpendicular to the both direction of the plan of Fig. 6, and the also oxidized layer of accumulation layer 3 fetters.Therefore, bury into oxide on all limits of accumulation layer, for good and all prevents to be trapped in the two-part carrier flow of accumulation layer together.So,, had than the former longer life-span of this type of memory cell with the small-sized multi-bit memory cell that this method is made.
Fig. 7 to 10 has shown another kind of method, and it provides a kind of memory cell that improves structure according to the present invention a little.This method still starts from growing semiconductor body 1 (Fig. 7), one deck and semiconductor material layer structures on the substrate.As needs, for semi-conducting material has this desirable doping, press method growing p-type trap or n type trap that desired concn injects by dopant material, on this whole surface be as under boundary layer following oxide skin(coating) 2 (end oxide skin(coating)), in order to the accumulation layer 3 of capturing charge carrier with as the oxide skin(coating) of one deck again (going up oxide skin(coating)) of last boundary layer.
According to the shown external form of top reserve part that constitutes the channel region 6 of wishing manufacturing, make an auxiliary layer 80 (as can be polysilicon).Utilize this auxiliary layer 80, in order to make LDD district 61 (lightly doped drains) facing to the source area of channel region and these edges of drain region, the injection of at first finishing dopant material is preferable.Use the method, make doped region opposite with the background doping type designations, bad conductivity.Be used for finishing injection under the n type doped P-type trap situation like this.With certain original known mode, for background doping (as P) conduction type, auxiliary what is called bag injects 62 to be finished better.But, have higher doping content for obtaining source area and the precipitous restriction in drain region.If auxiliary layer is used as the mask of these injections, the size that indicates according to point shown in Figure 7 anisotropic etching more thereafter.Because when etching, the thickness of layer will have some losses, in order to obtain rest layers thickness accurately, must fall into a trap at original layers thickness and count suitable retention.If do not need LDD and bag to inject, be in strict accordance with the big or small manufacturing of institute's overall dimensions that an indicate auxiliary layer.
Shown in Figure 8, in the mutual opposite edges manufacturing of auxiliary layer 80 at interval 90, auxiliary layer is positioned at the source that will make and restriction place in drain region.Make these at interval with original certain known mode, at first be intended as one deck of anisotropically using relevant material (as nitride) on the whole zone of a layer thickness of interval width, and then anisotropically this layer of etching disappears and the vertical component of retaining layer only until the horizontal component of layer, is original layers thickness substantially.Utilize these intervals 90 then, implement the actual injection of the dopant material 6b in source region 6a and drain region.The conductivity of these doping characterizes and characterizes opposite with the conductivity of background doping (as n+).
Remove auxiliary layer 80, only keep interval 90.Make mask with distance element,, make structure shown in Figure 9 by removing last oxide layer 4 and the accumulation layer 3 outside the wall overlay area.Like this, accumulation layer is arrived in the certain applications of oxide layer 4, and for accumulation layer, is in freedom at interval owing to removing.It is after 90s to remove wall, only retains the accumulation layer remainder that oxide covers on the surface of oxide skin(coating) 2.These parts lay respectively at the interface between channel region, source region and the drain region, promptly because the result of manufacture method, source region or drain region respectively in each case with an overlapping of channel region.
Make oxide skin(coating) 13, be formed on the channel region at least and accumulation layer 3 on, to such an extent as to the complete oxide of accumulation layer surrounds.The method that can partly reoxidize with nitride (especially when making semi-conducting material with silicon: 2 Si3N4+12 H2O produce 6 SiO2) is made oxide skin(coating) 13.The part oxide deposition process (oxide CVD, chemical vapor deposition, the thermal oxidation of TEOS when particularly using silicon as semi-conducting material, tetraethoxysilane, Si (OC2H5) 4+12 O2 produces SiO2).Auxiliary thermal oxidation with silicon has advantage, promptly improves the oxidation of silicon on to the source of channel region and drain region part, to form thick oxide layers 70.Figure 10 has shown and has used as word capable conducting channel 12 and the making of gate electrode separately.This conductive printed circuit constitutes from the source through channel region to the band shape of leaking with electric current, to such an extent as to conductive printed circuit is limited in the side of marginal surface and can imagines front and back at plan.The accumulation layer that part exposes is the result who removes.Preferably the exposure that this result is caused is buried subsequently into oxide, is preferably in when reoxidizing and finishes.
Claims (6)
1. method of making memory cell, the source area of memory (6a) and drain region (6b) in semiconductor body (1) or in semi-conducting material one deck, form doped region, doped region utilizes channel region (6) separated from one another,
One accumulation layer (3) is prepared as storing charge carrier, is arranged on these districts between the boundary layer,
Accumulation layer (3) except being positioned at interface between channel region and source area or these districts on the interface between channel region and drain region separately, all is removed so that accumulation layer appears on source area and the drain region part and on channel region (6) to be cut off,
One gate electrode (11) is isolated itself and semi-conducting material with dielectric layer (10),
It is characterized in that: the first step, semiconductor body (1) go up or semiconductor material layer on growth by oxide skin(coating) (2), accumulation layer (3) with form the series of layers that the oxide skin(coating) (4) of a boundary layer is formed;
In second step, accumulation layer is shifted out from the zone that will be used as memory cell;
In the 3rd step, in semi-conducting material, inject dopant material as source area (6a) and drain region (6b);
The 4th step, outside the zone that accumulation layer occupies, make one deck auxiliary layer (8), it has a pit and has ensuing needed enough precipitous edge of the 5th step in the accumulation layer zone;
In the 5th step, in the pit of auxiliary layer edge, make (9) at interval;
In the 6th step, the accumulation layer of removal compartment is made and is made up dielectric layer (10) and gate electrode (11);
In the 7th step, use conductive printed circuit (12) electricity and lead the connection gate electrode.
2. according to method described in the claim 1, in its 6th step, dielectric layer (10) is manufactured on semiconductor body (1) or the semiconductor material layer and on the limit of (9) at interval.
3. according to method described in claim 1 or 2, between its 6th and the 7th step, the free edge of accumulation layer (3) is buried in the oxide.
4. method that is used for making memory cell, in this memory cell, source electrode (6a) and drain electrode (6b) are in semiconductor body (1) or form doped region in semiconductor material layer, be separated from each other by channel region (6),
One accumulation layer (3) is prepared to be arranged on the zone between the boundary layer as the storage charge carrier,
Accumulation layer (3) except being positioned at interface between channel region and source area or these districts on the interface between channel region and drain region separately, all is removed so that accumulation layer appears on source area and the drain region part and on channel region (6) to be cut off,
Utilize gate electrode (11), itself and semi-conducting material isolated with dielectric layer,
It is characterized in that: the first step, semiconductor body (1) go up or semiconductor material layer on growth by oxide skin(coating) (2), accumulation layer (3) with form the series of layers that the oxide skin(coating) (4) of a boundary layer is formed;
Second step, on this, to make auxiliary layer (80), and remove and prepare to be used as the regional exceptionally last of channel region, all the other are removed, so that the remainder of auxiliary layer has next step needed enough precipitous edge;
In the 3rd step, on the edge that auxiliary layer opposes mutually, make (90) at interval;
In the 4th step, in semi-conducting material, introduce dopant material to form source area (6a) and drain region (6b) with making mask at interval;
In the 5th step, remove auxiliary layer;
In the 6th step, accumulation layer is arrived in the certain applications of oxide layer (4), and for accumulation layer, is in freedom at interval owing to removing;
In the 7th step, remove at interval;
The 8th step, make dielectric layer, it covers the edge of channel region and accumulation layer at least;
The 9th step, use conductive printed circuit (12), this conductive printed circuit passes channel region.
5. according to method described in the claim 4, wherein,, inject dopant material to form LDD district (61) at source area (6a) and drain region (6b) and to use and wrap injection, subsequently anisotropy etching auxiliary layer again with the remainder of auxiliary layer (80) in second step.
6. according to method described in claim 4 or 5, in its 9th step, make conductive printed circuit so that flow through source area (6a), channel region (6) and drain region (6b) with band shape, and the part of in manufacture process, removing the accumulation layer that is present in the conductive printed circuit limit; In the tenth step, the free edge of burying accumulation layer is in oxide.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10036911A DE10036911C2 (en) | 2000-07-28 | 2000-07-28 | Method for producing a multi-bit memory cell |
| DE10036911.1 | 2000-07-28 |
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| CN1444774A CN1444774A (en) | 2003-09-24 |
| CN100352021C true CN100352021C (en) | 2007-11-28 |
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| US (2) | US6673677B2 (en) |
| EP (1) | EP1305825A2 (en) |
| JP (1) | JP4116428B2 (en) |
| KR (1) | KR100474176B1 (en) |
| CN (1) | CN100352021C (en) |
| DE (1) | DE10036911C2 (en) |
| TW (1) | TW499738B (en) |
| WO (1) | WO2002011145A2 (en) |
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- 2001-07-25 KR KR10-2003-7000706A patent/KR100474176B1/en not_active Expired - Fee Related
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- 2001-07-25 WO PCT/DE2001/002811 patent/WO2002011145A2/en active IP Right Grant
- 2001-07-25 EP EP01964854A patent/EP1305825A2/en not_active Withdrawn
- 2001-07-25 JP JP2002516782A patent/JP4116428B2/en not_active Expired - Fee Related
- 2001-07-27 TW TW090118284A patent/TW499738B/en not_active IP Right Cessation
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Also Published As
| Publication number | Publication date |
|---|---|
| US20040097037A1 (en) | 2004-05-20 |
| US20030134475A1 (en) | 2003-07-17 |
| US6673677B2 (en) | 2004-01-06 |
| JP4116428B2 (en) | 2008-07-09 |
| KR20030019585A (en) | 2003-03-06 |
| WO2002011145A3 (en) | 2002-04-25 |
| DE10036911A1 (en) | 2002-02-14 |
| KR100474176B1 (en) | 2005-03-14 |
| DE10036911C2 (en) | 2002-06-06 |
| WO2002011145A2 (en) | 2002-02-07 |
| US6960505B2 (en) | 2005-11-01 |
| TW499738B (en) | 2002-08-21 |
| JP2004505460A (en) | 2004-02-19 |
| EP1305825A2 (en) | 2003-05-02 |
| CN1444774A (en) | 2003-09-24 |
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