CN100351816C - Data transmission controller, electronic device and data transmission method - Google Patents

Abstract

In the case of allocating CBW and data as information transmitted through one endpoint EP1, a buffer prepared with CBW area 12 (command storage area which can be accessed randomly) and EP1 area 10 (data storage area for FIFO setting) is provided. Then, when switching from the USB command stage (command transfer) to the data stage (data transfer), the information reading area is switched from the CBW area 12 to the EP1 area 10, and the OUT data transferred from the host to the endpoint EP1 Write to the EP1 area. Switching from the CBW area 12 to the EP1 area 10 is conditional on an acknowledgment in the command phase being returned to the host. In case of a trigger error, even if ACK is returned, zone switching is not performed.

Description

Data transmission control device, electronic device and data transmission control method

technical field

The present invention relates to a data transmission control device, an electronic device and a data transmission control method.

Background technique

In recent years, USB (Universal Serial Bus; Universal Serial Bus) has attracted attention as a standard for connecting personal computers and peripheral devices (electronic devices in a broad sense). In this USB, peripheral devices such as a mouse, a keyboard, and a printer conventionally connected with connectors of each standard can be connected simultaneously with the same standard connector, and there is an advantage that so-called plug-and-play or hot swap can be realized.

On the other hand, in this USB, as the standard of the same serial bus stage, there is a problem that the transmission speed is slower than that of IEEE1394, which is attracting attention.

Therefore, it is very attractive to formulate a USB2.0 standard that has interchangeability with respect to the existing USB1.1 standard, and can realize a very high-speed 480Mbps (HS mode) data transfer rate compared with USB1.1. Attention.

Furthermore, in this USB2.0, data transfer is performed at 480 Mbps in HS (High Speed) mode. Therefore, there is an advantage that it can be used as a stage of a storage device such as a hard disk drive or an optical disk that requires a high transfer speed.

However, on the other hand, a data transfer control device connected to a USB bus must handle data transferred at a high speed of 480 Mbps. Therefore, if the processing speed of the data transfer control device and the processing speed of the firmware (CPU) controlling the data transfer control device are slow, an effective transfer speed cannot be ensured, and there is a problem that the bus bandwidth is lost.

Contents of the invention

The present invention was made in view of the above technical problems, and an object of the present invention is to provide a data transfer control device, an electronic device, and a data transfer control method capable of increasing an effective bus transfer rate.

In order to solve the above-mentioned problems, the present invention is a data transmission control device for data transmission through a bus, which includes: a buffer for distributing various information including the first and second information as a data transmission through an end point (end point) In the case of transmitted information, prepare the first storage area for the first information and the second storage area for the second information to correspond to one endpoint; and the buffer management circuit, in the first stage of transmitting the first information through the bus In the first storage area, the information transmitted from the host to the endpoint is written into the first storage area for the first information, and in the second stage of transmitting the second information through the bus, the information transmitted from the host to the endpoint is written into the the second storage area for the second information;

The first storage area prepared for the first information is set in an area where information can be randomly accessed; the second storage area prepared for the second information is set in the previously input The area where information is output first.

According to the present invention, the first storage area for the first information allocated to the given endpoint and the second storage area for the second information allocated to the same endpoint are prepared in the buffer. Then, in the first phase (first transfer), the information transmitted from the host to the endpoint is written into the first storage area, and in the second phase (second transfer), the information transmitted from the host to the endpoint is written to the second storage area. For example, when switching from the first stage to the second stage, the information writing area to the endpoint is switched from the first storage area to the second storage area.

In this way, even when multiple types of information are allocated to one endpoint, the information written in the first storage area can be processed while the second information can be written in the second storage area. Therefore, the processing speed of the data transfer control device can be increased, the load on the parts processing the first information can be reduced, and the effective bus transfer speed can be increased.

In this way, the processing speed of the means for processing the first information written in the first storage area can be improved.

In addition, in the present invention, at least one of the command block instructing the transfer of the second information and the length information of the second information instructed to be transferred by the command block is written in an area other than the head address of the first storage area storing the first information. a message.

Even in such a case, according to the present invention, the command block and the length information can be read by random access, and the processing speed of the means for processing the first information can be improved.

In addition, the present invention is a data transmission control device for data transmission through a bus, which includes: a buffer for distributing various information including the first and second information as information transmitted through one endpoint (end point) In the case of , prepare the first storage area for the first information and the second storage area for the second information to correspond to one endpoint; and the buffer management circuit, in the first stage of transmitting the first information through the bus, will The information transmitted from the host to the endpoint is written in the first storage area for the first information, and in the second stage of transmitting the second information through the bus, the information transmitted from the host to the endpoint is written in the second information. said second storage area used;

The writing area of the information transferred from the host to the endpoint may be switched from the first storage area to the second storage area on condition that the acknowledgment of the data transfer in the first stage is returned to the host.

In this way, error-free and reliable zone switching can be achieved with a small processing load.

Furthermore, in the present invention, when an error occurs in the data trigger bit for sequence synchronization of transactions between the hosts, even when an acknowledgment is returned to the host, no transfer from the first storage area to the host is performed. Switching of the second storage area.

In this way, even when an error occurs in the data trigger bit (trigger error), appropriate data transfer processing can be realized.

In addition, the present invention is a data transmission control device for data transmission through a bus, which includes: a buffer for distributing various information including the first and second information as information transmitted through one endpoint (end point) In the case of , prepare the first storage area for the first information and the second storage area for the second information to correspond to one endpoint; and the buffer management circuit, in the first stage of transmitting the first information through the bus, will The information transmitted from the host to the endpoint is written in the first storage area for the first information, and in the second stage of transmitting the second information through the bus, the information transmitted from the host to the endpoint is written in the second information. said second storage area used;

The first information is a packet of a command block; the second information is a packet of data transferred according to an instruction of the command block.

However, in the present invention, the types of the first and second information stored in the first and second storage areas can be set arbitrarily.

Furthermore, the present invention may write packets of data into the second storage area while the processing unit interprets the packets of the command block.

In this way, when switching from the common phase (command transmission) to the data phase (data transmission), etc., the start timing of the data transmission process through the second storage area can be accelerated, and the effective transmission speed of the bus can be improved. .

In addition, the present invention is a data transfer control device for data transfer through a bus, which includes: a buffer corresponding to preparing a command storage area for a command block and a data storage area for data at one endpoint; and a buffer management circuit switching from a command stage of transmitting a packet of the command block to data of a packet of data via the bus In the case of the phase, the information writing area is switched from the command storage area for command blocks to the data storage area for data, and the data packets transmitted from the host to the endpoint are written in the data storage area.

According to the present invention, a command storage area for command block packets allocated to a given endpoint and a data storage area for data blocks allocated to the same endpoint are prepared in the buffer. Then, when switching from the command phase (command transmission) to the data phase (data transmission), the writing area of the information to the endpoint is switched from the command storage area to the data storage area.

In this way, even when a command block packet and a data packet are allocated to one endpoint, the command block packet written in the command storage area can be processed, and the data packet can be written in the data storage area at the same time. . Therefore, the processing speed of the data transfer control device can be increased, the load on the components processing command block packets can be reduced, and the effective bus transfer speed can be increased.

In addition, the present invention can perform data transfer handled in accordance with the USB (Universal Serial Bus) standard.

However, the present invention can be applied to data transfers handled by standards other than USB (standards that inherit the idea of USB).

In addition, the electronic device of the present invention may also include any one of the data transfer control devices described above, and a device that performs output processing, fetch processing, or storage processing of data transferred via the data transfer control device and the bus.

According to the present invention, it is possible to reduce the processing load on the processing means (firmware, etc.) for controlling data transfer of the data transfer control device, and realize cost reduction and downsizing of the electronic device. In addition, according to the present invention, data transfer can be performed in a high-speed transfer mode, so that the processing speed of the electronic device can be realized.

Description of drawings

1A, 1B, 1C, and 1D are diagrams illustrating USB endpoints and transaction structures.

2A and 2B are diagrams illustrating the CBI standard and the Bulk-Only standard.

Fig. 3 is a diagram showing the CBW format.

Fig. 4 is a diagram showing the CSW format.

5A and 5B are diagrams illustrating write processing and read processing of data in Bulk-Only.

6A, 6B, 6C, and 6D are diagrams illustrating the method of the comparative example.

7A, 7B, and 7C are diagrams illustrating the method of this embodiment.

8A and 8B are diagrams illustrating the advantages of the method of setting the CBW area to be randomly accessible.

FIG. 9 is a diagram showing a configuration example of the data transfer control device of this embodiment.

FIG. 10 is a diagram showing an example of a detailed configuration of a transaction management circuit, an endpoint management circuit, a buffer management circuit, and a buffer.

11 is a diagram showing another example of the detailed configuration of the transaction management circuit, the endpoint management circuit, the buffer management circuit, and the buffer.

FIG. 12 is a timing waveform diagram illustrating the operation of the present embodiment at the beginning of the command phase.

FIG. 13 is a timing waveform diagram illustrating the operation of the present embodiment in the case of successful data transfer.

Fig. 14 is a timing waveform diagram illustrating the operation of the present embodiment in the case of a data length error.

Fig. 15 is a timing waveform diagram illustrating the operation of the present embodiment in the case of a CRC error.

Fig. 16 is a timing waveform diagram illustrating the operation of the present embodiment in the case of a trigger error.

17A and 17B are diagrams illustrating trigger bits and trigger errors.

18A and 18B are timing waveform diagrams of the comparative example and the present embodiment.

19A and 19B are flowcharts showing the processing of the firmware in the comparative example and the present embodiment.

20A, 20B, and 20C are examples of internal block diagrams of various electronic devices.

21A, 21B, and 21C are external views of various electronic devices.

Detailed ways

Hereinafter, this embodiment will be described in detail using the drawings.

The present embodiment described below does not limit the content of the present invention described in the claims. In addition, the entire structure described in this embodiment does not necessarily have to be a solution of the present invention.

1.USB

1.1 Data transfer method

First, the data transfer method of USB (USB2.0) will be briefly described.

In USB, unlike IEEE1394 and the like, the host has the initiative to transfer data. That is, the transaction to start data transfer is on the host side, and the host performs most of the control related to data transfer. Therefore, the processing load of the host is heavy, but since a PC (personal computer) or the like as the host has a high-speed, high-performance CPU (processor), there is no problem in processing such a heavy load.

On the other hand, in USB, the device (target) only needs to simply respond to the request from the host, so the processing and configuration on the device side can be simplified. Therefore, it is not necessary to use a high-performance and high-speed CPU like a host on the device side, and an inexpensive CPU (microcomputer) can be used, thereby achieving cost reduction.

In addition, in USB, in order to realize such host-driven data transfer, as shown in FIG. 1A , endpoints (EP0 to 15) are prepared on the device side. Here, the endpoint corresponds to the entry of a buffer (FIFO) for data transfer between the host and the device, and all data transfers in the USB are performed through the endpoint.

Furthermore, the endpoint is uniquely addressed by the device address and endpoint number. That is, the host can freely perform transmission of data to and reception of data from a desired endpoint by designating a device address and an endpoint number.

It is optional whether or not to set endpoints on the device side, and the host can know the allocation of endpoint numbers, the data volume of storage areas allocated to each endpoint, and the like during enumeration processing.

In USB, as types of data transfer, control transfer, isochronous transfer, interrupt transfer, and bulk transfer are prepared.

Here, the control transfer is a transfer mode for control between a host and a device (target) via a control endpoint. Through this control transmission, configuration information and the like for initialization of the device can be transmitted.

The isochronous transfer is a transfer mode prepared for data transfer that prioritizes securing a bandwidth over the availability of data such as image data and voice data. In this synchronous transmission, since it is guaranteed that a certain amount of data can be transmitted within a certain period, the real-time nature of data becomes an effective transmission mode in important applications.

Interrupt transfer is a transfer mode prepared for transferring a small amount of data at a relatively low transfer rate.

The bulk transfer is a transfer mode prepared for transferring a large amount of data generated irregularly. In this bulk transfer, data is transferred during idle time other than the time used by isochronous transfer and interrupt transfer while checking the validity of the data. Therefore, real-time performance is not so important, but it is an effective transmission mode for data transmission in which reliability of data must be ensured.

1.2 Transaction Processing Composition

As shown in FIG. 1B , a transaction in USB bulk transfer basically consists of three packets: a marker packet, a data packet, and a handshake packet. Also, in the case of isochronous transfer, no handshaking packets are required.

Here, the marker packet is a packet used when, for example, a host requests reading or writing of an endpoint of a device (target). The tag information packet has fields such as PID (packet ID of OUT, IN, SOF, SETUP, etc.), ADDR (device address), ENDP (endpoint number), and CRC (Cyclic Redundancy Check; Cyclic Redundancy Check).

The data packet is a packet for transmitting the entity of data, and has fields of PID (DATA0, DATA1), DATA (data entity), and CRC.

The handshake information packet is an information packet for the receiving end to transmit to the sending end whether the data reception is successful, and has a field of PID (ACK, NAK, STALL).

In an OUT transaction (a transaction in which the host outputs information to the device), as shown in FIG. 1C , first, the host transmits an OUT flag packet to the device. Next, the host sends the OUT data packet to the device. Then, if the data packet of OUT is successfully received, the device transmits a handshake packet of ACK to the host.

On the other hand, in an IN transaction (a transaction in which the host inputs information from the device), as shown in FIG. 1D , first, the host transmits an IN flag packet to the device. Then, the device that has received the IN tag packet transmits the IN data packet to the host. Then, if the data packet of IN is successfully received, the host transmits a handshake packet of ACK to the device.

In FIG. 1C and FIG. 1D , "D←H" means that information is transmitted from the host to the device, and "D→H" means that information is transmitted from the device to the host (the same applies to the following description and drawings).

1.3 Bulk-Only

USB devices are classified into various classes. Furthermore, devices such as hard disk drives and optical disk drives belong to a class called mass storage, and in this mass storage, there are standards such as CBI (Control/Bulk/Interrupt) and Bulk-Only established by manufacturers of electronic devices.

Furthermore, in the CBI standard, as shown in FIG. 2A, the device is prepared with endpoints EP0, 1, 2, and 3 for control, bulk output, bulk input, and interrupt. Here, control packets and command packets of the USB layer are transmitted in the endpoint EP0. OUT data (data transmitted from the host to the device) is transmitted in EP1, IN data (data transmitted from the device to the host) is transmitted in EP2, and an interrupt IN packet is transmitted in EP3. It should be noted that it is arbitrary on the device side whether to allocate any one of EP1 to 15 to the endpoints of bulk output, bulk input, and interrupt IN.

On the other hand, in the Bulk-Only standard, as shown in FIG. 2B , devices are prepared with endpoints EP0, 1, and 2 for control, bulk output, and bulk input. Here, a control packet of the USB layer is transmitted in the endpoint EP0. The command (CBW) and OUT data are transmitted in EP1, and the status (CSW) and IN data packets are transmitted in EP2. It should be noted that it is optional on the device side whether to set any one of EP1 to 15 as an endpoint of batch output or batch input.

Here, CBW (Command Block Wrapper) is an information package that includes a command block and its related information, and its format is shown in FIG. 3 . CSW (Command Status Wrapper) is an information packet containing the status of the command block, and its format is shown in Figure 4.

In Figure 3, dCBWSignature is the information to identify the information packet as CBW, dCBWTag is the identifier of the command block, and dCBWData Transfer Length is specified as the length of the data transferred in the data phase. In addition, bmCBWFlags is a flag for designating a transfer direction, dCBWLUN is a local unit number, bCBWCBLength is a command length, and CBWCB is a command block in which commands such as ATA/ATAPI or SCSI are boxed and described.

In FIG. 4, dCSWSignature is information for identifying the packet as CSW. dCSWTag is an identifier of the status block, and the value of dCBWTag of the CBW corresponding to the CSW is written. CSWDataResidue is the difference between the length of data specified by dCBWDataTransferLength of CBW and the length of data actually processed by the device, and bCSWStatus is a status block.

Next, data write processing and read processing in the Bulk-Only standard shown in FIG. 2B will be described with reference to FIGS. 5A and 5B.

When the host writes data to the device, as shown in FIG. 5A , first, the host performs a command phase (command transmission) of transferring the CBW to the device. Specifically, the host transmits a marker packet specifying the endpoint EP1 to the device, and then transmits the CBW (see A1 in FIG. 2B , FIG. 3 ) to the endpoint EP1 of the device. Write commands are included in this CBW. Then, if the slave returns a handshake (H.S) of ACK to the master, the command phase ends.

When the command phase (command transfer) is completed, it moves to the data phase (data transfer). In this data phase, first, the host transmits a marker packet specifying the endpoint EP1 to the device, and then transmits OUT data (refer to A2 in FIG. 2B ) to the endpoint EP1 of the device. Then, if the slave returns a handshake of ACK to the master, a transaction ends. Then, such transaction processing is repeated, and when the data of the data length amount specified by dCBWDataTransferLength (refer to FIG. 3 ) of the CBW is transferred, the data phase ends.

If the data phase (data transfer) is over, move to the status phase (status transfer). In this status phase, first, the host transmits a marker packet specifying the endpoint EP2 to the device. Then, the device transmits the CSW (refer to A3 of FIG. 2B , FIG. 4 ) at the endpoint EP2 to the host. Subsequently, if a handshake of ACK is returned from the host to the device, the status phase ends.

When the host reads data, as shown in FIG. 5B , first, the host transmits a marker packet specifying the endpoint EP1 to the device, and then transmits the CBW to the endpoint EP1 of the device. The CBW contains read commands. Then, if the slave returns a handshake of ACK to the master, the command phase ends.

Move to the data phase after the command phase ends. In this data phase, first, the host transmits a marker packet specifying the endpoint EP2 to the device. Then, the device transmits the IN data (refer to A4 in FIG. 2B ) at the endpoint EP2 to the host, and when the handshake of ACK is returned from the host to the device, one transaction is ended. Then, such a transaction process is repeated, and if the data of the data length amount specified by dCBWDataTransferLength of the CBW is transferred, the data phase ends.

If the data phase ends move to the status phase. The processing in this status stage is the same as in the case of the data writing processing in FIG. 5A.

2. Features of this embodiment

2.1 Region switching

In the CBI standard shown in FIG. 2A , there is a standard that the host transfers a flag to the device at regular intervals. Therefore, there is a disadvantage of increasing the processing load of the host and the processing load of the device receiving the mark.

Therefore, currently, the Bulk-Only standard shown in Figure 2B is becoming mainstream.

However, in this Bulk-Only standard, various types of information are allocated as information transmitted through one endpoint. Specifically, in FIG. 2B, as information transmitted through the bulk-output endpoint EP1, command (CBW) and OUT data are allocated, and as information transmitted through the bulk-in endpoint EP2, status (CSW0 and IN data are allocated. Therefore, the host and the device need to distinguish which information is transmitted through each endpoint. In the Bulk-Only standard, the host and the device judge which stage is the current stage and perform the judgment of the information.

For example, in B1 and B2 of FIG. 5A and FIG. 5B , the current stage is the command stage, so the information transmitted through the endpoint EP1 is judged as CBW (command). In addition, in B3 and B4, since the current phase is the data phase, the information transmitted through the endpoint EP1 is judged to be OUT data, and the information transmitted through the endpoint EP2 is judged to be IN data. In addition, in B5 and B6, since the current phase is the status phase, the information transmitted through the endpoint EP2 is judged as CSW (status).

Furthermore, in the Bulk-Only standard, since the data transfer is performed between the host and the device so that the stages are always consistent, even when multiple information (CBW and OUT data, CSW and IN data) are allocated to one endpoint , and appropriate data transfers can also be performed.

However, in the Bulk-Only standard, it was found that there were the following problems.

For example, the method of the comparative example of this embodiment is shown in FIG. 6A - FIG. 6D. In this comparative example, as shown in FIG. 6A, in the command phase, a CBW (command) from the host is written to the FIFO (EP1) 600 having the endpoint EP1 as an entry.

Then, as shown in FIG. 6B , the CPU (firmware, processing unit) on the device side reads the CBW written into the FIFO 600 in a first-in-first-out manner, and interprets commands. In this case, the data from the host cannot be written to the FIFO 600 until the CPU's command interpretation is completed.

Therefore, as shown in FIG. 6C , moving to the data phase, the device returns NAK to the host even when a flag of OUT data is transmitted from the host.

Then, as shown in FIG. 6D , the OUT data from the host computer is written into the FIFO 600 on the condition that the command interpretation by the CPU ends and the FIFO 600 becomes empty. .

Therefore, in the comparative example of FIGS. 6A to 6D , OUT data is not written into the FIFO 600 while the CPU is interpreting the command. Therefore, the processing on the device side is slow during this period, which reduces the effective data transfer rate.

In this case, since the transfer speed of the bus is low in USB1.1, the processing delay on the device side shown in FIGS. 6B and 6C is hardly a problem.

However, in the HS mode of USB2.0, data transfer is performed at high-speed 480Mbps. Therefore, data is transferred at high speed from the host through the USB. Therefore, if the processing on the device side is slow and the device cannot cope with the processing of such high-speed data transfer, the effective data transfer rate of the entire system will drop significantly.

Especially on the device side, from the viewpoint of cost reduction, an inexpensive CPU that operates at a clock frequency of, for example, about 20 to 50 MHz is often used. Therefore, it takes a lot of time to interpret the commands in FIG. 6B and FIG. 6C , and the slowdown of the effective data transfer rate becomes a more serious problem.

Therefore, in this embodiment, in order to solve such a problem, a method of switching the storage area of the buffer according to the switching of the stage (transfer) is adopted.

More specifically, in the present embodiment shown in FIG. 7A, in addition to the EP1 area 10 (the second storage area, data storage area) for writing the OUT data (the second information), the A CBW area 12 (first storage area, command storage area) for writing CBW (first information, command block) is also prepared on the buffer of the component.

Here, both the EP1 area 10 and the CBW area 12 are storage areas having the bulk output endpoint EP1 as an entry. In addition, the EP1 area 10 is set (FIFO setting) so that information input first is output first, and the CBW area 12 is set (random access setting) so that random access of information can be performed.

In the present embodiment, the switch SW (switching means) is switched to the CBW area 12 side in the command phase (first phase), and the CBW transmitted from the host is written in the CBW area 12 . Then, the CPU (firmware, processing unit) reads the CBW written in the CBW area 12 and interprets the command. In this case, since the CBW area 12 is set to be randomly accessible, the CPU can read information at an arbitrary address in the CBW area 12 at high speed.

As shown in FIG. 7B , when shifting from the command phase (first phase) to the data phase (second phase), the switch SW is switched to the EP1 area 10 side. Thus, OUT data from the host can be written into the EP1 area 10 . Then, when the command interpretation by the CPU is completed, DMA transfer for transferring the OUT data of the EP1 area 10 to a subsequent device such as a hard disk drive is started.

For example, in the comparative example shown in FIG. 6C , during command interpretation by the CPU, OUT data from the host cannot be received, and NAK cannot be returned to the host.

On the contrary, in this embodiment, as shown in FIG. 7B , during the command interpretation by the CPU, the OUT data from the host is also received and can be written into the EP1 area 10 . Therefore, it is possible to return an ACK to the host and realize high-speed processing.

Especially in USB2.0, data is transferred at high speed from the host. Therefore, as shown in the comparative example of FIG. 6C , if the host continues to return NAK, the bus bandwidth will be lost, and the high-speed data transmission of USB2.0 cannot be used flexibly.

On the contrary, in this embodiment, as shown in FIG. 7B, ACK can be returned to the host, so the loss of the bus frequency band can be suppressed to a minimum, high-speed data transmission of USB2.0 can be generated, and the effective data transmission speed can be improved. .

In addition, in the comparative example, as shown in FIG. 8A , the CBW is stored in the first-in-first-out FIFO 600 . Therefore, the CPU needs to read the CBW sequentially from the head address of the FIFO 600 when interpreting the command. As a result, it takes time until the data length (dCBWDataTransferLength in FIG. 3 ) and the command (CBWCB), which are important in the command interpretation, are read, and the processing of the command interpretation is further delayed.

In contrast, in the present embodiment, the CBW is stored in the randomly accessible CBW area 12 as shown in FIG. 8B. Therefore, the CPU can first read out the data length and the command which are important in command interpretation, and the processing time for command interpretation can be saved. As a result, the effective data transfer rate can be further increased.

Therefore, in this embodiment, even in the area other than the head address of the CBW area 12 (the first storage area storing the first information), the data length (the length information of the second information) and the command (instructing to transmit the first information) are written. 2 information command block), the CBW area 12 is also set to be randomly accessible, so the data length and command can be read first, and the effective data transfer speed can be improved.

In addition, in order to efficiently DMA transfer data to a subsequent device (hard disk drive, etc.), it is desirable to set information in a first-in-first-out area (FIFO setting) in the EP1 area 10 . In this case, the EP1 area 10 can be set in a first-in first-out area by configuring registers, memories, etc. connected in series, or it can be set by trying to control the address of the RAM as described later. in a first-in, first-out zone.

2.2 Composition example

FIG. 9 shows a configuration example of the data transfer control device of this embodiment.

The data transfer control device in this embodiment includes a transceiver macro block 20, an SIE 30, an endpoint management circuit 40, a buffer management circuit 50, a buffer 60, a bulk transfer management circuit 70, and a DMACS0. In addition, the data transfer control device of the present invention does not need to include all the circuit blocks shown in FIG. 9, and may be constructed by omitting some of them.

Here, the transceiver macro block 20 is a circuit for realizing data transfer in the FS mode and HS mode of the USB (first bus). As the transceiver macroblock 20, for example, a macroblock unit in UTMI (USB2.0 Transceiver Macrocell Interface) that defines a part of the physical layer circuit and logical layer circuit of USB2.0 can be used. The transceiver macro block 20 includes a transceiver circuit 22 and a clock generation circuit 24 .

The transceiver circuit 22 includes an analog front-end circuit (receiving circuit, transmitting circuit) for transmitting and receiving data on the USB using differential signals DP and DM. In addition, it includes circuits for processing such as bit stuffing, non-bit stuffing, serial-to-parallel conversion, NRZI decoding, NRZI encoding, and sampling clock generation.

The clock generating circuit 24 is a circuit for generating an operation clock used by the data transfer control device and a clock used for generating a sampling clock, and includes a PLL and an oscillation circuit that support clocks of 480 MHz and 60 MHz.

SIE (Serial Interface Engine; Serial Interface Engine) is a circuit for performing various processes such as USB packet transfer processing, and includes a packet processing circuit 32, a stop and resume control circuit 34, and a transaction management circuit 36.

The packet processing circuit 32 is a circuit that assembles (generates) and disassembles a packet composed of a header and data, and includes a CRC processing circuit 33 that generates and decodes a CRC.

The stop and resume control circuit 34 is a circuit for performing sequence control at the time of stop and resume.

The transaction management circuit 36 is a circuit that manages transactions constituted by packets of flags, data, handshake, and the like. Specifically, in the case of receiving a tag packet, it is confirmed whether it is sent to itself, and in the case of sending to itself, the transfer processing of the data packet is performed between the hosts, and then the transfer of the handshake packet is performed deal with.

The endpoint management circuit 40 is a circuit that manages the endpoints of each storage area entry of the buffer 60, and includes registers (register group) that store attribute information of the endpoints, and the like.

The buffer management circuit 50 is a circuit that manages a buffer 60 composed of, for example, a RAM or the like. More specifically, a write address and a read address are generated, and data write processing to the buffer 60 and data read processing from the buffer 60 are performed.

The buffer 60 (packet storage means) temporarily stores data (packets) transmitted via the USB, and has a function to compensate for the speed difference between the data transmission speed in the USB (the first bus) and the data transmission speed in the EBUS (the second bus). Function. Also, EBUS is an external bus connected to devices (mass storage devices) such as hard disk drives and CD drives.

In this embodiment, when distributing multiple types of information as information transmitted through one endpoint, a first storage area (such as a command block) for the first information (such as a command block) is prepared (secured) on the buffer 60. storage area) and a second storage area (eg data storage area) for second information (eg data).

The bulk transfer management circuit 70 is a circuit for managing bulk transfer in USB.

DMAC 80 is a DMA controller for DMA transfer via EBUS and includes DMA counter 82 . Also, the DMA counter 82 is a circuit that counts the amount of data (the number of transfers) transferred via the EBUS.

2.3 Detailed configuration example

FIG. 10 shows a detailed configuration example of the transaction management circuit 36 (SIE), the endpoint management circuit 40 , the buffer management circuit 50 , and the buffer 60 .

Buffer 60 (RAM) includes: CBE area 61 of CBW (command block) storing information allocated to endpoint EP1; EP0 area 62 of control storing information allocated to EP0; EP1 storing OUT data of information allocated to EP1 Area 63; EP2 area 64 of the IN data allocated to the information of EP2.

In FIG. 10, the CBW area 61 is set so as to be randomly accessible by the CPU (firmware, processing unit). On the other hand, the EP0, EP1, and EP2 areas 62, 63, and 64 are set (FIFO settings) so that the information input first can be output first.

The transaction management circuit 36 outputs write data SIEWrData (write packet) transmitted via USB to the buffer 60 , and inputs read data SIERdData (read packet) from the buffer 60 .

The transaction management circuit 36 outputs the write request signal SIEWrReq and the read request signal SIERdReq to the buffer management circuit 50 , and receives the write acknowledgment signal SIRWrAck and the read acknowledgment signal SIERdAck from the buffer management circuit 50 .

The transaction management circuit 36 outputs a transaction end signal TranEndPulse, a transaction status signal TranStatus, an endpoint number designation signal EPnum, and a transmission direction designation signal Direction to the endpoint management circuit 40 , and receives an endpoint existence signal Epexist from the endpoint management circuit 40 .

The endpoint management circuit 40 includes registers (register groups) 42, 43, and 44 for describing attribute information of endpoints (endpoint number, maximum packet size, etc.). Furthermore, an endpoint selection signal Epsel is generated based on various signals from the transaction management circuit 36 and attribute information of the register, and is output to the buffer management circuit 50 .

The endpoint management circuit 40 outputs the write request signal CPUWrReq and the read request signal CPURdReq from the CPU to the buffer management circuit 50 , and receives the write acknowledgment signal CPUWrAck and the read acknowledgment signal CPURdAck to the CPU from the buffer management circuit 50 .

The EP0 register 42 including the endpoint management circuit 40 is a register for describing attribute information of control endpoints defined by default in the USB standard.

The EP1 and EP2 registers 43 and 44 are registers for describing attribute information of bulk-out and bulk-in endpoints defined by the BULK-Only standard. It should be noted that whether any of the endpoints EP1 to 15 is set as an endpoint for batch output or batch input is optional on the device side.

In the EP1 register 43, the flag DIR indicating the transfer direction of data is set as OUT, and EP1 is set as the end point of the batch output.

In the EP1 register 43, the flag EnCBW is set to 1. This EnCBW is a flag for connecting an endpoint to the CBW area 61 of the buffer 60 , and an endpoint whose EnCBW is set to 1 is connected to the CBW area 61 .

In the EP2 register 44, the flag DIR indicating the transfer direction of the data is set to IN, and EP2 is set as the end point of the batch input.

In addition, EnCBW is set to 0 in the EP2 register 44 .

The buffer management circuit 50 receives the write and read request signals from the transaction management circuit 36 and the endpoint management circuit 40, the endpoint selection signal Epsel from the endpoint management circuit 40, and sends the address Address and the write pulse xWR (x means negative logic ) is output to the buffer 60. This buffer management circuit 50 includes address generation circuits 51 , 52 , 53 , and 54 for CBW, EP0 , EP1 , and BP2 , and a selector 56 .

Here, the CBW address generation circuit 51 generates a write or read address AD0 of SIEWrData and SIERdData to the CBW area 61 (start address a0).

In addition, the address generation circuits 52, 53, and 54 of EP0, EP1, and EP2 generate write or read data of SIEWrData and SIERdData in areas 62, 63, and 64 (start addresses a1, a2, and a3) of EP0, EP, 1, and EP2, respectively. Out addresses AD1, AD2, AD3.

The selector 56 selects one of the addresses AD0 to 3 according to the signal Epsel, and outputs it to the buffer 60 as an Address, and outputs the write pulse xWR to the buffer 60 . Specifically, AD0 is selected in the case of selecting and specifying CBW by EPsel, AD1 is selected in the case of selecting and specifying EP0, AD2 is selected in the case of selecting and specifying EP1, and AD3 is selected in the case of selecting and specifying EP2, and output as Address to Buffer 60.

In addition, CPURdData can be read from the CBW area 61 by the CPU. In this case, the buffer management circuit 50 outputs an Address for reading CPURdData to the buffer 60 according to EPsel or CPURdReq from the endpoint management circuit 40 .

FIG. 11 shows another configuration example of the transaction management circuit 36 , the endpoint management circuit 40 , the buffer management circuit 50 , and the buffer 60 .

In FIG. 11 , which is different from FIG. 10 , buffer 60 includes FIFOs 65 , 66 , 67 , and 68 (for example, serially connected registers and memories) used by CBW, EP0 , EP1 , and EP2 .

The selector 57 including the buffer management circuit 50 outputs the SIEWrData from the transaction management circuit 36 to the buffer 60 as any one of WrDataCBW, WrDataEP0, WrDataEP1, and WrDataEP2 according to the EPsel from the endpoint management circuit 40.

Alternatively, the selector 57 selects one of RdDataCBW, RdDataEP0, RdDataEP1, and RdDataEP2 from the buffer 60 according to EPsel, and outputs it to the transaction management circuit 36 as SIERdData.

More specifically, in the case of selecting and indicating CBW through EPsel, select WrDataCBW and RdDataCBW; in the case of selecting and indicating EP0, select WrDataEP0 and RdDataEP0; in the case of selecting and indicating EP1, select WrDataEP1 and RdDataEP1; In the case of EP2, select WrDataEP2, RdDataEP2.

Then, writing of data into the buffer 60 is performed by a write pulse SIEWR from the transaction management circuit 36 , and reading of data from the buffer 60 is performed by a read pulse SIERD from the transaction management circuit 36 .

In FIG. 11, the FIFO 65 (CBW) may be set in a random-accessible storage area.

2.4 Working conditions

12 to 16 show examples of timing waveform diagrams illustrating the detailed operation of the data transfer control device of this embodiment.

2.4.1 When successful

FIG. 12 is a timing waveform diagram at the start of the command phase (see B1 in FIG. 5A ), and FIG. 13 is a timing waveform diagram at the end of the command phase.

As shown in C1 and C2 of FIG. 12, if the transaction management circuit 36 sets Epnum to 1 (endpoint number=1) and sets Direction to OUT, then there is a register 43 of the batch output endpoint EP1 (refer to FIG. 10 ). , so the endpoint management circuit 40 activates Epexist (H level) as indicated by C3.

At this time, as shown in C4, the EnCBW of the endpoint EP1 is set to H level (1), so the endpoint management circuit 40 outputs EPsel for selecting address AD0 indicating the CBW area 61 to the buffer management circuit as shown in C5. 50. Accordingly, the selector 56 of the buffer management circuit 50 selects the address AD0 generated by the CBW address generation circuit 51 .

Then, as shown in C6, if the transaction management circuit 36 validates SIEWrReq, then as shown in C7, the buffer management circuit 50 outputs AD0=a0 from the CBW address generation circuit 51 to the buffer 60 as Address, and at the same time, as shown in C8 display, make xWR valid (L level). Thus, with a0 in the CBW area 61 of the buffer 60 as the head address, bytes 0 to 3 of CBW (SIEWrData) are written as indicated by C9. Then, as indicated by C10, SIEWrAck is enabled, and an acknowledgment is returned to the transaction management circuit.

Next, as shown in C11, when the transaction management circuit 36 validates SIEWrReq, as shown in C12 and C13, the buffer management circuit 50 outputs AD0=a0+4 as Address to the buffer 60, and simultaneously enables xWR. Thereby, using a0+4 of the CBW area 61 as the head address, as indicated by C14, 4 to 7 bytes of CBW (SIEWrData) are written. Then, as indicated by C15, SIEWrAck is enabled, and an acknowledgment is returned to the transaction management circuit 36.

By repeating the above writing process, all 0 to 30 bytes (31 bytes in total) of the CBW are written into the CBW area 61 as shown in C16 of FIG. 13 .

Then, as shown in C17, if an ACK is properly returned to the host, then as shown in C18, the transaction management circuit 36 enables TranEndPusel, and simultaneously as shown in C19, TranStatus is set to Success, and the successful situation of the transaction is transmitted to the endpoint management Circuit 40.

Then, as indicated by C20, EnCBW of the endpoint EP1 (register 43 in FIG. 10 ) is set to L level (0). Thereby, as indicated by C21 , the endpoint management circuit 40 outputs the EPsel for selecting the address AD2 indicating the EP1 area 63 to the buffer management circuit 50 . As a result, the selector 56 of the buffer management circuit 50 selects the address AD2 of the EP1 area 63 as the Address output to the buffer 60 in the subsequent data phase (see B3 in FIG. 5A ).

Therefore, in this embodiment, the EnCBW of the endpoint EP1 is set to L level (refer to C20) on the condition that the acknowledgment ACK for the data transmission in the command stage (first stage) is returned to the host (refer to C17), and the The writing area of data transferred from the host to the endpoint EP1 is switched from the CBW area 61 (first storage area) to the EP1 area 63 (second storage area) (see C21). Then, in the data phase, data from the host is written into the switched EP1 area 63 .

Therefore, by performing zone switching according to whether or not an ACK is returned, reliable zone switching without errors can be realized with a small processing load.

2.4.2 Data length error, CRC error

Fig. 14 is a timing waveform diagram in the case where there is an error in the data length (CBW length) written in the command phase.

When there is an error in the data length (when the data length is short or long), as shown in D1 of FIG. 14 , NAK is returned to the host instead of ACK. Then, the transaction management circuit 36 outputs to the endpoint management circuit 40 TranStatus indicating that there is an error in the data length as shown in D2. Therefore, in this case, unlike the case of C20 in FIG. 13 , as shown in D3 in FIG. 14 , EnCBW at the end point EP1 does not become L level. Therefore, as shown in D4, EPsel also does not change, and area switching from the CBW area 61 to the EP1 area 63 is not performed. In addition, the so-called error in the data length means that there is a possibility that there is an interface mismatch between the host and the device, so the endpoint is blocked.

Fig. 15 is a timing waveform diagram of a case where a CRC error occurs in the command phase.

When a CRC error occurs, as shown in E1 in FIG. 15 , no ACK is returned to the host. Then, the transaction management circuit 36 outputs TranStatus indicating a CRC error indicated by E2 to the endpoint management circuit 40 . Therefore, in this case, unlike the case of C20 in FIG. 13 , EnCBW at the end point EP1 does not become L level as shown in E3 in FIG. 15 . Therefore, as indicated by E4, EPsel does not change, and the area switching from the CBW area 61 to the EP1 area 63 is not performed. As a result, the host that has not received the ACK performs rewriting processing, and if the CBW can be retransmitted, writes the CBW in the CBW area 61 instead of the EP1 area 63 . Thereby, appropriate data transfer can be realized.

2.4.3 Trigger errors

Fig. 16 is a timing waveform diagram in the case where a trigger error occurs in the command phase.

First, a trigger error will be described with reference to FIGS. 17A and 17B.

In USB, in order to synchronize the ordering of transactions between the host and the device, as shown in FIG. 17A, DATA0 and DATA1 are prepared as the PID of the data, and at the same time, there are trigger bits in the host and the device (used between the host and the device) bits used to synchronize the ordering of transactions).

Furthermore, as shown in FIG. 17A , the host and the device trigger DATA0 and DATA1 included in the PID of the data and the trigger bit on the condition that the transaction is determined to be successful.

For example, as shown in G1 of FIG. 17A , if ACK is properly returned for the transmitted data (DATA1), the host determines that the transaction is successful, and triggers the trigger bit on the host side.

In addition, as shown in G2, if the next incoming data (PID=DATA1) is transmitted from the host and ACK is returned to the host, the device determines that the transaction is successful and triggers the trigger bit on the device side.

On the other hand, as shown in G3 of FIG. 17B , when the transmitted data (PID=DATA1) is not properly returned with ACK, the host determines that the transaction is unsuccessful, and the trigger bit on the host side is not triggered. Then, as shown in G4, the data of PID=DATA1 is retransmitted to the device.

Then, as shown in G5, since there is data of PID=DATA0 and data of PID=DATA1 can be transmitted, the device judges that it is a trigger error and does not trigger the trigger bit on the device side. Then, in this case, the device discards the data of PID=DATA1, and returns ACK to the host. Thus, continuity of transactions can be ensured between the host and the device.

In this embodiment, when such a trigger error occurs, even if an acknowledgment ACK is returned to the master, area switching from the CBW area 61 to the EP1 area 63 is not performed.

That is, in the case of a trigger error, as shown by F1 in FIG. 16 , ACK is returned to the host. Then, the transaction management circuit 36 outputs a TranStatus indicating a trigger error as indicated by F2 to the endpoint management circuit 40 . Therefore, in this case, as shown by F3 in FIG. 16 , EnCBW at the end point EP1 does not become L level. Therefore, as indicated by F4, EPsel also does not change, and area switching from the CBW area to the EP1 area 63 is not performed. As a result, suitable data transfer processing can be achieved even in the event of a trigger error.

2.5 Comparative example and the comparison of present embodiment

An example of a timing waveform diagram of the comparative example (FIGS. 6A to 6D ) is shown in FIG. 18A , and a timing waveform diagram of the present embodiment is shown in FIG. 18B . 18A and 18B are timing waveform diagrams in the case where the storage area of the buffer is a double buffer structure.

For example, in the comparative example of FIG. 18A, in the command phase, as indicated by H1, the CBW from the host is written in the FIFO for EP1 (600 in FIG. 6A). At this time, when FIFO is constructed with a double buffer, as shown in H2, the first OUT data from the host can be written in FIFO. However, the next OUT data cannot be written in the FIFO, so as shown in H3, NYET is returned to the next OUT data request from the host.

Then, as shown in H4, even if the host can send a PING packet to inquire whether there is a vacancy in the FIFO, as shown in H5, the device will return NAK. That is, the device continues to return NAK to the host until the CPU's command interpretation is completed. Then, the command interpretation ends, and if a vacancy occurs in the FIFO, as indicated by H6, the OUT data from the host is received and can be written in the FIFO.

In this regard, in this embodiment, as shown in H7 of FIG. 18B, CBW is written in the CBW area, and when ACK is returned appropriately, EnCBW becomes L level as shown in H8 (see C20 in FIG. 13 ). . Then, as described in FIG. 7B , switching is performed from the CBW area to the EP1 area, and the end point EP1 is connected to the EP1 area.

Therefore, as shown in H9, the OUT data from the host in the endpoint can be written into this EP1 area, and ACK can be returned to the host. Then, as shown in H10, when the command interpretation is completed, as shown in H11, DMA transfer between subsequent hard disk drives and the like can be started using this EP1 area, and data from the USB can be efficiently transferred.

Therefore, in this embodiment, the DMA transfer of data can be started earlier than in the comparative example, so that the loss of the bus bandwidth can be suppressed to a minimum, and the effective data transfer speed can be increased compared with the comparative example.

FIG. 19A shows a processing flowchart of the firmware (CPU) in the case of the comparative example, and FIG. 19B shows a processing flowchart of the firmware in the case of the present embodiment.

In the comparative example of FIG. 19A, the firmware first judges whether or not the OUT transaction has ended (step S1). That is, it waits for the slave to return the ACK of H1 in FIG. 18A .

Then, when it is judged that the OUT transaction is completed, the firmware reads the CBW from the FIFO for EP1 (step S2). Then, it is judged whether the data length is 31 bytes (whether the data length is appropriate) (step S3), and in the case of 31 bytes, command interpretation is performed (step S4), and the command process is moved to (step S5). On the other hand, when it is not 31 bytes, it moves to error processing (step S6).

In the present embodiment of FIG. 19B, the firmware first judges whether or not the CBW transaction (reading of the CBW area) indicated by H7 in FIG. 18B has just ended (step S11). Then, when the CBW transaction is not completed, it is judged whether there is a CBW error (step S12), and when the CBW error occurs, the process proceeds to error processing (step S16). On the other hand, if there is no CBW error, it returns to step S11 and waits for the end of the CBW transaction.

For example, in the case of an error in the data length shown in FIG. 14 , it is judged to be a CBW error, and the process proceeds to error processing in step S16 . On the other hand, in the case of a trigger error in FIG. 16, it is not judged as a CBW error, and the process returns from step S12 to step S11.

On the other hand, when the data transfer in FIG. 13 is successful, it is determined that the transaction of CBW is completed, and EnCBW becomes L level. Then, the firmware reads the CBW from the CBW area (step S13), performs command interpretation (step S14), and moves to command processing (step S15). In this case, as described in Fig. 8A and Fig. 8B, in this embodiment, the CBW area is set to be random access, so compared with the comparative example, the command interpretation can be completed as soon as possible, and the DMA transmission can be moved to as soon as possible. .

3. Electronic devices

Next, an example of an electronic device including the data transfer control device of the present embodiment will be described.

For example, FIG. 20A shows an internal block diagram of a printer as an electronic device, and FIG. 21A shows its external view. A CPU (microcomputer) 510 performs control and the like of the entire system. The operation unit 511 is used for the user to operate the printer. ROM516 stores a control program, fonts, etc., and RAM517 functions as a work area of CPU510. DMAC518 is a DMA controller that performs data transfer without CPU510. The display panel 519 notifies the user of the working status of the printer.

Serial print data transferable from other devices such as a personal computer via USB is converted into parallel print data by the data transfer control device 5000 . Then, the converted parallel print data is sent to the print processing unit (printer engine) 512 via the CPU 510 or the DMAC 518 . Then, in the print processing unit 512, given processing is performed on the parallel print data, and the print unit (device that performs data output processing) 514 composed of a print head and the like prints out the data on paper.

FIG. 20B shows an internal block diagram of a scanner as an electronic device, and FIG. 21B shows its external view. CPU520 performs control etc. of the whole system. The operation unit 521 is used for the user to operate the scanner. ROM526 stores a control program and the like, and RAM527 functions as a work area for CPU510. DMAC528 is a DMA controller.

An image reading unit (device for reading data) 522 composed of a light source, a photoelectric transducer, etc. reads an image of a document, and the read image data is processed by an image processing unit (scanner engine) 524 . Then, the processed image data is transferred to the data transfer control device 500 via the CPU 520 or the DMAC 528 . The data transfer control device 500 converts the parallel image data into serial data, and sends it to other devices such as a personal computer via USB.

Fig. 20C shows an internal block diagram of a CD-RW drive as an electronic device, and Fig. 21 shows its external view. CPU530 performs control etc. of the whole system. The operation unit 531 is used for the user to operate the CD-RW. A control program and the like are stored in ROM536, and RAM537 functions as a work area of CPU530. DMAC538 is a DMA controller.

The data read from the CD-RW 532 is input to the signal processing unit by the reading and writing unit (a device for taking in data or a device for storing data) 533 composed of a laser, a motor, an optical system, etc. 534. Perform given signal processing such as error correction processing. Then, the data subjected to signal processing is transferred to the data transfer control device 500 via the CPU 530 or the DMAC 538 . The data transfer control device 500 converts the parallel image data into serial data, and sends it to other devices such as a personal computer via USB.

On the other hand, serial data transferred from another device via USB is converted into parallel data by the data transfer control device 500 . And this parallel data is sent to the signal processing part 534 via CPU530 or DMAC538. Then, given signal processing is performed on the parallel data in the signal processing unit 534 , and the data is stored in the CD-RW 532 through the read/write unit 533 .

In FIG. 20A , FIG. 20B , and FIG. 20C , in addition to CPUs 510 , 520 , and 530 , CPUs for data transfer control in data transfer control device 500 may be provided, respectively.

If the data transfer control device of this embodiment is used in an electronic device, data transfer in the HS mode in USB2.0 can be appropriately performed. Therefore, when the user instructs a printout through a personal computer or the like, the printing is completed at least in real time. In addition, after instructing the scanner to read the image, the user can observe the read image with little delay. In addition, reading of data from the CD-RW and writing of data to the CD-RW can be performed at high speed.

Furthermore, if the data transfer control device of this embodiment is used in an electronic device, it is possible to manufacture a data transfer control device capable of data transfer in the HS mode even with an ordinary semiconductor processor which is inexpensive to manufacture. Therefore, the cost reduction of the data transfer control device can be realized, and the cost reduction of the electronic device can also be realized. In addition, the reliability of data transmission can be improved, and the reliability of electronic devices can also be improved.

In addition, if the data transfer control device of this embodiment is used in an electronic device, the processing load of firmware operating on the CPU can be reduced, and an inexpensive CPU can be used. Furthermore, cost reduction and downsizing of the data transfer control device can be realized, so that cost reduction and downsizing of the electronic device can also be realized.

As electronic devices that can adopt the data transfer control device of this embodiment, in addition to the above, there are, for example, various optical disk drives (CD-ROM, DVD), optical disk drives (MO), hard disk drives, TVs, VTRs, video cameras, etc. , audio equipment, telephones, projectors, personal computers, electronic notebooks, word processors and other devices.

The present invention is not limited to this embodiment, and various modifications can be made within the scope of the main spirit of the present invention.

For example, the configuration of the data transfer control device of the present invention is not limited to the configurations shown in FIGS. 9 , 10 , and 11 , and various modifications can be made.

In this embodiment, the case where the first storage area is the CBW area (command storage area) and the second storage area is the EP1 area (data storage area) has been described, but the present invention is not limited thereto. That is, the types of information stored in the first and second storage areas are arbitrary. In addition, the number of information set in the endpoint may be three or more, and the types of information are also arbitrary.

In addition, in this embodiment, an application example to the USB Bulk-Only standard is described, but the standard to which the present invention is applied is not limited to the USB Bulk-Only standard.

In addition, the method of switching between the first and second storage areas is not limited to the method described in detail in FIGS. 7A to 19B , and various modifications can be made.

In addition, the present invention particularly expects to adopt data transmission in USB2.0, but is not limited thereto. For example, the present invention can be applied even to data transfer in a standard based on the same idea as USB2.0 or a standard developed from USB2.0.

Claims (17)

1. a data transmission control device is used for transmitting by the data of bus, it is characterized in that, comprising:

Impact damper comprises in distribution under the situation of multiple information as the information that transmits by an end points of the 1st, the 2nd information, and the 2nd storage area that the 1st storage area that the 1st information of preparing is used and the 2nd information are used comes corresponding to an end points; And

The buffer management circuit, in the 1st stage of transmitting the 1st information by bus, to be written to described the 1st storage area that the 1st information is used to the information that end points transmits from main frame, and in the 2nd stage of transmitting the 2nd information by bus, will be written to described the 2nd storage area that the 2nd information is used to the information that end points transmits from main frame;

To be set in the random-access zone of the information of can carrying out for the 1st information with described the 1st storage area of preparing;

To be set in the zone of the information elder generation output that will import previously for the 2nd information with described the 2nd storage area of preparing.

2. data transmission control device as claimed in claim 1 is characterized in that:

In the zone beyond the beginning address of described the 1st storage area of storage the 1st information, write that indication transmits the command block of the 2nd information and at least one information of the length information of the 2nd information that transmits by the command block indication.

3. data transmission control device as claimed in claim 1 is characterized in that:

Carry out with the specification of USB (universal serial bus) is the data transmission of standard.

4. a data transmission control device is used for transmitting by the data of bus, it is characterized in that: comprising:

Impact damper comprises in distribution under the situation of multiple information as the information that transmits by an end points of the 1st, the 2nd information, and the 2nd storage area that the 1st storage area that the 1st information of preparing is used and the 2nd information are used comes corresponding to an end points; And

The buffer management circuit, in the 1st stage of transmitting the 1st information by bus, to be written to described the 1st storage area that the 1st information is used to the information that end points transmits from main frame, and in the 2nd stage of transmitting the 2nd information by bus, will be written to described the 2nd storage area that the 2nd information is used to the information that end points transmits from main frame;

Being returned to main frame with the affirmation that transmits for the data in described the 1st stage is condition, the writing the zone and switch to described the 2nd storage area from described the 1st storage area of the information that will transmit to end points from main frame.

5. data transmission control device as claimed in claim 4 is characterized in that:

Trigger under the situation that bit produces mistake in the ordering data in synchronization that is used for carrying out issued transaction between the main frame,, also do not carry out from of the switching of described the 1st storage area to described the 2nd storage area even be returned under the situation of main frame confirming.

6. data transmission control device as claimed in claim 4 is characterized in that:

Carry out with the specification of USB (universal serial bus) is the data transmission of standard.

7. a data transmission control device is used for transmitting by the data of bus, it is characterized in that: comprising:

Impact damper comprises in distribution under the situation of multiple information as the information that transmits by an end points of the 1st, the 2nd information, and the 2nd storage area that the 1st storage area that the 1st information of preparing is used and the 2nd information are used comes corresponding to an end points; And

The buffer management circuit, in the 1st stage of transmitting the 1st information by bus, to be written to described the 1st storage area that the 1st information is used to the information that end points transmits from main frame, and in the 2nd stage of transmitting the 2nd information by bus, will be written to described the 2nd storage area that the 2nd information is used to the information that end points transmits from main frame;

Described the 1st information is the packets of information of command block;

Described the 2nd information is the packets of information according to the data of the indication transmission of described command block.

8. data transmission control device as claimed in claim 7 is characterized in that:

Explain in processing element during the packets of information of described command block, the packets of information of data is written to described the 2nd storage area.

9. data transmission control device as claimed in claim 7 is characterized in that:

Carry out with the specification of USB (universal serial bus) is the data transmission of standard.

10. a data transmission control device is used for transmitting by the data of bus, it is characterized in that, comprising:

Impact damper, under the situation of packets of information as the information that transmits by an end points of the packets of information of assignment commands piece and data, the data storage areas that comes demanded storage zone that the warning order piece uses and data to use corresponding to an end points; And

The buffer management circuit, under the situation of the data phase that switches to the packets of information by bus transmissioning data from the command phase of transmitting the packets of information of command block by bus, the described demanded storage zone that makes piece use of obeying the order, zone that writes of information is switched to the data storage areas that data are used, and the packets of information of the data that will transmit to end points from main frame be written to described data storage areas.

11. the data transmission control device as claim 10 is characterized in that:

Carry out with the specification of USB (universal serial bus) is the data transmission of standard.

12. an electronic installation is characterized in that, comprising:

Any one data transmission control device as claim 1 to 9; And

The output of carrying out the data that transmit by described data transmission control device and bus is handled or is taken into and handles or the device of stores processor.

13. an electronic installation is characterized in that, comprising:

Any one data transmission control device as claim 10 or 11; And

The output of carrying out the data that transmit by described data transmission control device and bus is handled or is taken into and handles or the device of stores processor.

14. a control method for data transfer is used for transmitting by the data of bus, it is characterized in that:

Comprise in distribution under the situation of multiple information as the information that transmits by an end points of the 1st, the 2nd information, the 2nd storage area that the 1st storage area that the 1st information of preparing on impact damper is used and the 2nd information are used comes corresponding to an end points; And

In the 1st stage of transmitting the 1st information by bus, to be written to described the 1st storage area that the 1st information is used to the information that end points transmits from main frame, and in the 2nd stage of transmitting the 2nd information by bus, will be written to described the 2nd storage area that the 2nd information is used to the information that end points transmits from main frame;

To be set in the random-access zone of the information of can carrying out for the 1st information with described the 1st storage area of preparing;

To be set in the zone of the information elder generation output that will import previously for the 2nd information with described the 2nd storage area of preparing.

15. a control method for data transfer is used for transmitting by the data of bus, it is characterized in that:

Comprise in distribution under the situation of multiple information as the information that transmits by an end points of the 1st, the 2nd information, the 2nd storage area that the 1st storage area that the 1st information of preparing on impact damper is used and the 2nd information are used comes corresponding to an end points; And

In the 1st stage of transmitting the 1st information by bus, to be written to described the 1st storage area that the 1st information is used to the information that end points transmits from main frame, and in the 2nd stage of transmitting the 2nd information by bus, will be written to described the 2nd storage area that the 2nd information is used to the information that end points transmits from main frame;

Being returned to main frame with the affirmation that transmits for the data in described the 1st stage is condition, the writing the zone and switch to described the 2nd storage area from described the 1st storage area of the information that will transmit to end points from main frame.

16. a control method for data transfer is used for transmitting by the data of bus, it is characterized in that:

Comprise in distribution under the situation of multiple information as the information that transmits by an end points of the 1st, the 2nd information, the 2nd storage area that the 1st storage area that the 1st information of preparing on impact damper is used and the 2nd information are used comes corresponding to an end points; And

In the 1st stage of transmitting the 1st information by bus, to be written to described the 1st storage area that the 1st information is used to the information that end points transmits from main frame, and in the 2nd stage of transmitting the 2nd information by bus, will be written to described the 2nd storage area that the 2nd information is used to the information that end points transmits from main frame;

Described the 1st information is the packets of information of command block;

Described the 2nd information is the packets of information according to the data of the indication transmission of described command block.

17. a control method for data transfer is used for transmitting by the data of bus, it is characterized in that:

Under the situation of packets of information as the information that transmits by an end points of the packets of information of assignment commands piece and data, the data storage areas that demanded storage zone that the warning order piece is used on impact damper and data are used is next corresponding to an end points; And

Under the situation of the data phase that switches to the packets of information by bus transmissioning data from the command phase of transmitting the packets of information of command block by bus, the described demanded storage zone that makes piece use of obeying the order, zone that writes of information is switched to the data storage areas that data are used, and the packets of information of the data that will transmit to end points from main frame be written to described data storage areas.

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