CN100349380C - Prarallel cascade code coding and decoding method - Google Patents
Prarallel cascade code coding and decoding method Download PDFInfo
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Abstract
The present invention provides a parallel cascade code encoding and decoding method. A known bit is inserted into an information bit stream of the transmitting end, and the performance of the decoding is enhanced by the high energy of a known inserted bit signal at the receiving end. The method comprises the following steps that (1) the known bit is inserted; (2) the parallel cascade encoding is carried out; (3) the inserted bit is deleted; (4) the transmission is realized by a communication channel; (5) the inserted bit with appropriate energy is restored; (6) the parallel cascade decoding is carried out. The encoding and decoding method proposed by the present invention can obviously reduce iterative frequencies, reduce the time delay of a decoder, enhance the speed of decoding and enhance the stability of the decoder simultaneously. Under the condition of low signal-to-noise ratio, the decoder can still keep stable decoding performance.
Description
Technical field
The present invention relates to the Error-correcting Encoding and Decoding method in the digital communication system, in particular, relate to the coding and decoding method of the parallel cascade codes (Turbo Code is called for short TC) in 3-G (Generation Three mobile communication system).
Background technology
Parallel cascade codes is a kind of coding and decoding method that generally adopts in 3-G (Generation Three mobile communication system), can improve the decoding performance of data packet services greatly.Parallel cascade codes its performance in Gaussian channel approaches the Shannon capacity limit, and parallel cascade codes adopts iteration, the decoding algorithm of soft input/soft output, and performance substantially exceeds traditional convolutional encoding under identical decoding complex degree.Because the capacity and the Signal-to-Noise of Wideband Code Division Multiple Access (WCDMA) (WCDMAWideband Code Division Multiple Access) system are in close relations, so performance improvement has directly improved power system capacity.
Shannon (shannon) information theory is pointed out, when on noisy channel, using grouping error correction coding or convolution code etc., have only when the constraint length n of block length or convolutional encoding is tending towards infinity, the performance of error correction coding could be near the theoretical limit of Shannon, as utilize the random code average behavior can reach theoretical value, but in fact be difficult to realize.The most frequently used interpretation method is maximum likelihood algorithm (ML Maximum Likelihood), and index increases but the complexity of this algorithm is with the increase of n, up to the degree that in fact can not realize.Therefore people are seeking code check near the Shannon theory value always for a long time, and the error rate is little, the good sign indicating number that decoding complexity is low, and the method for good yard of many structures has been proposed.The parallel cascade codes of people such as Berrou proposition in 1993 is actually the ingenious comprehensive and development of previous work, initial report achievement shows that its decoding performance can be near the Shannon theory value, as to utilize two code checks be the parallel cascade codes that 1/2 convolution code parallel cascade forms, when signal to noise ratio was 0.7dB, bit error rate can reach 10
-5, many theories and actual application show that parallel cascade codes provides the approach of the good sign indicating number of structure really, so parallel cascade codes becomes the research focus of international information opinion and coding theory circle very soon, and attempt to be applied in the various communication systems.
In 3-G (Generation Three mobile communication system), comprise WCDMA, code division multiple access (CDMA2000 CodeDivision Multiple Access), the S-CDMA of time division way (TD-SCDMA TimeDivision-Synchronization Code Division Multiple Access) system all adopts the coding and decoding mode of parallel cascade codes (Turbo Code) as data channel, the parallel cascade codes decoding performance obviously is better than convolution code, it is long more to divide into groups, performance improves obvious more, is very suitable for the coding and decoding of the big grouping of data channel.But also there are two significant disadvantages in existing parallel cascade code coding/decoding method: 1, because decoding adopts is iterative algorithm, the decoding algorithm complexity, in the existing coding and decoding method decoder the time prolong, speed is slow; 2, under low signal-to-noise ratio, have the decoding effect instability of coding and decoding method now, the situation of iteration failure or decoding performance difference often appears.
Summary of the invention
The objective of the invention is on the basis of existing parallel cascade code coding/decoding method, to propose a kind of coding and decoding method that can overcome the parallel cascade codes of above-mentioned shortcoming.
Main thought of the present invention is on the basis of existing parallel cascade code coding/decoding method, inserts known bits in the message bit stream of transmitting terminal, and at receiving terminal by utilizing the high energy of known insertion bit signal, improve the performance of decoding.
Technical scheme of the present invention is as follows: a kind of coding and decoding method of parallel cascade codes comprises the steps:
The first step is inserted a certain proportion of known bits in the message bit stream of transmitting terminal;
The second step parallel concatenated coding device will contain the bit stream of inserting bit information encodes;
Known insertion bit in the bit stream behind the 3rd step deletion coding;
The 4th step transmitted by channel with certain code rate;
The 5th step recovered to insert the bit of giving certain energy to the code stream that receives on known location;
The 6th step parallel cascade decoder is deciphered the code stream that recovers the insertion bit.
Wherein the known bits in the first step is the bit stream that complete " 1 ", complete " 0 " or " 0 ", " 1 " replace.
Certain code rate can adopt 1/3 code rate in the 4th step, also can adopt 1/2 or 1/4 code rate.
Inserting a certain proportion of known bits in the first step in the message bit stream of transmitting terminal realizes by multiplexer.In the 5th step the code stream that receives being recovered to insert the bit of giving certain energy on known location realizes by demodulation multiplexer.
Channel in the 4th step can be Gaussian channel, rayleigh fading channel, vehicle-mounted channel and indoor channel.
The proportion that inserts a certain proportion of known bits in the first step is between 1/3～1/9.
The insertion bit power that the bit of giving certain energy in the 5th step adopts promotes with 10dB.
The present invention inserts known bits in the message bit stream of transmitting terminal on the basis of existing parallel cascade code coding/decoding method, by utilizing the high energy of known insertion bit signal, improved the big performance of decoding at receiving terminal greatly.The coding and decoding that adopts the present invention to propose can reduce the time delay of decoder obviously to reduce iterations, improves the speed of decoding; Also improve the stability of decoder simultaneously, make that decoder still can keep stable decoding performance under the situation of low signal-to-noise ratio, so the present invention has had good prospects for application in 3-G (Generation Three mobile communication system).
Description of drawings
Fig. 1 is the theory diagram of existing parallel cascade code coder.
Fig. 2 is the theory diagram of existing parallel cascade code decoder.
Fig. 3 is the flow chart of the coding and decoding method that proposes of the present invention.
Fig. 4 is when adopting 1/3 code rate, the variation schematic diagram of bit stream in handling process.
Fig. 5 is under different grouping length, the comparison schematic diagram of decoding performance under the decoding performance of the method that employing the present invention proposes and the traditional coding and decoding method.
Fig. 6 is under the situation of different insertion bit power assignment, the comparison schematic diagram of decoding performance under the decoding performance of the method that employing the present invention proposes and the traditional coding and decoding method.
Fig. 7 inserts under the bits proportion in difference, the comparison schematic diagram of decoding performance under the decoding performance of the method that employing the present invention proposes and the traditional coding and decoding method.
Embodiment
Below in conjunction with accompanying drawing the application of the present invention in 3-G (Generation Three mobile communication system) is described in further detail.
Fig. 1 is the theory diagram of existing parallel cascade code coder.As shown in Figure 1, existing parallel cascade code coder (is called that " Turbo interleaver ") forms by two parallel recursive convolutional encoder devices 101,102 and the interleaver 103 before the second recursive convolutional encoder device.These two recursive convolutional encoder devices are called the composition encoder of parallel cascade codes, information bit is by these two encoder encodes, first recursive convolutional encoder device 101 is according to input original order coding, the information bit sequential encoding of second recursive convolutional encoder device 102 after according to interleaver 103 changes order.According to the code check that sets, export from the parity bit of prime information bit and two recursive convolutional encoder devices respectively.Further specify in conjunction with Fig. 1: systematic code is from the output of X end, and recursive convolutional encoder device 101 output verification sign indicating number Y1 behind the original information bits process interleaver 103, have upset order, through recursive convolutional encoder device 102 back output verification sign indicating number Y2.After passing through the parallel cascade code coder as can be seen, information bit has increased by 2 times redundancy check bit, and code rate is 1/3.Parallel cascade codes can have higher code rate, can increase redundant bit by the quantity that increases recursive convolutional encoder device and interleaver and improve decoding performance.
Fig. 2 is the theory diagram of existing parallel cascade code decoder.As shown in Figure 2, the parallel cascade code decoder is made up of first decoder 201, interleaver 202, second decoder 203, deinterleaver 204, deinterleaver 205 and interleaver 206.Its course of work is as follows: the soft-decision likelihood value that the system of first composition sign indicating number and parity bits soft-decision (maximum likelihood) information Y1 will be input to after first decoder, 201, the first decoders will upgrade is sent into second decoder 203 through behind the interleaver 202.In addition, second decoder also receives through the original information bits X behind the interleaver 206, and corresponding to parity bits channel soft decision information Y2.The likelihood information that upgraded, the soft-decision output from second decoder 203 feeds back to first decoder through deinterleaver 205, repeats this process then.This process can repeat arbitrarily repeatedly, but only needs limited circulation several times just passable in actual applications, and too much iteration can cause output saturated sometimes on the contrary.Afterbody is through carrying out hard decision output behind the deinterleaver 204.
Fig. 3 is the flow chart of the coding and decoding method that proposes of the present invention.As shown in Figure 3, the coding and decoding method of the present invention's proposition comprises the following steps: 1, inserts known bits.Insert a certain proportion of known bits in the message bit stream of transmitting terminal, inserting bit can be complete " 1 ", complete " 0 ", perhaps alternately inserts " 1 ", " 0 ", and this insertion process can be carried out according to certain ratio by a multiplexer.At this moment, having inserted a certain proportion of known bits point bit stream is 301.2, parallel concatenated coding, parallel concatenated coding device will contain the bit stream 301 of inserting bit information encodes.Through the bit stream behind the coding is 302.3, bit is inserted in deletion, i.e. known insertion bit in the bit stream 302 behind the deletion coding.The code stream that deletion is inserted behind the bit is 303.4, transmit by channel, transmit by channel with certain code rate.The code rate here can adopt 1/3 code rate, also can adopt 1/2 or 1/4 code rate; Being sent to channel can be Gaussian channel, rayleigh fading channel, vehicle-mounted channel or indoor channel, Gaussian channel described herein is pure noisy communication channel, and rayleigh fading channel is the wireless multipath fading channel, and vehicle-mounted channel and indoor channel are typical fading channel test environments.5, recover to insert the bit of suitable energy.The code stream 303 that receives is recovered to insert the bit of giving suitable energy on known location, and this step can finish by a demodulation multiplexer.The bit stream of recovering the bit of the suitable energy of insertion is 304.6, parallel cascade decoding, the parallel cascade decoder is deciphered the code stream 304 that recovers the insertion bit.What parallel cascade codes adopted is iterative decoding algorithm, and what adopt usually is BCJR (Bahl, Cocke, Jelinek and Rajiv Algorithm) and MAP (Maximum a posteriori) algorithm.The basic principle of iterative decoding algorithm be decoding algorithm not only with the bit of needs decoding near soft decision information relevant, and relation is all arranged with whole decoding grouping, so can be assigned on each decoding position because the insertion bit has been endowed high energy, thereby improved the decoding performance of whole coding groups, therefore adopted the method for inserting known bits can under the situation of not obvious increase redundant bit, obviously improve the coding and decoding performance of parallel cascade codes.
Fig. 4 is when adopting 1/3 code rate, the variation schematic diagram of bit stream in handling process.As shown in Figure 4, what Fig. 4-a represented is the schematic diagram of bit stream 301, has evenly inserted the part known bits in message bit stream.What Fig. 4-b represented is the schematic diagram of bit stream 302, and information bit and known insertion bit are all encoded, and becomes code rate and be 1/3 the systematic code and the code stream of check code.What Fig. 4-c represented is the schematic diagram of bit stream 303, and the insertion bit of dotted portion is deleted to reduce the redundant efficient that improves coding.What Fig. 4-d represented is the schematic diagram of bit stream 304, the code stream 303 that receives is recovered to insert bit on known location, and give very high energy, enters decoder subsequently and deciphers normally.
Fig. 5 is under different grouping length, the comparison schematic diagram of decoding performance under the decoding performance of the method that employing the present invention proposes and the traditional coding and decoding method.As shown in Figure 5, because the parallel cascade codes employing is that iteration is pursued the bit decoding method, block length is long more, and decoding performance is good more.Fig. 5 is the insertion bit performance that will observe under different grouping length, and the block length of information bit has three kinds, 100,800 and 4800.Inserting bits proportion is 1/9, and promptly 9 information bits insert a known bits.As can be seen from Figure, it is long more to divide into groups, and the decoding performance of the coding and decoding method that the present invention proposes is good more, and when block length N=4800, performance improves 1.7dB; And during N=800, performance improves 1.0dB; During N=100, performance improves has only 0.7dB, illustrates and inserts the bit method to bigger than long grouping effect.
Fig. 6 is under the situation of different insertion bit power assignment, the comparison schematic diagram of decoding performance under the decoding performance of the coding and decoding method that employing the present invention proposes and the traditional coding and decoding method.As shown in Figure 6, when insertion bit power assignment was increased, the decoding performance raising of the method that the present invention proposes was tending towards saturated, in Fig. 6, insert bit power and information bit relatively, got four kinds of power, 0dB, 6dB, 9.5dB, 19.5dB, as can be seen from Figure 6, when raising power reaches 9.5dB, performance improves very limited, compares with 19.5dB, has only the difference of 0.2dB, find out thus, select the power ascension about 10dB more reasonable.
Fig. 7 inserts under the bits proportion in difference, the comparison schematic diagram of decoding performance under the decoding performance of the method that employing the present invention proposes and the traditional coding and decoding method.As shown in Figure 7, the decoding performance of the coding and decoding method that the present invention proposes reaches capacity gradually along with the increase of inserting bits proportion, and main cause is to insert bits proportion to be increased, redundant bit also increases, so code rate is reducing, under same-code speed, performance boost is limited.As can be seen from Figure 7, the performance of inserting bits proportion 1/3 this shows that on the contrary not as the performance of insertion ratio 1/9 between inserting bits proportion is chosen in 1/3 to 1/9 be proper.
Claims (8)
1, a kind of coding and decoding method of parallel cascade codes is characterized in that comprising the steps:
The first step is inserted a certain proportion of known bits in the message bit stream of transmitting terminal;
The second step parallel concatenated coding device will contain the bit stream of inserting bit information encodes;
Known insertion bit in the bit stream behind the 3rd step deletion coding;
The 4th step transmitted by channel with certain code rate;
The 5th step recovered to insert the bit of giving certain energy to the code stream that receives on known location;
The 6th step parallel cascade decoder is deciphered the code stream that recovers the insertion bit.
2, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: the bit stream that the known bits in the described first step replaces for complete " 1 ", complete " 0 " or " 0 ", " 1 ".
3, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: certain code rate can adopt 1/3 code rate in described the 4th step, also can adopt 1/2 or 1/4 code rate.
4, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: insert a certain proportion of known bits in the described first step and realize by multiplexer in the message bit stream of transmitting terminal.
5, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: in described the 5th step code stream that receives is recovered to insert the bit of giving certain energy on known location and realize by demodulation multiplexer.
6, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: the channel in described the 4th step can be Gaussian channel, rayleigh fading channel, vehicle-mounted channel or indoor channel.
7, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: the proportion that inserts a certain proportion of known bits in the described first step is between 1/3～1/9.
8, the coding and decoding method of a kind of parallel cascade codes as claimed in claim 1 is characterized in that: the insertion bit power that the bit of giving certain energy in described the 5th step adopts promotes with 10dB.
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| CN101345607B (en) * | 2008-08-14 | 2012-07-25 | 西安电子科技大学 | Encoding/decoding method of multidimensional crossing parallel cascade single-parity check code |
| CN103795492B (en) * | 2013-09-30 | 2015-09-09 | 深圳光启智能光子技术有限公司 | Coding/decoding method in optical communication system, device and system |
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| WO2000008767A1 (en) * | 1998-08-06 | 2000-02-17 | Samsung Electronics Co., Ltd. | Channel encoding/decoding in communication system |
| CN1275264A (en) * | 1998-08-20 | 2000-11-29 | 三星电子株式会社 | Device and method for inserting previously known bits in input stage of channel encoder |
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