CN100349148C - Core logic chips used in computer systems - Google Patents
Core logic chips used in computer systems Download PDFInfo
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- CN100349148C CN100349148C CNB2005100713067A CN200510071306A CN100349148C CN 100349148 C CN100349148 C CN 100349148C CN B2005100713067 A CNB2005100713067 A CN B2005100713067A CN 200510071306 A CN200510071306 A CN 200510071306A CN 100349148 C CN100349148 C CN 100349148C
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- interrupt controller
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Abstract
The invention relates to a core logic chip, which is applied to a computer system with a central processing unit and a peripheral device, and comprises: a programmable interrupt controller, electrically connected to the peripheral device, for responding to an external interrupt signal sent by the peripheral device and sending a control signal through an interrupt signal pin when the operating system of the computer system is not loaded; an input/output advanced programmable interrupt controller electrically connected to the peripheral device, which can respond to the external interrupt signal sent by the peripheral device to send an interrupt control packet with interrupt vector content to the central processing unit when the operating system of the computer system is loaded and the programmable interrupt controller is disabled; and a virtual wiring function block, electrically connected to the interrupt signal pin of the programmable interrupt controller, for responding to the trigger of the control signal and sending a virtual wiring interrupt control packet to the central processing unit.
Description
Technical field
The present invention relates to a kind of core logic chipset, relate in particular to a kind of core logic chipset that is applied on the computer system.
Background technology
See also Fig. 1, interrupt control configuration diagram for central processing unit in the conventional computer system, after 11 pairs of South Bridge chips of peripheral unit (South Bridge) 12 send an external interrupt signal, this external interrupt signal can be delivered to programmable interrupt controller (the ProgrammableInterrupt Controller of South Bridge chip 12 inside, be called for short PIC) 121, after this programmable interrupt controller 121 is received this external interrupt signal, just can notify central processing unit (CPU) 13 to have external interrupt signal to produce by look-at-me pin (INTR), after central processing unit 13 is notified, just read interrupt vector (interrupt vector) data about this external interrupt signal to programmable interrupt controller 121 again, different interrupt vectors makes central processing unit 13 to read different service routine (service routine) in the different addresses in the Installed System Memory 10 by north bridge chips 14 and carries out different actions.And because this programmable interrupt controller 121 is only notified central processing unit (CPU) 13 by a look-at-me pin (INTR), therefore central processing unit 13 need cause process comparatively complicated again by the next action of reading vector value to interruptable controller 121 of additional programs.And this interrupt control mode is except older computer system is used, computer system is in start now, and also be to keep such control model when operating system loads before finishing as yet, the programmable interrupt controller pattern that this just is commonly called as (PIC mode).
And with advanced programmable interrupt controller (the I/O Advanced Programmable Interrupt Controller of input and output, abbreviation I/O APIC) technology is applied to after the computer system, its framework can be the interrupt control configuration diagram with the computer system of the advanced programmable Interrupt control technology of input and output referring to shown in Figure 2, still be to use programmable interrupt controller 221 as the interrupt control assembly during computer system power-on, when operating system loads, just one in the advanced programmable interrupt controller 222 of input and output guiding table (redirection table) content again can be set (set 24 projects (entry) entry0 to entry23 as shown in the figure usually for, and each project having 64).And after the operating system loading is finished, but obtain the just generation of response external look-at-me of operating system of ownership, utilize the advanced programmable interrupt controller 222 of these input and output to transmit some projects (entry) to central processing unit 23 by a bus 24, and has interrupt vector (normally the 0th 's to the 7th) information in the project of being sent (entry) content simultaneously, so can reduce number of times and flow that the interrupt control signal of central processing unit 23 and South Bridge chip 22 transmits back and forth, and make the processing speed of entire system promote.Details are as follows again is and the interrupt control under this framework is moved: after the operating system loading is finished, programmable interrupt controller 221 will be by forbidden energy, to no longer produce signal on the look-at-me pin (INTR), take over and carry out interrupt control but set the advanced programmable interrupt controller 222 of the input and output finished by content, after 21 pairs of South Bridge chips 22 of peripheral unit send an external interrupt signal, the advanced programmable interrupt controller 222 of this input and output just can respond the triggering of this external interrupt signal and utilize project (entry) data packets that bus 24 directly transmits corresponding this external interrupt signal to central processing unit 23, and the interrupt vector that is had in project (entry) content (normally the 0th to the 7th) just can make central processing unit 23 read different service routine (service routine) in the different addresses by north bridge chips 24 in the Installed System Memory 20 to carry out different actions.And the advanced programmable Interrupt control model (APIC mode) that Here it is is commonly called as.
In addition, in MultiProcessor Specification the 1.4th edition (MultiProcessor Specification V1.4), the deviser imports a virtual circuit pattern (Virtual wire mode) again, and relevant synoptic diagram sees also Fig. 3.This virtual circuit pattern (Virtual wire mode) can be set in Basic Input or Output System (BIOS) (BIOS), operate in then operating system load as yet finish before.Owing to have central processing unit 33 partly look-at-me pin (INTR) to be omitted, so programmable interrupt controller (PIC) 321 just can't directly utilize its look-at-me pin (INTR) to transmit look-at-me to central processing unit 33 in programmable interrupt controller pattern (PIC mode).
And this above-mentioned virtual circuit pattern just can be in order to replace the problem that look-at-me pin (INTR) that programmable interrupt controller pattern (PICmode) solves central processing unit 33 is omitted, its practice mainly is fixedly to be made as 111 with the 8th among the entry0 in advanced programmable interrupt controller 322 contents to the 10th, and its framework can be referring to virtual circuit interrupt control architecture synoptic diagram shown in Figure 3.And before operating system is not finished loading as yet, the 8th to the 10th of the entry0 of the advanced programmable interrupt controller 322 of input and output is fixed and is made as 111, so this look-at-me of being sent when peripheral unit (device) 31 is delivered to the programmable interrupt controller (PIC) 321 of South Bridge chip 32 inside, this programmable interrupt controller 321 is received in the time of can notifying input and output advanced person programmable interrupt controller 322 can utilize bus 34 to send entry0 to central processing unit 33 by the look-at-me pin (INTR) of itself after this look-at-me, but because the 8th to the 10th fixedly be made as 111, therefore when the 8th to the 10th of central processing unit 33 discovery entry0 is 111, just can ignore the 0th to the 7th interrupt vector, and the data of directly removing to read in the programmable interrupt controller 321 correct interrupt vector (interrupt vector).The problem that the look-at-me pin (INTR) that just can solve central processing unit 33 like this is omitted.
And after operating system is finished loading, system just can transfer advanced programmable Interrupt control model (APIC mode) to, this moment, programmable interrupt controller 321 will be by forbidden energy, to no longer produce signal on the look-at-me pin (INTR) on it, carry out interrupt control and set the advanced programmable interrupt controller 322 of the input and output of finishing by content.So after 31 pairs of South Bridge chips 32 of peripheral unit send an external interrupt signal, this external interrupt signal will trigger this advanced person's programmable interrupt controller 322, make the advanced programmable interrupt controller 322 of input and output can utilize bus 34 to send some projects (entry), and the interrupt vector that is had in project (entry) content (normally the 0th to the 7th) just can make central processing unit 33 directly read different service routine (service routine) in the different addresses in the Installed System Memory 30 to carry out different actions to central processing unit 33.Only to be kept be 111 to the 8th of entry0 the to the 10th need, so can't be used in advanced programmable Interrupt control model (APICmode), makes that an only remaining entry1 to entry23 can be used.
But, partly operating system (for example the Netware5.1 version of novell, inc. and 6.0 editions) is arranged, the discovery system has the advanced programmable interrupt controller (I/O APIC) of input and output in loading procedure, just can automatically it be carried out initialization action, and the full content of the table (redirection table) that wherein leads again will be eliminated, cause the 8th to the 10th of entry0 can't remain 111 always, make that to solve the problem mechanism that the look-at-me pin (INTR) of central processing unit 33 is omitted with the virtual circuit pattern destroyed, so when having look-at-me produce at this moment, central processing unit 33 can't be apprised of and cause interrupt control generation problem and the generation system when the state of machine.
Above-mentionedly undeservedly the advanced programmable interrupt controller of input and output (I/O APIC) are carried out the interrupt control problem that caused after the initialization action because of firmware or software and how to solve, make computer system that higher interrupt control Reliability be arranged, for developing fundamental purpose of the present invention.
Summary of the invention
Fundamental purpose of the present invention, the invention provides a kind of core logic chipset, be applied in the computer system, this computer system has a central processing unit and a peripheral unit, this core logic chipset comprises: a programmable interrupt controller, be electrically connected on this peripheral unit, it is when operating system of this computer system loads as yet when finishing, and can respond the external interrupt signal that this peripheral unit sends and sends a control signal by a look-at-me pin; The advanced programmable interrupt controller of one input and output, be electrically connected on this peripheral unit, it is finished and this programmable interrupt controller during by forbidden energy when operating system of this computer system loads, can respond this external interrupt signal that this peripheral unit sends and send have the interrupt vector content an interrupt control package to this central processing unit; An and virtual connection function piece, be electrically connected on this look-at-me pin of this programmable interrupt controller, it responds the triggering of this control signal and sends a virtual wiring interrupt control package to this central processing unit, has the information that makes this central processing unit ignore interrupt vector content in this package in this virtual wiring interrupt control package.
According to above-mentioned conception, core logic chipset of the present invention, when wherein this programmable interrupt controller was by forbidden energy, this look-at-me pin just stopped to send this control signal.
According to above-mentioned conception, core logic chipset of the present invention, wherein the advanced programmable interrupt controller of this input and output has the guiding table again that content can be set by the operating system of this computer system, this again the guiding table include a plurality of interrupt control packet datas with different interrupt vector contents.
According to above-mentioned conception, core logic chipset of the present invention be the content that stores this virtual wiring interrupt control package in this virtual connection function piece wherein, and this content can not removed by the operating system of this computer system.
According to above-mentioned conception, core logic chipset of the present invention, the information that wherein makes this central processing unit ignore interrupt vector content in this package is fixedly to be made as 111 with the 8th in 64 bit data to the 10th, and the interrupt vector content is the 0th to the 7th.
According to above-mentioned conception, core logic chipset of the present invention, wherein the look-at-me pin of this programmable interrupt controller is electrically connected in the advanced programmable interrupt controller of this input and output a project of guiding table again, and this core logic chipset also comprises a multiplexer, its input end is electrically connected to the advanced programmable interrupt controller of this virtual connection function piece and this input and output respectively, and be subjected to one select signal control and will this virtual connection function piece and the output package of this input and output advanced person programmable interrupt controller select an output.
Description of drawings
Fig. 1 is the interrupt control configuration diagram of central processing unit in the conventional computer system.
Fig. 2 is an interrupt control configuration diagram of using the computer system of the advanced programmable Interrupt control technology of input and output in the conventional computer system.
Fig. 3 is the interrupt control configuration diagram of virtual circuit pattern in the conventional computer system.
The core logic chipset that Fig. 4 develops out for the above-mentioned conventional means defective of improvement for the present invention is applied to the preferred embodiment function block diagram in the computer system.
The core logic chipset that Fig. 5 develops out for the above-mentioned conventional means defective of improvement for the present invention is applied to another preferred embodiment function block diagram in the computer system.
Wherein, description of reference numerals is as follows:
11 peripheral units, 12 South Bridge chips
121 programmable interrupt controller, 13 central processing units
14 north bridge chips, 10 Installed System Memories
The advanced programmable interrupt controller of 221 programmable interrupt controller, 222 input and output
24 buses, 23 central processing units
22 South Bridge chips, 21 peripheral units
24 north bridge chips, 20 Installed System Memories
33 central processing units, 321 programmable interrupt controller
The advanced programmable interrupt controller of 34 buses, 322 input and output
31 peripheral units, 32 South Bridge chips
40 central processing units, 41 peripheral units
42 core logic chipsets, 420 north bridge chips
421 South Bridge chips, 422 Front Side Buss
4210 programmable interrupt controller, 4212 virtual connection function pieces
The advanced programmable interrupt controller of 4211 input and output
43 buses, 44 Installed System Memories
5213 multiplexers, 50 central processing units
51 peripheral units, 52 core logic chipsets
520 north bridge chips, 521 South Bridge chips
522 Front Side Buss, 5210 programmable interrupt controller
The advanced programmable interrupt controller of 5212 virtual connection function piece 5211 input and output
53 buses, 54 Installed System Memories
Embodiment
See also Fig. 1, the core logic chipset that its present invention develops out for the above-mentioned conventional means defective of improvement is applied to the preferred embodiment function block diagram in the computer system, at first, this computer system has a central processing unit 40 and a peripheral unit 41, and this core logic chipset 42 mainly is made up of a north bridge chips 420 and a South Bridge chip 421, north bridge chips 420 links by a Front Side Bus 422 and central processing unit 40, and includes a programmable interrupt controller 4210 in the South Bridge chip 421, an advanced programmable interrupt controller 4211 of one input and output and a virtual connection function piece 4212.
And this programmable interrupt controller 4210 is electrically connected on this peripheral unit 41, its major function is to be to load as yet when finishing when the operating system of this computer system, can respond the external interrupt signal that this peripheral unit 41 sends and sends a control signal by a look-at-me pin (INTR).And look-at-me pin (INTR) is electrically connected to virtual connection function piece 4212, this virtual connection function piece 4212 stores the content of a virtual wiring interrupt control package, with form commonly used at present is example, its length is 64, and the 8th to the 10th be 111, and since virtual connection function piece 4212 not among the advanced programmable interrupt controller 4211 of input and output, so content can not removed because of carelessness by software or firmware.So in the virtual circuit pattern; before operating system is not finished loading as yet; and 31 of peripheral units (device) are when sending an external interrupt signal; virtual connection function piece 4212 will be triggered by the control signal on the look-at-me pin (INTR) of programmable interrupt controller (PIC) 4210; and then (can be interruptable controller communication (InterruptController Communication) bus usually by bus 43 virtual wiring interrupt control package; be called for short ICC-Bus; if when central processing unit 40 also omits the pin of ICC-Bus, then use Front Side Bus 422 instead) send.The look-at-me pin (INTR) that so just can solve central processing unit 40 simultaneously is omitted the problem of the improper removing of software such as the system that is operated with the advanced programmable interrupt controller 4211 of input and output.After finishing when the operating system loading, system just enters advanced programmable Interrupt control model (APIC mode), this moment, programmable interrupt controller 4210 will be by forbidden energy, to no longer produce signal on the look-at-me pin (INTR), take over and carry out interrupt control but set the advanced programmable interrupt controller 4211 of the input and output finished by content, after 41 pairs of South Bridge chips 421 of peripheral unit send external interrupt signal, the advanced programmable interrupt controller 4211 of this input and output just can respond the triggering of this external interrupt signal and utilize project (entry) data packet that bus 43 directly transmits corresponding this external interrupt signal in guiding table (redirection table) again to central processing unit 40, and the interrupt vector that is had in project (entry) content (normally the 0th to the 7th) just can make central processing unit 40 directly read different service routine (service routine) in the different addresses in the Installed System Memory 44 to carry out different actions.
Please again referring to Fig. 5, it is that the present invention is that core logic chipset that the above-mentioned conventional means defective of improvement develops out is applied to another preferred embodiment function block diagram in the computer system, equally, this computer system has a central processing unit 50 and a peripheral unit 51, and this core logic chipset 52 mainly is made up of a north bridge chips 520 and a South Bridge chip 521, north bridge chips 520 links by a Front Side Bus 522 and central processing unit 50, and includes a programmable interrupt controller 5210 in the South Bridge chip 521, the advanced programmable interrupt controller 5211 of one input and output, an one virtual connection function piece 5212 and a multiplexer 5213.
For the elasticity that keeps using, present embodiment is set up a multiplexer 5213 more, and its major function is to allow user's elasticity of signal transmission path that changes.By the change (selecting the high-low level of signal to set in basic input/output system (BIOS)) of selecting signal, multiplexer 5213 can select to transmit the package content output of advanced programmable interrupt controller 5211 of input and output or virtual connection function piece 5212.In detail, in programmable Interrupt control model (PIC mode), when the operating system of being moved in the system can't be improper during the table of guiding again in the advanced programmable interrupt controller 5211 of removing input and output, then multiplexer 5213 just can select the package in the advanced programmable interrupt controller 5211 of input and output to export, and this programmable interrupt controller 4210 is electrically connected on this peripheral unit 41, and when the operating system of being moved in the system and can be improper in the advanced programmable interrupt controller 5211 of removing input and output the table of guiding again and when causing when machine, then multiplexer 5213 just can be exported by the virtual connection function square frame 5212 interior packages of controlled selection.
In sum, the technology of the present invention means can effectively be improved the defective of conventional means, and then reduce computer system and work as the problem of machine because of interrupt control is bad, thoroughly reach development fundamental purpose of the present invention.But the above only is preferred embodiment of the present invention; be not in order to limit claim of the present invention; and the technology of the present invention thought can be applied to having on the computer system of interrupt control mechanism widely; therefore all other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should comprise in the scope of patent protection of the present invention.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100713067A CN100349148C (en) | 2005-05-09 | 2005-05-09 | Core logic chips used in computer systems |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100713067A CN100349148C (en) | 2005-05-09 | 2005-05-09 | Core logic chips used in computer systems |
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| CN100349148C true CN100349148C (en) | 2007-11-14 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2298503A (en) * | 1993-12-16 | 1996-09-04 | Intel Corp | Multiple programmable interrupt controllers in a multi-processor system |
| US6029223A (en) * | 1996-08-02 | 2000-02-22 | Micron Electronics, Inc. | Advanced programmable interrupt controller |
| US6470408B1 (en) * | 1999-04-14 | 2002-10-22 | Hewlett-Packard Company | Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors |
| CN1499388A (en) * | 2002-10-31 | 2004-05-26 | ض� | Event transmitting |
| CN1540539A (en) * | 2003-10-28 | 2004-10-27 | 威盛电子股份有限公司 | Interrupt signal control system and control method |
-
2005
- 2005-05-09 CN CNB2005100713067A patent/CN100349148C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2298503A (en) * | 1993-12-16 | 1996-09-04 | Intel Corp | Multiple programmable interrupt controllers in a multi-processor system |
| US6029223A (en) * | 1996-08-02 | 2000-02-22 | Micron Electronics, Inc. | Advanced programmable interrupt controller |
| US6470408B1 (en) * | 1999-04-14 | 2002-10-22 | Hewlett-Packard Company | Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors |
| CN1499388A (en) * | 2002-10-31 | 2004-05-26 | ض� | Event transmitting |
| CN1540539A (en) * | 2003-10-28 | 2004-10-27 | 威盛电子股份有限公司 | Interrupt signal control system and control method |
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| CN1687911A (en) | 2005-10-26 |
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