CN100349122C - Method for realizing data packet sequencing for multi engine paralled processor - Google Patents

Abstract

The invention discloses a method for realizing data packet sorting in a multi-engine parallel processor. The key is to generate a tag code during the distribution process of the data stream and save it as a sequence, and to store it in the data stream during the collection process. The tags in the sequence are decoded in sequence, the engine channel or load channel corresponding to the tag is selected, and a corresponding complete data packet is output in sequence, and only one data packet is allowed to be output. Thereby solving the ordering of output packets. Applying the present invention has the following advantages: it is not necessary to use a separate queuing machine to realize data packet sorting, which reduces system resource overhead; at the same time, because the sorting function is combined with a multi-engine parallel processor, the impact of sorting on the efficiency of parallel processing is reduced to It is the smallest and reduces the possibility of system congestion; multi-engine parallel processors can guarantee the logical order of data packets without occupying a large amount of shared memory of the system.

Description

A Method for Realizing Data Packet Sequencing in Multi-Engine Parallel Processor

technical field

The invention relates to the technical field of multi-engine parallel processors, in particular to a method for realizing data packet sorting in multi-engine parallel processors.

Background technique

Multi-engine parallel processors provide a solution to break through the limitations of single-engine processing capabilities. In theory, if factors such as the speed of the interface and the amount of resources implemented by the hardware are not considered, the processing capacity of the multi-engine parallel processor can be unlimited. In practical applications, multi-engine parallel processors are usually divided into multiple load levels in structure, and each load level is divided into multiple load paths, and each load path at the bottom layer has a packet processing engine (PE ), these engines can work in parallel. Assuming that the total level of load is N, any level is represented by n, and the n satisfies 1≤n≤N. There are m load paths in each layer, then the number of load paths from the first layer to the nth layer is m ₁ , m ₂ ... m _n , and the total number of engines P is P=m ₁ ×m ₂ ×... × m _n .

For the convenience of explanation, the abbreviations of several concepts are first defined as follows:

Layer n Load Balance Unit (Layer n Load Balance Unit), abbreviated as LnBU;

Layer n Input Cache Unit (Layer n Input Cache Unit), abbreviated as InCU;

Layer n Load Pooling Unit (Layer n Load Pooling Unit), abbreviated as LnPU;

Layer n Output Cache Unit (Layer n Output Cache Unit), abbreviated as OnCU.

The following takes n=2, m ₁ =2, m ₂ =4, and P=8 as an example for illustration.

Referring to FIG. 1, FIG. 1 is a schematic structural diagram of an 8-engine parallel processor. The data flow of Baowen in this multi-engine parallel processor is:

1. The layer 1 load balancing module (L1BU, Layer 1 Load Balance Unit) distributes the input data packets to two layer 1 input buffer modules (I1CU, Layer 1 Input Cache) according to the arbitration strategy of load balancing or Round Robin Cache Unit).

2. The two I1CUs are responsible for the data input buffer of their respective load paths.

3. Two layer 2 load balancing modules (L2BU, Layer 2 Load Balance Unit) distribute the data packets of their respective load paths to four layer 2 input buffer modules ( In I2CU, Layer 2 Input Cache Unit), each I2CU corresponds to a packet processing engine (PE, Packet Engine). That is to say, each L2BU distributes the data packets of its respective load path to four PEs.

4. PE obtains the data packet to be processed from the I2CU, and stores the data packet in the Layer 2 output cache module (O2CU, Layer 2 Output Cache Unit) after the processing is completed.

5. Each layer 2 load collection module (L2PU, Layer 2 Load Pooling Unit) collects the output data packets of the four packet processing engines from the four O2CUs on their respective load paths, and outputs them to the layer in a certain order 1 output cache module (O1CU, Layer 1 Output CacheUnit).

6. O1CU is responsible for the data output buffer of their respective load paths.

7. The L1PU collects the output data packets of the two O1CUs and outputs them in a certain order.

It can be seen from the above processing that since L1BU and L2BU _i (where i is 0 and 1) do not consider the order of packets when distributing data packets to each engine; and because the load of each packet processing engine is not It may be exactly the same, and the order in which the processing of the packets allocated to each engine in sequence cannot be guaranteed. Therefore, the output data packets after processing by the multi-engine parallel processor will not be able to guarantee the logical sequence.

The existing implementation method for guaranteeing the logical sequence of data packets in a multi-engine parallel processor is as follows:

Before the data packet enters the multi-engine parallel processor, a queuing machine (generally realized by software) is used to insert a sequence mark in the data packet, and each processing module in the multi-engine parallel processor must transparently transmit the mark. After the data packets are processed and output by the multi-engine parallel processor, the queuing machine is used to query the marks in the data packets, and the data packets are sorted according to the marks.

Due to the existence of the queuing machine, the existing implementation methods must have the following defects:

1. Due to the use of a separate queuing machine to implement data packet sorting, additional system resources will be occupied;

2. If the queuing machine cannot complete the sorting of the data packets output by the multi-engine parallel processor in time, it will cause system congestion and affect the computing efficiency of the multi-engine parallel processor;

3. In the process of using the queuing machine to implement data packet sorting, it is necessary to cache all the data packets that have been processed first, but occupy a large amount of shared memory in the system.

Contents of the invention

In view of this, the object of the present invention is to provide a method for realizing data packet sequencing in multi-engine parallel processors, so as to solve the problem of data packet sequencing in multi-engine processing.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

A method for realizing data packet sorting in a multi-engine parallel processor, the multi-engine parallel processor includes more than one layer of load balancing modules LBU, and each LBU corresponds to a load collection module LPU, the LPU and the corresponding LBU at the same level,

In a multi-engine parallel processor, more than one sequence for recording tag information is preset, and each sequence corresponds to one LBU;

The LBU performs the following processing steps:

A. The LBU receives the data packet to be processed, and distributes the received data packet to the processing module of the next layer according to the preset distribution principle, and marks the distributed data packet to indicate where the data packet is load path, and record the mark in the sequence corresponding to the LBU;

B. The LBU judges whether the number of recorded information in its corresponding sequence reaches the preset threshold for the number of flow control data packets. If so, stop the distribution operation, and then repeat step B, otherwise, repeat the execution Step A;

The load collection module LPU corresponding to each LBU and at the same layer as the corresponding LBU performs the following processing steps:

a. The LPU judges whether the number of recorded information in the sequence corresponding to the corresponding LBU is non-empty, if yes, execute step b; otherwise, repeat step a;

b. The LPU sequentially reads a tag information from the sequence, obtains the location of the corresponding data packet according to the tag information, opens the output channel corresponding to the location, waits for a complete data packet to pass through, and only allows one data packet to pass through, Then repeat step a until all packets are output.

Preferably, if the LBU is a non-bottom LBU, then the processing module of the next layer described in step A is an LBU of the next layer; if the LBU is the bottom LBU, then the next layer described in step A The processing module of the layer is the packet processing engine PE.

Preferably, if the LBU of the load balancing module is the highest-level LBU, the threshold for the number of flow control data packets described in step B is the flow control threshold of the number of data packets of the data input port; if the load balancing module The LBU is a non-top layer LBU, and the threshold for the number of flow control data packets in step B is the flow control threshold for the number of data packets of the load path.

Preferably, the width B _n of the sequence is

B _n = [log ₂ (m _n )], where [ ] represents the rounding operation, and m _n is the number of load channels of the next layer corresponding to the LBU;

The depth of the sequence corresponding to the highest level LBU is the flow control threshold of the number of data packets at the data input port;

The depth of the sequence corresponding to the non-highest layer LBU is the flow control threshold of the number of data packets of the upper layer load path corresponding to the layer LBU.

Preferably, the method for determining the flow control threshold of the number of data packets at the data input port is:

First calculate the size of the cache space of the multi-engine parallel processor, and then divide the value of the cache space by the length of the minimum packet to obtain the maximum number of packets that can be accommodated, and then according to the maximum number of packets and the preset The strategy determines the flow control threshold of the number of data packets at the data input port.

Preferably, the method for calculating the size of the cache space of the multi-engine parallel processor is: calculating the sum of the cache spaces of all input cache modules ICU and output cache modules OCU in the multi-engine parallel processor.

Preferably, the method for determining the flow control threshold of the number of data packets of the load path is:

First calculate the size of all cache spaces in the load path, and then divide the value of the cache space by the length of the minimum packet to obtain the maximum number of packets that can be accommodated, and then according to the maximum number of packets and the preset The strategy determines the flow control threshold of the number of data packets in the load path.

Preferably, the method for calculating the size of all cache spaces in the load path is: calculating the sum of the cache spaces of all input cache modules ICU and output cache modules OCU in the load path.

Preferably, the preset strategy is to determine the flow control threshold according to resource overhead and/or impact on cache efficiency.

Preferably, said sequence is carried by a first-in-first-out FIFO buffer.

Preferably, the preset distribution principle includes a load balancing strategy or a round-robin (RoundRobin) arbitration strategy.

The key of the present invention is that the encoding of the mark is generated during the distribution process of the data stream and stored as a sequence, and the marks stored in the sequence are sequentially decoded during the collection process of the data stream, and the engine channel corresponding to the mark is selected Or the load channel, which outputs a corresponding complete data packet in sequence, and only allows one data packet to be output. Thereby solving the ordering of output packets.

Applying the present invention has the following advantages: it is not necessary to use a separate queuing machine to realize data packet sorting, which reduces system resource overhead; at the same time, because the sorting function is combined with a multi-engine parallel processor, the impact of sorting on the efficiency of parallel processing is reduced to It is the smallest and reduces the possibility of system congestion; multi-engine parallel processors can guarantee the logical order of data packets without occupying a large amount of shared memory of the system.

Description of drawings

Figure 1 shows a schematic diagram of the structure of an 8-engine parallel processor;

Fig. 2 is a schematic diagram of coding of the 8-engine parallel processor structure applying the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The thinking of the present invention is: generate the code of mark during the distribution process of data flow, and save it as a sequence, decode the marks stored in the sequence in sequence during the collection process of data flow, select the engine channel corresponding to the mark Or the load channel, which outputs a corresponding complete data packet in sequence, and only allows one data packet to be output. In this way, the marking of the input data packets and the sorting of the output data packets are completed.

In order to ensure that the data packets processed by each engine are output sequentially in a predetermined order, the input data packets must be uniquely marked before each LnBU distributes them to each load path or PE. In the LnPU, the sequence of output packets is controlled according to the pre-made tags.

The meaning of "unique mark" here means that in the limit case, the multi-engine parallel processor, that is, the packets that can be accommodated in the chip at the same time must have their own distinctive marks, and the number of "unique marks" is the number of multi-engine parallel processors. The maximum number of packets that can be accommodated at the same time. The "maximum number" is already the limit that the multi-engine parallel processor can accommodate. Usually, in order to reduce the length of the cache, it is necessary to perform flow control on the number of data packets, and to perform flow control, a reasonable flow control threshold needs to be set to reduce the impact of flow control on the cache efficiency.

In the present invention, two types of flow control thresholds are defined: one is the flow control threshold of the number of data packets at the data input port, which is used for flow control input of the data flow of the multi-engine parallel processor, so there is only one such threshold; The other is the flow control threshold of the number of data packets in the load path, which is used to control the flow of data input into each load path. Therefore, there are multiple thresholds of this type, and the number is the same as the actual number of multi-engine parallel processors. The number of load paths is the same. The following describes the setting process of the two types of thresholds respectively.

The process of setting the flow control threshold of the number of data packets at the data input port is: first calculate the size of the cache space of the multi-engine parallel processor, and then divide the value of the cache space by the length of the minimum packet to obtain the maximum The maximum number of packets, and then determine the flow control threshold of the number of data packets at the data input port according to the maximum number of packets and the preset strategy. The method for calculating the size of the cache space of the multi-engine parallel processor is as follows: calculating the sum of the cache spaces of all input cache modules (ICU) and output cache modules (OCU) in the multi-engine parallel processor. The aforementioned preset strategy is to determine the flow control threshold according to resource overhead and/or impact on cache efficiency.

Still taking n=2, m ₁ =2, m ₂ =4, P=8 as an example, referring to Fig. 1, if the cache space size of each I1CU and O1CU is 8Kbyte and 9Kbyte, the cache space size of each I2CU and O2CU is 2Kbyte, then, the size of the cache space of the multi-engine parallel processor, that is, the cache space size of the whole chip=the cache space size of each I1CU×the number+the cache space size of each O1CU×the number+the cache memory of each I2CU Space size × number + O2CU cache space size × number = 8×2+9×2+2×8+2×8=66Kbyte, assuming that in the limit case all packets are small packets with a length of 64 bytes, Then the number of packets simultaneously accommodated in the multi-engine parallel processor is 66Kbyte/64byte, about 1000. Here, the flow control threshold of the number of data packets at the data input port is set to 256 according to a predetermined policy. That is to say, when the number of concurrently accommodated multi-engine parallel processors reaches 256, flow control must be performed on input data packets.

The process of setting the flow control threshold for the number of data packets in the load path is: first calculate the size of all cache spaces in the load path, and then divide the value of the cache space by the length of the minimum packet to obtain the maximum that can be accommodated. The number of packets, and then determine the flow control threshold of the number of packets of the load path according to the maximum number of packets and the preset policy. The method for calculating the size of all cache spaces in the load path is as follows: calculating the sum of the cache spaces of all ICUs and OCUs in the load path. The aforementioned preset strategy is to determine the flow control threshold according to resource overhead and/or impact on cache efficiency.

Still taking n=2, m ₁ =2, m ₂ =4, P=8 as an example, referring to Fig. 1, if the size of the buffer space of each I2CU and O2CU is 2Kbyte, then, all the buffer spaces in each load path Size = buffer space size of each I2CU × number + buffer size of O2CU × number = 2×4+2×4=16Kbyte, assuming that all packets are small packets with a length of 64 bytes in the limit case, then The number of packets simultaneously accommodated in the load path is 16Kbyte/64byte=256 packets. Here, the flow control threshold of the number of data packets of the load path is set to 100 according to a predetermined policy. That is to say, when the number of packets simultaneously accommodated in the load path reaches 100, flow control must be performed on the data packets input into the load path.

As we all know, a multi-engine parallel processor usually includes more than one layer of load balancing modules (LBU), and each LBU corresponds to a load collection module (LPU), and the LPU is at the same layer as the corresponding LBU. For the convenience of description, in this application, the LBU used to receive data streams from outside the engine parallel processor is called the highest-level LBU, and the LBU used to allocate data streams to PEs is called the lowest-level LBU.

The highest-level LBU is used to control the data flow input to the multi-engine parallel processor, that is, the threshold for the number of data packets used for flow control is the flow control threshold of the number of data packets at the data input port; the non-highest-level LBU is used for The flow control inputs the data flow in each load path, that is, the threshold for the number of data packets used for flow control is the flow control threshold of the number of data packets of the load path.

Each data packet has P possible destinations in the multi-engine parallel processor, that is, one of the P engines. The m load channels in load level n are numbered from 0 to m _n , then the number of coding bits B _n in load level n is

B _n =[log ₂ (m _n )]

Among them, [ ] represents the rounding operation by 1, that is, when the decimal place is not 0, it is fixed by 1. Combine the codes Bi of all load levels in order to get the code of the mark.

The following still takes n=2, m ₁ =2, m ₂ =4, and P=8 as an example to describe the encoding. Referring to FIG. 2, FIG. 2 is a schematic diagram of coding of the 8-engine parallel processor structure applied in the present invention. In this example, each data packet has only 8 possible destinations in the multi-engine parallel processor, that is, one of the 8 PEs.

When the L1BU distributes the input data packets to two load channels, there are two options. At this time, the number of coded bits B ₁ =[log ₂ (m ₁ )]=[log ₂ 2]=1 of the L1BU record mark is coded as 1bit data, resulting in the first bit of the mark. That is, 0 and 1 are used to distinguish the two load channels. Referring to Figure 2, if it is distributed to load channel 0, it is marked as 1'b0, and if it is distributed to load channel 1, it is marked as 1'b1. And, the flag bit corresponding to each data packet is stored in a sequence in turn, and the sequence is defined as S_load ₁₁ . The width of the sequence S_load ₁₁ is B ₁ , that is, the width of the sequence in this example is one, and the maximum depth of the sequence S_load ₁₁ is the flow control threshold of the number of data packets of the data input port.

When L2BU0 distributes the data packets of load channel 0 to the four packet processing engines, there are four choices. At this time, the number of coding bits B ₂ of L2BU0 record marks =[log ₂ (m ₂ )]=[log ₂ 4 ]=2, encoded as 2bit data, thus generating the second and third bits of the mark. Referring to FIG. 2 , the marks distributed to the four PEs are respectively marked as 2'b11, 2'b10, 2'b01, and 2'b00. And, the flag bit corresponding to each data packet is stored in a sequence in turn, and the sequence is defined as S_load ₂₁ . The width of the sequence S_PE0 is B ₂ , that is, the width of the sequence in this example is two, and the maximum depth is the maximum number of packets contained in the payload path 0 at the same time, that is, the data packets of the payload path corresponding to the payload path 0 Number of flow control thresholds.

L2BU1 is at the same level as L2BU0 and its environment is also the same as that of L2BU0, so its processing is the same as that of L2BU0. That is, when the L2BU1 distributes the data packets of the load path 1 to the four packet text processing engines, there are four choices, which are encoded as 2-bit data, thereby generating the second and third bits of the mark. The flag bit corresponding to each data packet is stored in a sequence in turn, and the sequence is defined as S_load ₂₂ . The width of the sequence S_PE1 is two, and the maximum depth is the maximum number of packets simultaneously contained in the payload path 1, that is, the flow control threshold of the number of data packets of the payload path corresponding to the payload path 1.

It can be seen from this that the depth of the sequence corresponding to the highest level LBU is the data packet number flow control threshold of the data input port; the depth of the sequence corresponding to the non-highest level LBU is the load of the upper layer corresponding to the LBU of this level The flow control threshold of the number of data packets in the path.

It can be seen from the above processing that in order to achieve sorting, more than one sequence for recording tag information must be preset in the multi-engine parallel processor, and each sequence corresponds to one LBU; thus forming an LBU , LPU and the one-to-one relationship between the sequence. Wherein, the subscript of sequence S_load is represented by nk: n is the load level, K is the total number of LBUs in this layer, and one of the levels is represented by k, and the k satisfies 1≤k≤K.

With the above preparations, the process of sorting the data packets is described in detail below:

The LBU in the multi-engine parallel processor performs the following processing steps:

A. The LBU receives the data packets to be processed, and distributes the received data packets to the processing module of the next layer according to the preset distribution principle, such as load balancing strategy or circular Round Robin arbitration strategy, etc. The distributed data packet is marked to indicate the load path where the data packet is located, and the mark is recorded in the sequence corresponding to the LBU;

B. The LBU judges whether the number recorded in its corresponding sequence reaches the preset threshold for the number of flow control data packets. If so, stop the distribution operation, and then repeat step B, otherwise, repeat the execution Step A;

If the above-mentioned LBU is a non-lowest LBU, then the processing module of the next layer described in the above-mentioned step A is an LBU of the next layer; The processing module is PE.

The LPU corresponding to each LBU and at the same layer as the corresponding LBU in the multi-engine parallel processor performs the following processing steps:

a. After the LPU determines that the record information in the sequence corresponding to the corresponding LBU is non-empty, execute step b;

b. The LPU sequentially reads a tag information from the sequence, obtains the location of the corresponding data packet according to the tag information, opens the output channel corresponding to the location, waits for a complete data packet to pass through, and only allows one data packet to pass through, Then repeat step a until all packets are output.

The following still takes n=2, m ₁ =2, m ₂ =4, P=8 as an example for illustration, see FIG. 1 and FIG. 2 .

When the L1BU distributes the input data packets to the two load channels, it marks the data packets for the first time, and at the same time sequentially writes the marks of the data packets into the sequence S_load ₁₁ . When the number recorded in the sequence S_load ₁₁ reaches the preset data packet flow control threshold of the data input port, that is, when the sequence S_load ₁₁ is full, the L1BU stops distributing data packets, thereby realizing the data input port of the flow control chip.

When the L2BU0 distributes the data packets of the load channel 0 to the four packet processing engines, it marks the data packets for the second time, and at the same time writes the marks of the data packets into the sequence S_load ₂₁ sequentially. When the sequence S_load ₂₁ is full and reaches the flow control threshold of the number of data packets of the load path corresponding to the load path 0, the distribution of data packets is stopped, and the data input of the load path 0 is flow controlled.

When the L2BU1 distributes the data packets of the load channel 1 to the four packet processing engines, it marks the data packets for the second time, and simultaneously writes the marks of the data packets into the sequence S_load ₂₂ sequentially. When the sequence S_load1 ₂₂ is full and reaches the flow control threshold of the number of data packets of the load path corresponding to the load path 1, the distribution of data packets is stopped, and the data input of the load path 1 is flow controlled.

When L2PU0 determines that the information recorded in sequence S_load ₂₁ is not empty, L2PU0 reads the tag information from sequence S_load ₂₁ in order, and obtains the position information of the packet corresponding to the tag by decoding the tag, for example, the tag is 2' b01, indicating that the most recent packet that needs to pass is located in channel 1. L2PU0 opens the channel from engine 1 to load channel 0 in advance, waits for a complete data packet to pass through, and only allows one data packet to pass through, and then opens the next packet to pass through. channel until all packets in the load channel 0 are output through L2PU0.

When L2PU1 determines that the information recorded in sequence S_load ₂₂ is not empty, L2PU1 reads the tag information from sequence S_load ₂₂ in order, and obtains the position information of the packet corresponding to the tag by decoding the tag, for example, the tag is 2' b01, indicating that the most recent packet to be passed is located in channel 1. L2PU1 pre-opens the channel from engine 1 to load channel 1, waits for a complete data packet to pass, and only allows one data packet to pass, and then opens the next packet in turn. channel until all packets in the load channel 1 are output through L2PU1.

When the L1PU judges that the information recorded in the sequence S_load ₁₁ is non-empty, the L1PU reads the tag information from the sequence S_load ₁₁ in order, and obtains the position information of the packet corresponding to the tag by decoding the tag, for example, the tag is 2' b1, indicating that the most recent packet to be passed is located in load channel 1. L1PU pre-opens the channel from load channel 1 to the output port of the chip, waits for a complete data packet to pass, and only allows one data packet to pass, and then opens the next packet in turn. through the channel until all packets in the multi-engine parallel processor are output through the L1PU.

The above sequence S_load ₁₁ , sequence S_load ₂₁ and sequence S_load ₂₂ are respectively carried by a first-in-first-out FIFO buffer.

The above-mentioned embodiments are all described by taking n=2, m ₁ =2, m ₂ =4, and P=8 as examples. In practical applications, the load levels include n=2, 3, 4, 5.. ..., but not limited to the above values; the number of load paths for each layer includes m=2, 3, 4, 5..., but not limited to the above values.

Furthermore, the method for realizing data packet sorting in the multi-engine parallel processor described in the present invention is not only applicable to the multi-engine parallel processor with the structure shown in Fig. 1, for multi-engine processors with other structures, as long as it exists The structure of multi-level and multi-path is also applicable.

The preferred embodiments described in the present invention are not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (11)

1, a kind of method that realizes data packet sequencing in many engines parallel processor, described many engines parallel processor comprises the above load balancing module LBU of one deck, and the corresponding load collection module LPU of each LBU, and this LPU and pairing LBU are in same level, it is characterized in that

In many engines parallel processor, the default sequence that is used for record tag information more than, and each sequence is corresponding one by one with a LBU;

Described LBU carries out following treatment step:

A, LBU receive pending packet, the pending packet delivery that will receive according to default distribution principle is in the processing module of one deck down, and the packet of being distributed carried out mark, indicating this packet place load path, and with this label record with the pairing sequence of this LBU in;

B, this LBU judge whether the number of recorded information in its pairing sequence reaches the default threshold value that is used for Flow Control packet number, if, then stop distribution operation, repeated execution of steps B then, otherwise, repeated execution of steps A;

Described corresponding with each LBU and be in load collection module LPU with layer with pairing LBU, carry out following treatment step:

A, LPU judge whether the number of recorded information in the pairing sequence of LBU corresponding with it is non-NULL, if, execution in step b; Otherwise repeated execution of steps a;

B, LPU order from this sequence reads a label information, obtain corresponding data bag position according to this label information, open the pairing output channel in this position, wait for that a complete packet passes through, and only allow a packet to pass through, repeated execution of steps a finishes until all bag literary composition outputs then.

2, method according to claim 1 is characterized in that,

If described LBU is the LBU of the non-bottom, then the processing module of the described following one deck of steps A is the LBU of following one deck; If described LBU is the LBU of the bottom, then the processing module of the described one deck down of steps A is the civilian processing engine PE of bag.

3, method according to claim 2 is characterized in that, if described load balancing module LBU is top LBU, and the packet number Flow Control threshold value that the described threshold value that is used for Flow Control packet number of step B is a data-in port; If described load balancing module LBU is non-top LBU, the described threshold value that is used for Flow Control packet number of the step B packet number Flow Control threshold value that is load path then.

4, method according to claim 3 is characterized in that, the width B of described sequence _nFor

B _n=[log ₂(m _n)], wherein, 1 rounding operation, m are advanced in [] expression _nLoad path number for following one deck of LBU correspondence;

The degree of depth of the pairing sequence of top LBU is the packet number Flow Control threshold value of data-in port;

The degree of depth of the pairing sequence of non-top LBU is the packet number Flow Control threshold value of the pairing last layer load path of this layer LBU.

5, method according to claim 3 is characterized in that, the packet number Flow Control threshold value determination method of described data-in port is:

At first calculate the size of many engines parallel processor spatial cache, use the length value of the value of this spatial cache size then divided by parcel literary composition, obtain the civilian number of open ended maximum bag, the packet number Flow Control threshold value of wrapping civilian number and predetermined strategy specified data input port again according to this maximum.

6, method according to claim 5, it is characterized in that the method for the size of described many engines of calculating parallel processor spatial cache is: the summation of calculating the spatial cache of all input buffer module ICU and output buffer module OCU in this many engines parallel processor.

7, method according to claim 3 is characterized in that, the packet number Flow Control threshold value determination method of described load path is:

At first calculate the size of all spatial caches in this load path, use the length value of the value of this spatial cache size then divided by parcel literary composition, obtain the civilian number of open ended maximum bag, wrap the packet number Flow Control threshold value that civilian number and predetermined strategy are determined load path according to this maximum again.

8, method according to claim 7 is characterized in that, the method for all spatial cache sizes is in the described computational load path: the summation of calculating the spatial cache of all input buffer module ICU and output buffer module OCU in this load path.

According to claim 5 or 7 described methods, it is characterized in that 9, described predetermined strategy is according to resource overhead and/or to the influence of buffer efficiency, determines the Flow Control threshold value.

10, method according to claim 1 is characterized in that, described sequence is carried by the fifo fifo impact damper.

11, method according to claim 1 is characterized in that, described default distribution principle comprises load balancing strategy or round-robin resolving strategy.

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