CN100346454C - A metallized contact layer structure of silicon based device and method for making same - Google Patents

Abstract

The present invention belongs to the technical skill field of integrated circuit manufacture, and particularly relates to a metallization contact layer structure and a preparation method for metallization contact layers of silicon base devices. The metallization contact layer structure forms a metal silicide layer and a metal layer on a silicon base. The preparation method combines a self alignment metallization technique and a chemical plating technique or a plated metal technique and realizes a full self alignment metallization technique. The present invention has the advantages of good adhesive between the metallization contact layers and silicon, high mechanical strength, good corrosion resistance, simple manufacturing process of the preparation method and low cost. The present invention can be generally applied to integrated circuit manufacturing technique.

Description

A method for preparing a metallized contact layer structure of a silicon-based device

technical field

The invention belongs to the technical field of integrated circuit manufacturing technology, and in particular relates to a method for preparing a metallized contact layer structure of a silicon-based device.

Background technique

A good silicon-based device back metallization contact layer requires good ohmic contact, low contact thermal resistance and good reliability. At present, the structure of the backside metallization contact layer in practical application generally consists of three parts: an ohmic contact layer, a diffusion barrier layer and a conductive layer. The ohmic contact layer requires good adhesion to Si and low ohmic contact resistance, generally using Cr, Ti, etc.; the conductive layer requires stable performance, easy to solder with solder, and good electrical and thermal conductivity, generally using Au, Ag, etc. ; and the diffusion barrier layer is to prevent Au, Ag, etc. from diffusing into the ohmic contact layer to form a high-resistance phase, generally Ni, Pd, etc. are used.

At present, some silicon-based devices such as thyristor tubes and other devices adopt the method of preparing the metallized contact layer, which is to evaporate metal on the back or both sides of the silicon wafer. Generally, three layers of metal are used: Ti-Pd-Ag or Cr-Ni-Ag, etc., and then the metal layer on the oxide layer is removed by double-sided photolithography or grinding, and then soldered on the metal layer to lead out the wires. The disadvantage of this method is that the existing technology uses three layers of metal as the transition layer for welding, but because it is difficult to form a good metal bond between the metals, the phenomenon of delamination and fracture of the metal layer is prone to occur. Moreover, the whole process needs multiple times of double-sided photolithography, and the process is relatively complicated.

Contents of the invention

The object of the present invention is to propose a new structure of a device metallization contact layer with good performance, and propose a preparation method of the metallization contact layer with simple process and low cost.

The structure of the metallized contact layer of the silicon-based device proposed by the invention is that a metal silicide layer is formed on the _SiO2 substrate of the device with a thickness of 10-100nm; a metal layer is also plated on it with a thickness of 100-500nm.

In the metallized contact layer of the above device, the metal silicide includes transition metals (such as Ti, V, Cr, Co, etc.), refractory metals (such as Ni, Pd, Mo, W, Ta, etc.) , near precious metals, etc. As for the metal layer, any material can be used as long as it can be electroless plated or electroplated.

For the new structure of the metallized contact layer of the above device, the present invention proposes a preparation method combining a self-aligned metal silicide process and an electroless plating or electroplating metal process. In this method, no photolithography is required, the process is simple, and the cost is further reduced.

The self-aligned silicide process is a commonly used process in integrated circuits. The process is to deposit metal on the _SiO2 substrate with silicon windows, including transition metals (such as Ti, V, Cr, etc.), 3d , 4d and 5d metals (such as Ni, Pd, Mo, W, Ta, etc.), after thermal annealing, the metal reacts with Si to form silicide, but does not react with SiO ₂ , and then no corrosion occurs on silicon and SiO ₂ After reacting the metal, further annealing can form the desired silicide in the Si region, but no silicide in the _SiO2 region. A low-resistance conductive silicide layer can be formed on the surface of silicon and polysilicon by using the self-alignment process. The whole process does not require photolithography, and the process is very simple. During the formation of self-aligned silicide, the metal and Si react and will "eat" a part of silicon to form silicide, so the adhesion between metal silicide and Si is very good.

The process of electroplating or electroless plating occurs on the surface of the electrical conductor and activated, and after heat treatment, the metal layer can be selectively plated on the surface of the metal silicide instead of the surface of the silicon dioxide. Therefore, the electroplating or electroless plating process is also a self-alignment process without photolithography. Electroplating or electroless nickel plating has fine crystallization, high hardness, uniform coating, good weldability and corrosion resistance. Compared with the common three-layer metal Ti-Pd-Ag metallization process, the electroplated or chemically plated metal and solder have better solderability and higher mechanical strength without affecting the electrical performance of the device.

The invention proposes to plate metal on the metal silicide to realize a fully self-aligned metallization process. The specific operation steps are as follows: a, provide a silicon-based device 1, which has devices on one or both sides, including oxide layer isolation regions and active device regions, or a pure Si substrate; b. Or deposit metal 2 on both sides; c, perform the first annealing, so that the metal reacts with the silicon in the Si device region to form silicide 3, but does not react with the oxide layer; d, removes the metal layer on the oxide layer; e, carry out the second annealing, further react with the silicide, and form a metal silicide with low resistivity; f, remove the oxide layer on the surface of the silicide; g, perform electroplating or electroless metal layer 4; h: on the metal layer Welding, lead wire 5.

In step a, the pattern of the silicon-based device provided is not limited, but there must be a region covered by a dielectric and a region where silicon is exposed, or a region full of Si.

In step b, the type of deposited metal is generally a metal that can form a good low-resistivity silicide with silicon, including transition metals, refractory metals, and near-noble metals, such as: Ti, V, Cr, Ni, Pd, Mo, W, Ta et al. The thickness of the film is between 10nm and 100nm. If it is too thin, it is difficult to form a good quality film, and if it is too thick, it will cause unnecessary waste. Deposition generally adopts physical vapor deposition, and chemical vapor deposition can also be used.

In step C, the selection requirement of the first annealing temperature is to enable the metal to react with Si, but not to react with silicon oxide. Therefore, different metals require different annealing temperatures.

In step D, methods such as dry etching or wet etching can be used to remove the metal layer on the oxide layer.

In step e, the selection requirement of the annealing temperature for the second time is that the silicide can be further reacted to form a silicide with low resistivity, but the thermal stability of the silicide cannot be destroyed; Metals that can form low-resistivity silicides do not need to perform this step.

In step F, the deposited metal material can be any conductor as long as electroless plating and electroplating can be performed.

Description of drawings

Figure 1: Schematic diagram of device graphics on one or both sides.

Figure 2. Schematic after depositing a layer of metal on a graphic sheet.

Figure 3. Schematic of self-aligned silicide formation on Si after annealing and selective etching.

Figure 4. Schematic diagram of electroplating or electroless metal plating where silicide is present.

Numbers in the figure: 1 is a silicon-based device, 2 is a deposited metal layer, 3 is a metal silicide layer, 4 is a metal layer, and 5 is a wire.

Detailed ways

The present invention is further described below by way of examples.

Embodiment 1, electroless metal plating on CoSi ₂

1. Referring to Figure 1, a graphics sheet with devices on both sides (one side is also possible) is provided.

2. Referring to FIG. 2, a refractory metal layer Co is deposited on both sides of the graphic sheet by physical vapor deposition. The thickness of the metal is between 10nm and 100nm. The vacuum chamber should have a good background vacuum. If the vacuum chamber does not have a good vacuum degree, there will be more oxygen in the atmosphere, which will easily cause the oxidation of the film. The preferred vacuum degree is between 10 ^-7 Pa and 10 ^-5 Pa.

3. Referring to FIG. 3, perform the first annealing at a temperature of 500-650° C. to form a cobalt silicide on the pattern sheet. Then use an acidic or alkaline selective etching solution (such as HCl solution with H ₂ O ₂ and H ₂ O), and heat it in a water bath at about 60-90°C for selective etching to corrode unreacted metals, and then use deionized water Rinse for several times, preferably not less than 10 minutes. The second annealing is then carried out at a temperature of 700-950°C. At this time, low-resistivity cobalt disilicide is completely formed on the pattern sheet. This process is a self-alignment process without photolithography.

Then surface treatment is performed on the graphic sheet. After rinsing the graphic sheet with an acidic or alkaline solution (a preferred example is a solution with a ratio of HCl: _{H 2} O ₂ : _{H 2} O=1:2:8), rinse it with deionized water for several minutes, preferably The time is not less than 5 minutes.

4. Then, fully mix the plating solution containing the main salt of Ni ions, reducing agent and complexing agent, (a preferred example is NiSO ₄ : 6H ₂ O: sodium acetate (NaC ₂ H ₃ O ₂ ): lemon sodium hypophosphite (Na ₃ C ₆ H ₆ O ₇ )=25:5:5 mixed with sodium hypophosphite (NaH ₂ PO ₂ :H ₂ O)20, and ammonia water was added to the solution to adjust the pH value between 8 and 11 Place the solution in a water bath at a constant temperature (between 70 and 100° C., a preferred temperature being around 75-85° C.).

Referring to FIG. 4, before electroless plating, the substrate is activated. The activation solution is dilute HF acid (a preferred example is HF:H ₂ O=1:40), and the activation time is about 1 minute to 5 minutes. The purpose of activation is to remove the oxide layer on the surface of the silicide, so that the metal can be plated on the surface of the conductive silicide. If the activation time is too short, the purpose of activation cannot be achieved. If the time is too long, the HF acid will completely corrode the silicide. Then put the activated sheet into the plating solution to carry out the electroless plating process. When bubbles appear on the surface, start to count the time. After about a period of time, take out the slice, wash it with deionized water, and dry it with _N2 gas. The thickness of the coating should be within 100nm to 500nm. If the coating is too thick, it will easily cause the coating to break. At this time, nickel is plated on both sides of the silicon wafer at the same time. Since the nickel plating process is an autocatalytic process that is only carried out in conductive areas, photolithography is still not required for this step. Or self-alignment process.

Embodiment 2, electroless Ni plating on NiSi:

1. With reference to Fig. 1, a metal Ni film is deposited by sputtering on the graphics sheet, with a thickness of 10-100nm.

2. Referring to Figure 2, under the protection of high-purity nitrogen, perform the first step of annealing. The annealing temperature is between 250°C and 500°C, and the time is 10s to 10 minutes. A preferred time is 30s to 2 minutes. Then use an acidic solution such as H ₂ SO ₄ : H ₂ O = 1:1 solution for selective etching to etch away the Si and unreacted metal on the oxide layer for 5-10 minutes. Then rinse with deionized water for several minutes and blow dry with _N2 . If the annealing temperature of the first step is selected below 450°C, a second step of annealing is required, the annealing temperature is from 450°C to 600°C, and the time is from 30S to 5 minutes. If the annealing temperature of the first step is above 450° C., the second annealing step may not be necessary. 3. Then, fully mix the plating solution containing the main salt of Ni ions, reducing agent and complexing agent, (a preferred example is NiSO ₄ : 6H ₂ O: sodium acetate (NaC ₂ H ₃ O ₂ ): lemon sodium hypophosphite (Na ₃ C ₆ H ₆ O ₇ )=25:5:5 mixed with sodium hypophosphite (NaH ₂ PO ₂ :H ₂ O)20, and ammonia water was added to the solution to adjust the pH value between 8 and 11 Place the solution in a water bath at a constant temperature (between 70 and 100° C., a preferred temperature being around 75-85° C.).

Before electroless plating, the sample is cleaned with an acidic solution (a preferred example is a solution of H ₂ SO ₄ : _{H 2} O=1:1). After rinsing with deionized water, activate with an activation solution (a preferred example is HF:H ₂ O = 1:40), and the activation time is about 1 minute to 5 minutes. Then place the activated chip into the plating solution, and start counting when bubbles appear on the surface. After about a period of time, take out the chip, wash it with deionized water, and dry it with _N2 gas. The thickness of the coating should be within 100nm to 500nm. If the coating is too thick, it will easily cause the coating to break. At this time, nickel is plated on both sides of the silicon wafer at the same time. Since the nickel plating process is an autocatalytic process that is only carried out in conductive areas, photolithography is still not required for this step. Therefore, this process step is also a self-alignment process.

Embodiment 3, electroless Ni plating on TiSi ₂

1. Deposit a layer of metal Ti film (thickness between 10-100nm) by sputtering method on the graphic sheet.

2. After the first annealing at 500-650°C, a titanium silicide is formed on the pattern sheet. Then use an acidic or alkaline selective etching solution (such as HCl solution with H ₂ O ₂ and H ₂ O), and heat it in a water bath at about 60-90°C for selective etching to corrode unreacted metals, and then use deionized water Rinse and then for some time, the preferred time is more than 10 minutes. Then go through a second annealing at 700-950°C. At this time, low-resistivity titanium disilicide is completely formed on the pattern sheet. This process is a self-alignment process without photolithography.

3. Then, fully mix the plating solution containing the main salt of Ni ions, reducing agent and complexing agent, (a preferred example is NiSO ₄ : 6H ₂ O: sodium acetate (NaC ₂ H ₃ O ₂ ): lemon sodium hypophosphite (Na ₃ C ₆ H ₆ O ₇ )=25:5:5 mixed with sodium hypophosphite (NaH ₂ PO ₂ :H ₂ O)20, and ammonia water was added to the solution to adjust the pH value between 8 and 11 Place the solution in a water bath at a constant temperature (between 70 and 100° C., a preferred temperature being around 75-85° C.).

3. Before electroless plating, wash the sample with an acidic or alkaline solution (a preferred example is a solution of NH ₄ OH: _{H 2} O ₂ :H ₂ O=1:2:5). After rinsing with deionized water, activate with an activation solution (a preferred example is HF:H ₂ O = 1:40), and the activation time is about 1 minute to 5 minutes. Then place the activated chip into the plating solution, and start counting when bubbles appear on the surface. After about a period of time, take out the chip, wash it with deionized water, and dry it with _N2 gas. The thickness of the coating should be within 100nm to 500nm. If the coating is too thick, it will easily cause the coating to break. At this time, nickel is plated on both sides of the silicon wafer at the same time. Since the nickel plating process is an autocatalytic process that is only carried out in conductive areas, photolithography is still not required for this step. Or self-alignment process.

Embodiment 4, electroless Cu plating on NiSi

1. With reference to FIG. 1, a metal Ni film (about 30nm-100nm) is deposited on the graphic sheet by sputtering.

2. Referring to Figure 2, under the protection of high-purity nitrogen, perform the first step of annealing, the annealing temperature is between 250°C and 500°C, and the time is 10s to 10 minutes, and a preferred time is 30s to 2 minutes. Then use an acidic solution such as H ₂ SO ₄ : H ₂ O = 1:1 solution to carry out selective etching to etch away the Si and unreacted metal on the oxide layer for 5 minutes. Then rinse with deionized water for several minutes and blow dry with _N2 . If the annealing temperature of the first step is selected below 450°C, the second step of annealing is required, the annealing time is from 450°C to 600°C, and the time is from 30S to 5 minutes. If the annealing temperature of the first step is above 450° C., the second annealing step may not be necessary.

3. Then, fully mix the plating solution containing the main salt of Cu ions, reducing agent and complexing agent, (a preferred example is CuSO ₄ : 5H ₂ O: EDTA disodium salt (Na ₂ EDTA): bipyridine (C ₅ H ₄ N) ₂ =15:30:0.1 is mixed with formaldehyde solution, and sodium hydroxide (NaOH) is added to the solution to adjust the pH value between 12 and 13. The solution is placed at a constant temperature (20-50 ℃, a preferred temperature is about 25-35 ℃) in a water bath.

Before electroless plating, the sample is cleaned with an acidic solution (a preferred example is a solution of H ₂ SO ₄ : _{H 2} O=1:1). After rinsing with deionized water, activate with an activation solution (a preferred example is HF:H ₂ O = 1:40), and the activation time is about 1 minute to 5 minutes. Then place the activated chip into the plating solution, and start counting when bubbles appear on the surface. After about a period of time, take out the chip, wash it with deionized water, and dry it with _N2 gas. The thickness of the coating should be within 100nm to 500nm. If the coating is too thick, it will easily cause the coating to break. At this time, Cu is plated on both sides of the silicon wafer at the same time. Since the Cu plating process is a self-catalyzed process, which is only carried out in the conductive area, this step process still does not require photolithography. Therefore, this process step is also a self-alignment process.

Although what provided in above-mentioned embodiment is the example of electroless plating Ni or Cu, for electroless plating other metals, perhaps with electroplating relevant metals, a skilled engineer can complete the method used in the present invention.

Claims (3)

1, a kind of preparation method of metallization contact layer structure of silicon-based devices is characterized in that self-aligned metal silicate technology and chemical plating or plated metal layer process are combined, and the concrete operations step is as follows:

A, provide a silicon-based devices (1), its single face that device is arranged or two-sided device arranged, comprise oxide layer isolated area and active device region;

B, at the single or double depositing metal (2) of this silicon-based devices (1);

C, carry out first time annealing, make the silicon of this metal and silicon-based devices react and form silicide (3), and do not react with the oxide layer isolated area;

Metal on d, the removal oxide layer isolated area;

E, carry out second time annealing, silicide is further reacted, form the metal silicide layer of low-resistivity;

The oxide layer of f, removal suicide surfaces;

G, electroplate or chemical plating metal layer (4);

H, on metal level, weld, draw lead (5);

Wherein, the thickness of described metal silicide layer is 10-100nm, and the thickness of described metal level (4) is 100-500nm.

2, the preparation method of the metallization contact layer structure of silicon-based devices according to claim 1 is characterized in that the metal in the said metal silicide layer is a transition metal, refractory metal, or near noble metal; Described metal layer material is for can carry out chemical plating or electroplated metal.

3, the preparation method of the metallization contact layer structure of silicon-based devices according to claim 1 is characterized in that metal in the said metal silicide layer is a kind of of Ti, V, Cr, Co, Ni, Pd, Mo, W, Ta.

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