CN100346268C

CN100346268C - Dynamic power consumption management method in information safety SoC based on door control clock

Info

Publication number: CN100346268C
Application number: CNB2005100289120A
Authority: CN
Inventors: 曾晓洋; 吴敏; 林一帆; 韩军; 吴永一; 陈俊; 张章; 郭亚炜
Original assignee: Shanghai Weike Integrated Circuit Co Ltd; Fudan University
Current assignee: Shanghai Weike Integrated Circuit Co Ltd; Fudan University
Priority date: 2005-08-18
Filing date: 2005-08-18
Publication date: 2007-10-31
Anticipated expiration: 2025-08-18
Also published as: CN1752894A

Abstract

The invention belongs to the technical field of integrated circuits, and specifically relates to a method for managing dynamic power consumption of an information security SoC. Information security SoC is a calculation-intensive application-specific integrated circuit, mainly controlled by microcontroller MCU, cryptographic operation unit, true random number generator, DMA controller, memory, USB interface controller, bus controller, interrupt controller, and UART Necessary peripherals such as registers and clock management modules. Its working process determines that not every component is involved in the work at the same time. The present invention divides its constituent modules into a plurality of clock regions according to the working process of the information security SoC, and then uses the embedded software of DPM technology to manage the clock supply of each clock region: completely close its clock input for modules not participating in the current work, Turn the clock supply back on when required to engage in work. The dynamic power consumption management technology described in the present invention can greatly reduce the system power consumption of the information security SoC.

Description

Among the information security SoC based on the dynamic power management method of gated clock

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of dynamic power management (Dynamic Power Management, DPM) method that in the digital integrated circuit system, makes things convenient for realization and performance brilliance.

Technical background

Follow the quickening of global IT application paces, network, especially wired, wireless internet network closely link to each other with people's life, become the indispensable carrier of message exchange in the modern society.Informationalizedly deeply also promoted various Network Based, business developments that electronic information is mutual with network universal, the most representative have ecommerce, E-Government, financial payment, intelligent transportation, interaction entertainment or the like.Popularizing of Network brought convenience for people's life, but brought more potential safety hazard also for simultaneously people's life.Today, the information security issue that produces in the network information exchange become to further promote IT application, accelerating network is badly in need of one of key issue that solves in using.

Information security SoC chip develops and becomes the basis of the chip-scale hardware safety of network information security system just rapidly under this background.And because the difference of application, information security SoC chip is also constantly developed on both direction in the world at present: the one, and the information security SoC chip that the curstomer-oriented end is used, as the USB-key that is used for the identity signature and authenticates; Other direction is towards high-end applications, as the high-end information security SoC chip of broadband network application.Though the safety chip of both direction is very different on arithmetic speed and data throughout, be consistent aspect the reduction system power dissipation.The power consumption that the former wishes chip is low as far as possible prolonging the service time of portable battery, and the latter wish the power consumption of chip low as far as possible with guarantee chip for a long time operate as normal with save heat sink (as fan, heat radiator etc.).

According to the CMOS theory, reduce power consumption, the especially dynamic power consumption of cmos circuit, mainly contain following several method: the upset probability that reduces equivalent capacity, reduction supply voltage, reduction frequency of operation and node.Generally speaking, it is very low to reduce this method of equivalent capacity availability in based on the ASIC of standard cell lib design; Reduce supply voltage and reduce these two kinds of methods of frequency of operation and then can have a negative impact the performance of system.And this method of upset probability of reduction node, the load capacitance of node is high more, and this method is just meaningful more.Two nodes of load maximum are exactly clock signal and global reset signal among the ASIC synchronously.And the probability that global reset signal is overturn in system work process very low (general just can overturn when only powering in system or when logic fault occurring), so the upset of control clock signal node is based on the very effective strategy that reduces power consumption among the SoC of CMOS standard block.

DPM can use minimum activating part (activecomponent) to satisfy demands of applications according to system's duty dynamic-configuration systematic parameter of now, and then improves the energy utilization efficiency of system.The DPM technology has important status in the low power dissipation design field, it is the research emphasis of a lot of colleges and universities, as Stanford Univ USA special DPM research group is arranged; Also be the technology that generally adopts in the present last word, as just having used DPM among the Centrino CPU of Intel.

DPM comprises software section and two aspects of hardware components.Software section is mainly analyzed the duty of current system and then the behavior in system future is made prediction; Hardware components is mainly supported the open and close of the clock signal in each clock zone.

Summary of the invention

The objective of the invention is to propose a kind of simple and dynamic power management method that reliability is high, it changes very little to existing hardware module and software module, and influences system performance hardly.

Information security SoC (System-on-Chip, SoC) be the special IC of computation-intensive, mainly by microcontroller MCU (Micro Controller Unit, MCU), the crypto-operation unit, real random number generator, DMA (Direct MemoryAccess, DMA) controller, storer, USB (Universal Serial Bus, USB) interface controller, bus controller and interruptable controller, (Clock Management Module, CMM) etc. necessary peripheral hardware constitutes for UART (Universal Asynchronous Receiver/Transceiver) controller and Clock management module.Its course of work has determined not to be that each parts all participates in work simultaneously.The present invention is divided into a plurality of clocks zone according to the course of work of information security SoC with its composition module, manage the clock supply in each clock zone then with the embedded software of DPM technology: close its clock input fully for the module that does not participate in work at present, when needs participation work, reopen clock and supply with.

The present invention generally requires certain regional module can be independent of some other (being not all) module work when dividing the clock zone; And the software-controllable scope is included in the clock input that will be subdivided into all modules in clock zone in.

Be complementary with above-mentioned embedded management software, the related hardware part of DPM among the information security SoC that the present invention proposes, comprise an above-mentioned software-accessible by Clock management module (Clock Management Module, CMM) and the microcontroller of an above-mentioned software-accessible (Micro Controller Unit, MCU) wrapper constitutes.The former is in charge of the clock of the functional module of other except MCU among the SoC; The latter is in charge of the clock of MCU itself.

The structure of CMM as shown in Figure 1.It comprises:

The control register assembly 1.1 of a CMM, MCU can and revise it by the APB interface accessing, and its value is closed corresponding clock output for ' 0 ' expression, and corresponding clock output is opened in ' 1 ' expression;

The effective latch assembly 1.2 of low level, it has guaranteed to have only the output when clock signal control registers group part 1.1 during for low level just may have influence on final n# clock output, thereby avoided on clock signal, introducing burr effectively, improved the stability of system;

Import and door assembly 1.3 for one two, it is the functional part of closing/opening clock output;

The functional module element 1.4 that rising edge triggers, for example RSA/ECC coprocessor, dma controller, a real random number generator etc.

For CMM, MCU is by rewriting the control register among the CMM, the clock in each clock zone in the On/Off system neatly.When microcontroller is in idle condition according to certain module of work at present status discovery of system, and this is in sky and closes block of state and still need not participation work in ensuing a period of time, and microcontroller can cut out the clock of this module by the state of a control register of revising the Clock management module so; When microcontroller according to system call algorithm or terminal user's request and needs certain when being in the module participation work of clock closed condition (being " hang-up ") to call the clock closed condition in the following text, microcontroller is at first opened the clock that this is in clock closed condition module by the state of a control register of revising the Clock management module, and then continues this module is operated.

The structure of MCU wrapper as shown in Figure 2.It comprises:

The control register assembly 2.1 of a MCU wrapper inside, it can be rewritten by system bus by MCU, and its state value has been controlled the action of finite state thermomechanical components 2.3, and then realize the clock of On/Off MCU;

An ahb bus controller assemblies 2.2, its constantly sample output control signal of MCU, and convert this control signal to meet the ahb bus agreement bus signals, it returns to MCU with operating result simultaneously;

The finite state thermomechanical components 2.3 of a control MCU wrapper operate as normal, its state exchange has reflected the duty of MCU, therefore this finite state thermomechanical components (2.3) can judge when can close/open the clock of MCU and can not cause misoperation, its output signal is directly received the D end of the effective latch assembly 2.4 of low level, and then realizes the Clock management of MCU;

The effective latch assembly 2.4 of low level, its effect are to guarantee just might close clock when the low level of clock, thereby avoid the burr that may occur;

Import and door assembly 2.5 for one two, it is the functional part of closing/opening clock output.

For MCU wrapper, its on the one hand as the bridge circuit that is connected between MCU and the system bus AHB, promptly converts the interface signal sequential of MCU to the AHB interface sequence, again connecting system bus AHB; Also be an AHB equipment on the other hand, MCU can visit or revise the control register of MCU wrapper inside---be used for closing the clock of MCU itself.If embedded software finds that MCU need not to participate in computing or control in a period of time, then can force MCU itself to hang up by the control register of writing among the MCUwrapper; After MCU was suspended, MCU wrapper began to monitor interrupt request singal; When interrupting request signal, MCU wrapper opens the clock of MCU again, makes MCU handling interrupt affairs in time; After interrupting finishing dealing with, thus scheduler program again the current state of inquiry system judge whether to force once more MCU to hang up.

From foregoing description as can be seen, this DPM method that the present invention proposes need not to change any functional module (as RSA/ECC coprocessor, dma controller, USB controller, TRNG or the like), only needs extra CMM of interpolation and slightly modified MCU wrapper to realize.Therefore it is fit to the SoC design based on standard cell lib (standard celllibrary) very much.

The inventive method be among a kind of information security SoC based on the dynamic power management method of gated clock, it can greatly reduce the system power dissipation of information security SoC.

Description of drawings

Fig. 1 is the structure of Clock management module CM M.

Fig. 2 is a MCU wrapper structural drawing.

Fig. 3 is the clock area dividing diagram of information security SoC.

Number in the figure: 1.1 is the control register assembly of CMM, and 1.2 is the effective latch assembly of low level, and 1.3 is two input and door assemblies, and 1.4 is functional module element; 2.1 be the control storage assembly of MCU wrapper inside, 2.2 is the ahb bus controller assemblies, 2.3 is the finite state thermomechanical components, and 2.4 is the effective latch assembly of low level, and 2.5 is two input and door assemblies; 3.1 be microcontroller, 3.2 be the PSA/ECC coprocessor, 3.3 be dma controller, 3.4 is the program storage module, 3.5 is the data-carrier store module, 3.6 be the real random number generator module, 3.7 be the usb interface controller module, 3.8 is universal asynchronous transfer bus controller module, 3.9 is interruptable controller, 3.10 be the Clock management module, 3.11 are the bridge of AHB to APB.

Embodiment

Further describe the present invention below by an object lesson.

1, at first whole information security SoC system divides is become 9 clock zones (as shown in Figure 3) according to the course of work of system.Wherein the clock of 8 shadow regions is software-controllable, and open all the time with the clock of exterior domain in 8 clock zones.Whether the clock that will make a concrete analysis of each parts among the information security SoC below can be included into the scope of management.

Parts 3.1 are core control part and the arithmetic units among the information security SoC: microcontroller (or MCU), and the numerical operation task is finished in it and program storage (ROM) and data-carrier store (SRAM) collaborative work together; Perhaps control other parts and finish the relevant task of information security algorithm.But for some transmission data tasks in enormous quantities, such as the data in the data-carrier store being transported in the data buffer of RSA/ECC coprocessor, the treatment effeciency of MCU can descend rapidly.At this time need dma controller to quicken the transformation task of batch data.And in the process of dma controller work, the only actually of MCU own is waiting for that DMA has carried all data, and therefore during DMA carrying data, MCU can select to close its clock.Given this process, the present invention independently is divided into clock zone 1 (hereinafter to be referred as zone 1) with MCU.Should be noted that MCU wrapper is not put under zone 1, this mainly is to consider that it is a module of finishing the clock control of MCU, and its circuit scale also very little (the power consumption contribution to entire circuit is very little) allows its clock remain the reliability that opening can improve circuit.

Parts 3.2 are core security engines of information security SoC: the RSA/ECC coprocessor, it comprises coprocessor microinstruction storage and coprocessor data-carrier store, can finish signature/verification and encrypt/decrypt task.Because only it just need participate in work when carrying out safe calculation task, the RSA/ECC coprocessor can be comprised that therefore coprocessor microinstruction storage and coprocessor data-carrier store include clock zone 2 (hereinafter to be referred as zone 2) in.

Parts 3.3 are dma controllers, and it is used for quickening the carrying work of batch data.Different with the dma controller on the ordinary meaning is that the work of the dma controller among the present invention is finished by MCU control fully.When scheduler program need to find the carrying batch data, MCU at first told the size of dma controller data source and destination address and data block, and then the work of startup dma controller---dma controller can the application system bus before this.In view of the course of work and the condition of dma controller, the present invention includes dma controller in clock zone 3 (hereinafter to be referred as zone 3).

Parts 3.6 are that (True Random Number Generator, TRNG) module mainly produce the random number that performance is very high at random and use for " safe calculation task " real random number generator.Information security SoC needs the situation of random number to have two kinds: when generating RSA PKI and private key; During the ECC signature.The working method of information security SoC has determined system in a single day to obtain effective random number, and the task of TRNG just declares to be finished thereupon.Therefore the TRNG most of the time all is in " dormancy " state, and the present invention includes it in clock zone 6 (hereinafter to be referred as zone 6).

Parts 3.4 are program storage modules, are used for embedded software---scheduler program, functional module driver and the disposition trace routine of canned data safety SoC; Can also deposit some specific data in addition.Dma controller also can be visited it under some situation, thus it should directly do not included in the zone 1 or the zone 3, and it should be included in separately one independently clock zone 4 (hereinafter to be referred as the zone 4).Zone 4 also comprises the program storage bridge.

Parts 3.5 are data-carrier store modules, and it is actually the primary memory of whole information security SoC, and it can be visited for MCU, also can visit for dma controller.With the program storage module class seemingly, the present invention with its include in independent clock zone 5 (hereinafter to be referred as the zone 5).Zone 5 also comprises the data-carrier store bridge.

Parts 3.7 and parts 3.8 are respectively usb interface controller module and universal asynchronous receiving-transmitting (transmission) (UniversalAsynchronous Receive Transfer, UART) bus controller module, they are two interfaces of communicating by letter with the external world of information security SoC.When scheduler program do not need to find their work, the clock that just can close them.Similarly, the present invention includes them in two independently clock zones respectively: clock zone 7 (hereinafter to be referred as zone 7) and clock zone 8 (hereinafter to be referred as zone 8).

Parts 3.9 are interruptable controllers, because it is bearing the task (summary of the invention has partly been described the process of MCU sleeping/waking) of waking MCU up, add that its circuit scale is very little, so the present invention does not control its clock supply.

Parts 3.10 are Clock management modules of one of key modules of realization DPM, since small, do not control its clock and supply with.

Similarly, the present invention does not control AHB yet and supplies with to APB bridge module 11 clocks.

Secondly 2, the power managed process of scheduler program described

(1) initialization:

When powering on, at first two external interface USB of initialization and UART, initialization miscellaneous part then.Because the function of information security SoC mainly is that the data that the external world transmits are into carried out encrypt/decrypt or signature/verification work, thereby after each module initialization of system finishes, if MCU finds USB and UART and does not receive any data transfer request, then close the clock in other clock zone outside closed region 1 (main control unit MCU), zone 7 and zone 8 (external interface circuit U SB and the UART) earlier, force MCU to enter " dormancy " state by writing control word (being the control register in the MCU bus bridge) then, wait for and interrupt arriving; If MCU finds USB or UART and has received extraneous operational order that then MCU continues its despatching work.

(2) disposition detects:

When the external world require to produce PKI/key to the time, MCU is the clock of opened areas 6 (TRNG) at first, and then forces MCU itself " dormancy ", the interruption of wait TRNG " data buffer is full ".After MCU was waken up by this interruption, MCU began to detect the random number that TRNG generates, if detect satisfactory prime number, the clock that closes closed region 6 is again supplied with, and MCU continues its scheduler task (such as carrying out other calculating again or result of calculation preserved etc.).After whole detection was finished, MCU entered " dormancy " state again, waited for next time interrupting.

(3) signature or checking:

When the external world required to finish signature or validation task, MCU is the clock of opened areas 2 (RSA/ECC coprocessor) at first, then the data buffer of the data transmission that receives from external interface (as USB, UART) to the RSA/ECC coprocessor.If under the hard-core situation of transmission speed, MCU itself just can finish data transfer task; If demanding transmission speed, MCU needs the clock of opened areas 3 (DMA), notify the first address and the data block size of the data block that DMA need carry then, restart DMA and force MCU itself to enter " dormancy " state, wait for the look-at-me that DMA carrying data are finished.After the data carrying was finished, MCU restarted the work of RSA/ECC coprocessor, and then entered " dormancy ", waited for RSA/ECC coprocessor look-at-me.After coprocessor was finished computing, MCU continued its scheduler task.

Claims

1. A dynamic power consumption management method based on a gated clock in an information security SoC, characterized in that the specific steps are as follows:

First, according to the working process of the information security SoC, its constituent modules are divided into the following eight clock areas: area 1 is the microcontroller, area 2 is the RSA/ECC coprocessor, area 3 is the DMA controller, and area 4 is the program memory module, the program memory module stores the embedded software of information security SoC, including scheduler, function module driver and primality detection program; area 5 is the data memory module, area 6 is the true random number generator module, and area 7 is the USB interface The controller module, area 8 is a universal asynchronous transfer bus control module, wherein the modules in a certain clock area work independently of other modules, and the clock inputs of all modules classified into the clock area are included in the software controllable range;

Then the embedded software using DPM technology manages the clock supply of each clock area: for the modules that do not participate in the current work, completely close their clock input, and reopen the clock supply when they need to participate in the work;

Corresponding to the embedded software of the DPM technology, the relevant hardware part of the DPM includes a clock management module accessible by the above software and a microcontroller wrapper accessible by the above software, the former is responsible for managing other functional modules in the SoC except the MCU The clock of the latter is responsible for managing the clock of the MCU itself; here DPM refers to dynamic power management, and MCU refers to the microcontroller.

2. The method according to claim 1, characterized in that the composition of the clock management module includes:

A control register component (1.1), which can be accessed and modified by the microcontroller through the APB interface;

A low-level active latch component (1.2), which ensures that only when the clock signal is low, the output of the control register component (1.1) may affect the final n# clock output;

A two-input AND gate component (1.3), which is a functional part for turning off/on the clock output;

A function module component (1.4) triggered by a rising edge;

When the microcontroller finds that a certain module is idle according to the current working state of the system, and the module in the air-closed state does not need to participate in the work for a period of time, then the microcontroller modifies the control status register of the clock management module to turn off the clock of the module in the air-closed state; when the microcontroller needs a module that is in the clock-off state to participate in the work according to the system scheduling algorithm or the request of the end user, the microcontroller first modifies the control of the clock management module status register to turn on the clock to the module in the clock-off state before continuing to operate the module.

3. The method according to claim 1, wherein the composition of the microcontroller wrapper comprises:

A control register component (2.1) inside the MCU wrapper, which can be rewritten by the MCU through the system bus, and its state value controls the action of the finite state machine component (2.3), and then realizes turning on/off the clock of the MCU;

An AHB bus controller component (2.2), which continuously samples the output control signal of the MCU, converts the control signal into a bus signal conforming to the AHB bus protocol, and returns the operation result to the MCU;

A finite state machine component (2.3) that controls the normal operation of the MCU wrapper, its state transition reflects the working state of the MCU, so the finite state machine component (2.3) can determine when the clock of the MCU can be turned off/on without causing errors Action, one of its output signals is directly connected to the D terminal of the low-level active latch component (2.4), thereby realizing the clock management of the MCU;

A low-level active latch component (2.4), its function is to ensure that the clock is only possible to turn off the clock when the clock is low, thereby avoiding possible glitches;

A two-input AND gate component (2.5), which is a functional part for turning off/on the clock output;

If the embedded software finds that the MCU does not need to participate in the operation or control for a period of time, it will force the MCU to hang up by writing the control register in the MCUwrapper; when the MCU is suspended, the MCU wrapper will start monitoring the interrupt request signal; when the interrupt request signal When it comes, the MCU wrapper restarts the clock of the MCU, so that the MCU can process the interrupt transaction in time; when the interrupt processing is completed, the scheduler will query the current state of the system to determine whether it is necessary to force the MCU to hang up again.

4. The method according to claim 1, characterized in that except for the 8 software-controllable clock regions divided by the information security SoC, the clocks of the remaining interrupt controller modules, clock management modules, and AHB to APB bridge modules are always On, does not control its clock supply;

The process of dynamic power management in information security SoC is as follows:

(1) Initialization:

When powering on, first initialize the two external interfaces USB and UART, and then initialize other modules; after the initialization of each module of the system is completed, if the MCU finds that the USB and UART have not received any data transmission requests, it will first turn off area 1, area 7 and area Clocks in other clock areas other than 8, and then force the MCU to enter the "sleep" state by writing the control word, waiting for the interrupt to arrive; if the MCU finds that the USB or UART has received an external operation command, the MCU continues its scheduling work; here the USB Refers to the USB interface control module, UART refers to the universal asynchronous transfer bus module;

(2) Primality detection:

When the outside world requests to generate a public key/key pair, the MCU first turns on the clock in area 6, and then forces the MCU itself to "sleep", waiting for the TRNG "data buffer is full" interrupt; when the MCU is awakened by this interrupt, the MCU Start to detect the random number generated by TRNG. If a prime number that meets the requirements is detected, then turn off the clock supply in area 6, and the MCU will continue its scheduling tasks; when the entire detection is completed, the MCU will enter the "sleep" state and wait for the next interrupt; here TRNG means True Random Number Generator;

(3) Signature or verification:

When the outside world requests to complete the signature or verification task, the MCU first turns on the clock in area 2, and then transmits the data received from the external interface to the data buffer of the RSA/ECC coprocessor; if the transmission speed is not limited, The MCU itself can complete the data transmission task; if a high transmission speed is required, the MCU needs to turn on the clock in area 3, and then notify the DMA of the first address and the size of the data block to be moved, and then start the DMA and force the MCU itself to enter "sleep" " state, waiting for the interrupt signal of the completion of the DMA transfer of data; after the data transfer is completed, the MCU starts the RSA/ECC coprocessor to work, and then enters "sleep", waiting for the RSA/ECC coprocessor interrupt signal; when the coprocessor completes After the calculation, the MCU continues its scheduling tasks.