CN100340992C - Memory control device for estimating memory power consumption - Google Patents

Abstract

The invention relates to a memory control device capable of estimating memory power consumption, which comprises a control device, a command dispatching device, a plurality of row state machines and a power state and current accumulation device. The power state and current accumulation device control device generates a control signal according to a memory access command transmitted by a system so as to access a synchronous dynamic random access memory; the command dispatch device synchronously receives the control signal from the control device to the synchronous dynamic random access memory; the plurality of row state machines are coupled to the command dispatching device to receive the control signals dispatched by the command dispatching device and judge whether the internal state of the command dispatching device is transferred or not; the power state and current accumulation device judges the state of the synchronous dynamic random access memory according to the states of the plurality of rows of state machines so as to calculate the current consumption of the synchronous dynamic random access memory.

Description

Memory control device for estimating memory power consumption

technical field

The invention relates to a memory control device, in particular to a memory control device capable of estimating memory power consumption.

Background technique

Due to the rapid evolution of semiconductor manufacturing processes, today's embedded system design has entered the so-called System on Chip (SOC) era, which consists of a CPU board, specific-purpose IP and peripheral control devices to form a specific-purpose The system is integrated into a single chip. Fig. 1 is a block diagram of an MPEGII single-chip decoding system, wherein in order to accelerate the execution speed, an On-chip memory 120 module is generally placed on the single-chip system, and there are data cache and instructions in the MIPS module 110 Cache (not shown in the figure), however, the on-chip memory 120, data cache and instruction cache are generally 8Kbyte, 16Kbyte or 32Kbyte due to process limitations.

However, the memory requirements of a general single-chip system are far from being met by the On-chip memory 120. At the same time, due to the limitation of the die area, a large amount of memory cannot be implemented in a single-chip system. Therefore, in order to meet the memory requirements, generally In addition to the MPEGII single-chip decoding system, a synchronous dynamic random access memory 180 is additionally added to allow the MIPS module 110 to store temporary data. However, for this kind of architecture, since the synchronous dynamic random access memory 180 is located outside the single-chip system, its power consumption cannot be estimated. Generally, the average value recorded on the Datasheet of the synchronous dynamic random access memory 180 is used. power to estimate the power consumed by the SDRAM 180 . This method cannot be correctly estimated, so the estimation of the power consumption of the known SDR still has many shortcomings and needs to be improved.

Contents of the invention

The main purpose of the present invention is to provide a memory control device capable of estimating memory power consumption, so as to accurately estimate memory power consumption, and avoid the problem that the known technology can only roughly estimate.

To achieve the above object, the present invention provides a memory control device capable of estimating memory power consumption, which is characterized in that it includes:

A control device generates a control signal according to a memory access command sent by a system to access a synchronous dynamic random access memory;

a command dispatching device, which is synchronously receiving control signals from the control device to the synchronous dynamic random access memory;

A plurality of row state machines, which are coupled to the command dispatching device, to receive the control signal dispatched by the command dispatching device, and to judge whether its internal state should be transferred; and

A power state and current accumulating device, which judges the state of the synchronous dynamic random access memory according to the state of the plurality of row state machines, and queries a current consumption table, and then calculates the current consumption of the synchronous dynamic random access memory .

It also includes a register for storing the current consumption value of the synchronous dynamic random access memory.

Wherein, the temporary register is a current consumption value that is regularly written into the synchronous dynamic random access memory.

Wherein, the synchronous dynamic random access memory is a double-speed data transmission synchronous dynamic random access memory.

Description of drawings

In order to further illustrate the technical content of the present invention, the following detailed description is as follows in conjunction with the embodiments and accompanying drawings, wherein:

FIG. 1 is a block diagram of a known MPEGII single-chip decoding system.

FIG. 2 is an operation diagram of a preferred embodiment of a memory control device capable of estimating memory power consumption according to the present invention.

FIG. 3 is a detailed circuit diagram of the random access memory dynamic power consumption estimation device of the present invention.

FIG. 4 is a state transition diagram of the row A state machine 320 and the row B state machine of the present invention.

Detailed ways

FIG. 2 shows an operation diagram of a preferred embodiment of a memory control device capable of estimating memory power consumption according to the present invention, which includes a memory control device 210, a random access memory dynamic power consumption estimation device 220, and a register bus 230. And a synchronous dynamic random access memory 200 . The synchronous dynamic random access memory 200 can also be a double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR-SDRAM). The memory control device 210 is a general dynamic random access memory control device, which generates a control signal for accessing the synchronous dynamic random access memory 200 .

The random access memory dynamic power consumption estimating device 220 is coupled to the memory control device 210, and monitors the control signal for accessing the synchronous dynamic random access memory 200 sent by the memory control device 210 as an internal combination The driving event of the state machine.

3 is a detailed circuit diagram of the random access memory dynamic power consumption estimating device 220, including a command dispatching device 310, a bank A state machine 320, a bank B state machine 330, and a power state and current accumulating device 340. The command dispatching device 310 synchronously receives the control signal from the memory control device 210 to the SDMA 200, and distributes the control signal to each corresponding memory bank. The access command sent by the memory control device 210 to the synchronous dynamic random access memory 200 includes a command (read/write) and a data length, and the command dispatching device 310 converts the access command into the relevant memory row. command(read/write, length).

The A-row state machine 320 and the B-row state machine 330 judge whether the state should transfer according to the control signal. FIG. That is, when the bank A state machine 320 and the bank B state machine 330 receive the same control signal as the SDR 200 , their states are the same as those of the SDR 200 . The A-row state machine 320 and the B-row state machine 330 output their states to the power state and current accumulation device 340 to determine which state the SDR 200 belongs to.

The power state and current accumulating device 340 searches the current consumption value of the memory row in this state according to the state of the A row state machine 320 and the B row state machine 330 and a built-in current consumption table 341, and adds it by an accumulator 342 Grand total. The accumulated current consumption value will be stored in a temporary register 343 in a certain period of time, and the system solid state (not shown) can read the accumulated current consumption value (previous time interval) through the temporary register bus 230, and the accumulator 342 will When the accumulated value is stored in the temporary register 343, the accumulator 342 is cleared and accumulated again. In this way, the accurate power consumption of the memory can be known.

It can be seen from the above description that the present invention builds the state machine of the simulated dynamic memory into the controller, so that the behavior of the simulated dynamic memory can be synchronized and its state can be known. In this way, the power consumption of the SRAM 200 can be accurately calculated, and the problem that the known technology can only roughly estimate the power consumption of the SRAM 200 can be reversibly avoided.

The above-mentioned embodiments are only examples for convenience of description, and the scope of rights claimed by the present invention should be based on the scope of the patent application, rather than limited to the above-mentioned embodiments.

Claims (4)

1. A memory control device capable of estimating memory power consumption, comprising: A control device generates a control signal according to a memory access command sent by a system to access a synchronous dynamic random access memory; a command dispatching device, which is synchronously receiving control signals from the control device to the synchronous dynamic random access memory; A plurality of row state machines, which are coupled to the command dispatching device, to receive the control signal dispatched by the command dispatching device, and to judge whether its internal state should be transferred; and A power state and current accumulating device, which judges the state of the synchronous dynamic random access memory according to the state of the plurality of row state machines, and queries a current consumption table, and then calculates the current consumption of the synchronous dynamic random access memory . 2. The memory control device capable of estimating memory power consumption as claimed in claim 1, further comprising a temporary register for storing the current consumption value of the synchronous dynamic random access memory. 3 . The memory control device capable of estimating memory power consumption as claimed in claim 2 , wherein the register is a current consumption value that is regularly written into the synchronous dynamic random access memory. 4 . 4. The memory control device capable of estimating memory power consumption as claimed in claim 1, wherein the synchronous dynamic random access memory is a double-speed data transmission synchronous dynamic random access memory.

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