CN100339823C - Program updating method and terminal device - Google Patents

Abstract

When updating the program stored in the rewritable non-volatile memory such as flash ROM, the program part in the block containing the stored program part to be updated in the non-volatile memory is transferred to the RAM, and only the program part to be updated The transfer program part receives instructions from the outside and updates them. Then erase this block in the non-volatile memory, and record the updated part of the program in the RAM to the erased block in the non-volatile memory again.

Description

Program update method and terminal device

technical field

The present invention relates to a method for updating a program stored in a rewritable non-volatile memory such as a flash ROM (flash ROM) in a terminal device, and to such a terminal device.

Background technique

Traditionally, a terminal device stores control software (program) in a rewritable non-volatile memory (such as a flash ROM) to instruct the operation of the CPU, thereby controlling the terminal device.

In this terminal device, a method for updating the control software when a program error (bug) in the control software is found is proposed. For example, JP2001-154838 (page 3-5, Fig. 3) discloses such a method.

In the method disclosed in JP2001-154838, first, new control software with program errors corrected is generated. Then, once the rewritable nonvolatile memory in which program errors are recorded is erased, the new control software is recorded in the memory. The control software is thus updated.

In the update control software method of recording new control software on rewritable nonvolatile memory such as flash ROM as soon as it is erased, under the constraints of nonvolatile memory such as flash ROM, the memory is Divide into multiple blocks, delete the old control software on the basis of only one divided block, and then record the new control software.

Therefore, even when only 1 byte needs to be corrected, if the block of the nonvolatile memory is 16K bytes or 64K bytes, it is necessary to delete the entire 16K bytes or 64K bytes, and then transfer it from outside the device 16K bytes or 64K bytes of new control software whose program errors have been corrected are recorded in the nonvolatile memory, respectively.

Therefore, in updating the control software of the terminal equipment, the amount of data transferred from the outside of the equipment increases, thus causing a problem that the operation time including the time required for data transfer increases.

Contents of the invention

An object of the present invention is to shorten the operating time of a terminal device required for updating a program recorded in the terminal device.

In the present invention, in the process of updating the program recorded in the rewritable non-volatile memory (such as flash ROM), in the RAM, the block containing the part of the program stored in the non-volatile memory needs to be updated The internal program part is expanded, and then according to the external instruction, only the part that needs to be updated in the extended program part is updated. Then, erase the block in the non-volatile memory, and record the updated program part in the RAM to the erased block in the non-volatile memory again.

In this way, by expanding the program part including the part to be updated in the RAM, only the part to be updated in the program part can be updated. In this way, it is only necessary to instruct the parts that need to be updated, instead of instructing to update the information of all program parts. In other words, since the rewrite command transmitted from outside the device can be reduced, the program update operation time including the time required for data transfer can be reduced.

Brief description of the drawings

FIG. 1 is a functional block diagram of a terminal device in a first embodiment of the present invention;

Fig. 2 is a schematic diagram showing an example of a memory map (map) in a terminal device;

Fig. 3 is a flowchart of the processing procedure in the first embodiment;

FIG. 4 is a schematic diagram showing an example of a rewrite command in the first embodiment;

Fig. 5 is a schematic diagram showing another example of the rewrite command in the first embodiment;

6 is a schematic diagram showing an example of a rewrite command in the second embodiment of the present invention;

Fig. 7 is a flowchart of the processing procedure in the second embodiment;

FIG. 8 is a schematic diagram showing an example of a rewrite command in the third embodiment of the present invention;

Fig. 9 is a flowchart of the processing procedure in the third embodiment;

FIG. 10 is a schematic diagram showing another example of a rewrite command in the third embodiment;

FIG. 11 is a schematic diagram showing still another example of a rewrite command in the third embodiment;

FIG. 12 is a schematic diagram showing an example of a rewrite command in the fourth embodiment of the present invention;

Fig. 13 is a flowchart of the processing procedure in the fourth embodiment;

14A is a schematic diagram showing the module structure of the software before correction in the fifth embodiment of the present invention;

Fig. 14B is a schematic diagram of the module structure of the corrected software in the fifth embodiment;

Fig. 15 is a diagram showing an example of a rewrite command in the fifth embodiment;

Fig. 16 is a flowchart of the processing procedure in the fifth embodiment;

FIG. 17 is a diagram showing another example of a rewrite command in the fifth embodiment;

Fig. 18 is a schematic diagram showing still another example of the rewrite command in the fifth embodiment;

Fig. 19 is a schematic diagram showing the module structure after the software is expanded in the RAM in the fifth embodiment;

Fig. 20A is a schematic diagram showing the module structure of the software before correction in the sixth embodiment of the present invention;

Fig. 20B is a schematic diagram showing the corrected module structure of the software in the sixth embodiment;

Fig. 21A is a schematic diagram showing software data in the flash (Flash) ROM before correction in the sixth embodiment;

Fig. 21B is a schematic diagram showing the corrected software data in the flash ROM in the sixth embodiment;

Fig. 22 is a schematic diagram of commands used to control CPU usage in the sixth embodiment;

Fig. 23 is a schematic diagram of an example of a rewrite command in the sixth embodiment;

Fig. 24 is a flowchart of the processing procedure in the sixth embodiment;

Fig. 25 is a schematic diagram showing shift (shift) recording in the sixth embodiment;

Fig. 26 is a schematic diagram showing part of software data in RAM before address rewriting in the sixth embodiment;

Fig. 27 is a schematic diagram showing part of the software data in the RAM after address rewriting is indicated in the sixth embodiment;

Fig. 28 is another diagram showing part of software data in RAM after address rewriting is instructed in the sixth embodiment.

best practice

Embodiments of the present invention will be described below with reference to the accompanying drawings.

(first embodiment)

Fig. 1 shows an example of a block diagram of a terminal device in a first embodiment of the present invention. In FIG. 1, "1" indicates a terminal device.

The terminal device 1 has an external connection interface 11 capable of sending/receiving signals to/from the outside, a control CPU 12 for controlling the terminal device 1, a flash ROM 13 as a rewritable nonvolatile memory, a RAM, and a data bus 15 (through which each function block is connected).

Conceivable as external interface 11 are a cable-wired connection interface and a wireless connection interface. Furthermore, for the external interface 11, a memory card interface can also be used. In this case, the control CPU 12 reads various information from the memory card inserted into the memory card interface.

In addition, when the external interface 11 is a wired connection interface or a wireless connection interface and is connected to a network, data can be input using HTTP, FTP, TFTP, and other transfer protocols. In addition, also when information is input through an external interface such as a wired connection interface, a wireless connection interface, or a memory card interface, the input information is recorded in the RAM 14 or the flash ROM 13 by controlling the CPU 12. Also, in this embodiment, data is recorded by controlling the CPU 12, and when DMA transfer is enabled, copied data can be transferred using DMA.

FIG. 2 shows an example of a memory map in the terminal device 1. As shown in FIG.

2, the storage area 201 of the flash ROM 13 connected to the data bus 15 has hexadecimal notation addresses 00000000 (hereinafter expressed as 0x00000000) to 0x0005FFFF in the storage space controlled by the control CPU 12. In addition, assuming that the storage area 202 of the RAM 14 has 0x00100000 to 0x0015FFFF, the erasing unit of the flash ROM 13 is 64K bytes, namely 0x00000000～0x0000FFFF, 0x00010000～0x0001FFFF...

The operation of the terminal device 1 constructed in the above manner will be described below with reference to the flowchart shown in FIG. 3 .

In step S101, the control CPU 12 of the terminal device 1 reads the rewrite instruction from the external device (not shown in Fig. 1) into the optional area of the RAM 14 through the external connection interface 11 (here, assuming that it is from 0x00100000 in Fig. 2 starting area).

Assume here that the addresses and data to be rewritten in the control software stored in the flash ROM 13 are as shown in FIG. 4 .

Furthermore, by using the address shown in FIG. 4 to designate the rewritten part of the control software, it is not necessary to use actual data to designate the rewritten part, so that the data amount of the rewritten command can be reduced and the program update time can be shortened.

Therefore, in step S102, the control CPU 12 determines the rewrite block in the flash ROM 13. For example, the control CPU 12 checks the rewrite addresses in FIG. 4, and then judges that the rewrite instructions No. 1 to No. 6 designate rewrite in blocks 0x00010000 to 0x0001FFFF in the flash ROM 13.

In step S103, the control CPU 12 expands the rewrite area determined in the step S102 in an optional area (here, assuming 0x00110000 to 0x0011FFFF among Fig. 2 ) of the RAM 14 except that the rewrite instruction area is read in the step S101 data within the block.

Further, in step S104, the control CPU 102 updates the data in the address 0x00110030 in the RAM, in which the data in the address 0x00010030 indicated by the rewrite command No. 1 of FIG. 4 is expanded to 0x43.

In step S105, the control CPU 12 judges whether all rewrite commands on the rewrite block determined in step S102 have been processed. In this case, since the instructions No.2 to No.6 are left, the control CPU 12 enters the process of step S104, and updates the process in the RAM according to the rewriting instructions No.2 to No.6 in the same manner as before. Extended control software.

After completing the processing of the rewriting command No. 6, the control CPU 12 can determine in step S105 that all the rewriting commands on the rewriting block have been processed, and then enter into the processing of step S106.

Next, in step S106, the control CPU 12 erases blocks 0x00010000 to 0x0001FFFF in the flash Rom 13. Then, the control CPU 12 records the update control software stored in the area 0x00110000 to 0x0011FFFF in the RAM 14 into the erased block in the flash ROM 13.

In step S107, the control CPU 12 judges whether all these read rewrite commands have been processed. In this case, since the rewrite command No. 7 remains, the control CPU 12 proceeds to the processing of step S102.

Then, in step S102, the control CPU 12 checks the address of instruction No.7 and subsequent numbers in Fig. rewrite in .

In step S103, the control CPU 12 expands data in blocks of all other areas (assuming 0x00110000 to 0x0011FFFF in FIG. 2 here) of the RAM 14 except the read and rewrite instruction area. In addition, in step S104, the control CPU 12 updates the data in the address 0x00110000 of the RAM 14, wherein the data located in the address 0x00021000 indicated by the rewrite command No. 7 of FIG. 4 is extended to 0x1F.

Thereafter, the control CPU 12 updates the expanded control software in the RAM according to the rewriting instructions No. 8 to No. 10 in the same manner as before. In step S106, the CPU 12 deletes the block in the flash ROM 13. Then, the control CPU 12 records the update control software stored in the area 0x00110000 to 0x0011FFFF of the RAM 14 in the deleted block of the flash ROM 13.

The above process is repeated until it is determined in step S107 that the process of reading the rewriting instruction in the terminal device 1 has been completed.

As described above, according to the first embodiment, by extending the program portion including the portion requiring update in the RAM 14, only the portion requiring update of the program portion can be updated. It is then only necessary to indicate the portion that needs to be updated, without requiring update information indicating to update the entire program portion. In other words, it is possible to reduce the number of rewriting instructions externally transmitted to the terminal device 1 . Therefore, it is possible to shorten the update operation time of the control program stored in the flash ROM 13 including the data transfer time.

In addition, after the update of the program part of the control program in the RAM 14 is completed, the flash ROM 13 can be deleted, and the updated data can be written into the flash ROM 13. In this way, for example, a method can be obtained in which only the part of the control program of the flash RAM 13 that does not need to be changed is stored in the RAM 14, the flash ROM 13 is deleted, and then the updated program part is downloaded to write to the flash ROM 13. In this method, the following situation can be avoided: when the communication is not connected during the process of writing the update program information into the flash ROM 13, not only the write update program fails, but also the original program stored in the flash ROM 13 is also lost. In other words, even if the communication is not connected during the writing of the update program information, the program part before the update can be left in the flash ROM 13, so it can be restored.

Furthermore, according to the first embodiment, a rewrite instruction can be supplied from the outside using the external interface 11, so it is not necessary to remove the flash ROM 13 to update the program, and a program update with shortened update operation time can be realized.

In addition, the storage space shown in FIG. 2 may vary according to the type or structure of the control CPU 12, flash ROM 13 and/or RAM 14 or the amount of data provided in the terminal device 1.

In addition, although the flash ROM 13 is used in this embodiment, as long as the memory is a rewritable nonvolatile memory, a memory such as EEPROM can also be used.

In addition, the update unit of the control software in this embodiment is 64 kilobytes, but it does not need to be 64 kilobytes, depending on the erasing area depending on the type of nonvolatile memory (such as flash ROM 13) device Block size is determined. Moreover, although this embodiment has described 1 byte as the number of rewriting bytes, the rewriting data need not be 1 byte, for example, it is also possible to simultaneously rewrite the amount of data designated by an optional address designation method such as 2 bytes and 4 bytes.

In Fig. 4, the target rewriting address in the flash ROM 13 is indicated with an absolute address. However, as shown in FIG. 5, only the first address may be indicated by an absolute address with respect to subsequent addresses indicated by a relative value of the address used immediately before. For example, in the example shown in FIG. 5, the rewrite address indicated by the rewrite command No. 2 indicates the address 0x1 located after the rewrite address indicated by the command No. 1.

In this way, rewriting can be indicated with a relative address whose data volume is smaller than that of an absolute address, thereby reducing the data volume of a rewriting command.

(second embodiment)

A terminal device according to a second embodiment of the present invention will be described below.

An example of a functional block diagram and an example of a memory map of a terminal device according to the second embodiment of the present invention are respectively the same as those of the terminal device in the first embodiment, and thus are also the same as those shown in FIGS. 1 and 2 .

In the first embodiment, the rewrite command is composed of a combination of rewrite target address 401 and rewrite data 402 in the nonvolatile memory shown in FIG. 4 . In the second embodiment, as shown in FIG. 6, the rewrite command is composed of a combination of a rewrite instruction command 501 and data 501 and 502 for executing the command. In this way, effects like those in the first embodiment can also be obtained.

For example, the rewrite instruction No. 1 in FIG. 6 is an instruction for expanding in the RAM 14. When the control CPU 12 receives the rewriting instruction No. 1, it uses data 1 as the extension source address 504, and uses data 2 as the extension destination address 505 to extend the program from the flash ROM 13 to the RAM 14.

In addition, rewrite command No. 8 in FIG. 6 is a command to write back to the flash ROM 13. The control CPU 12 that has received the rewrite command No. 8 deletes the block starting from the data 2 behind the rewrite command in the flash ROM 13, then uses the data 1 as the extended source address 506, and uses the data 2 as the recording target address 507 , the program in the RAM 14 is stored in the flash ROM 13.

Rewrite commands No. 2 to No. 7 and No. 10 to No. 13 are data rewrite commands. When the control CPU 12 receives the data rewriting instruction, it uses data 1 as the rewriting target address 508 and data 2 as the actual rewriting data 509 to rewrite the data in the RAM.

The following description gives the operation when the instruction shown in FIG. 6 is rewritten with reference to the flowchart shown in FIG. 7 .

First, in step S110, when the instruction shown in Figure 6 is provided as the rewriting instruction of the program stored in the flash ROM 13, the control CPU 12 reads the rewriting instruction No.1 shown in Figure 6 through the external connection interface 11, And store it in the optional area of RAM 14.

In step S111, the control CPU 12 checks whether command No. 1 is a rewriting termination command. Because this instruction No.1 is not rewriting termination instruction, control CPU 12 and proceed to the processing procedure of step S112.

In step S112, the control CPU 12 checks whether instruction No. 1 is an instruction for expansion in the RAM 14. Because instruction No.1 is the instruction that is used for expanding in RAM 14, control CPU 12 goes over to the processing procedure of step S115.

In step S115, the control CPU 12 expands the block from 0x00010000 in the flash ROM 13, that is, the data from 0x00010000 to 0x0001FFFF in the second embodiment, in the RAM 14 from 0x00110000 to 0x0011FFFF according to the data behind the instruction . Then, the control CPU 12 proceeds to the processing of step S110.

Next, in step S110, the control CPU 12 reads command No. 2. The control CPU 12 checks the command content of the read command No. 2 as in the command No. 1 in steps S111 and S112. However, instruction No. 2 does not match the branch conditions of steps S111 and S112. Therefore, the control CPU 12 proceeds to the processing of step S113.

In step S113, the control CPU 13 judges that command No. 2 is a data rewriting command, and therefore, proceeds to the process of step S116.

In step S116, the control CPU 12 rewrites the data stored in addresses 0x00110030 to 0x43 according to the data behind the instruction.

Then, the control CPU 12 repeats the same process as before until command No. 7, and then reads command No. 8 in step S110. The control CPU 12 checks the instruction content in steps S111 to S113 in the same manner as the foregoing procedure, and then proceeds to the processing procedure of step S114.

In step S114, the control CPU 12 judges that instruction No. 8 is an instruction to write back to the flash ROM 13, and then proceeds to the processing of step S117.

In step S117, according to the data behind the instruction, the control CPU 12 transfers to the process of recording the expanded program in the RAM 14 into blocks 0x00010000 to 0x0001FFFF. First, the control CPU 12 deletes blocks 0x00010000 to 0x0001FFFF in the ROM 13 at a time. Then, the control CPU 12 records the contents of the blocks 0x00010000 to 0x0001FFFF of the RAM 14 into the blocks 0x00010000 to 0x0001FFFF of the flash ROM 13.

Then, the control CPU 12 executes the aforementioned process for all the rewriting instructions provided in FIG. 6 .

As mentioned above, according to the second embodiment, only the data to be updated in the control software stored in the flash ROM 13 in the terminal device 1 can be read into the terminal device 1. This can shorten the time for updating the software recorded in the flash ROM 13 in the terminal device 1.

In addition, in the second embodiment, the rewrite command exemplified in FIG. 6 can be supplied through the external interface 11 shown in FIG. 1 , and furthermore, the content of the command can be sequentially supplied for executing the program process. Have again, also can provide the instruction that will be stored in the RAM 14 of terminal equipment 1 together, so that the rewriting process is carried out according to the instruction stored.

Furthermore, in the foregoing description, each process of checking the contents of the read command may be performed in the order of steps S111, S112, S113, and S114 in FIG. 7, but the same effect can be obtained even if the order is optionally changed.

(third embodiment)

In the first embodiment, the recommand is constituted by a combination of the rewrite target address 401 and rewrite data 402 shown in FIG. 4 in the flash ROM 13 (which is a nonvolatile memory). In the third embodiment, as shown in FIG. 8 , the rewrite command is composed of a rewrite start address 801 , a rewrite data item number 802 , and actual rewrite data 803 corresponding to the rewrite data item number 802 . In this way, the same effect as that of the first embodiment can be obtained.

In addition, an example of a functional block diagram and an example of a memory map of a terminal device according to the third embodiment of the present invention are the same as those of the first embodiment shown in FIGS. 1 and 2, respectively.

The operation of the terminal device 1 when supplied with the rewriting instruction shown in FIG. 8 will be described below with reference to the flowchart shown in FIG. 9 .

In step S121, when the instruction shown in FIG. 8 is provided to the terminal device 1 as the rewriting instruction of the program stored in the flash ROM13, the control CPU 12 reads the rewriting instruction shown in FIG. 8 through the external connection interface 11. (Here, assume that this area starts from 0x00100000 in Figure 2).

In step S122, the control CPU 12 checks the rewriting start address in FIG. 8, and determines that the rewriting instructions No. 1 and No. 2 indicate rewriting in blocks 0x00010000 to 0x0001FFFF in the flash ROM 13.

Next, in step S123, the control CPU 12 expands the data in the block determined in step S122 in an optional area (here, assume 0x00110000 to 0x0011FFFF) other than the area in which the rewrite command has been read.

In addition, in step S124, control CPU 12 determines that the address 0x00010030 in RAM 14 to 0x00110030 in flash ROM 13 has been extended according to rewriting instruction No.1 among Fig. The number is 0x04.

In step S125, the control CPU 12 changes the contents of addresses 0x00110030 to 0x43 according to the rewriting data of instruction No.1 in FIG. 8 .

Next, in step S126, the control CPU 12 adds 1 to the rewrite address to become 0x00110031. In step S127, the control CPU 12 decrements the number of rewritten data items by 1 to become 0x03. In step S128, the control CPU 12 checks whether the number of rewritten data items is 0, and when the number is not 0, it proceeds to the processing of step S125.

Then, the control CPU 12 repeats the above-described processing of steps S125 to S128 until the number of rewrite data items becomes zero.

When the number of rewriting data items becomes 0, the control CPU 12 judges in step S129 whether all the rewriting instructions to the rewriting blocks determined in step S122 have been processed. When the rewrite command on the block has not been processed, the control CPU 12 proceeds to the processing of step S124, and then repeats the processing of steps S124 to S129 until all rewrite commands on the block have been processed.

At the same time, after all the rewrite commands on the rewrite block are all processed, the control CPU 12 deletes the block determined in the step S122 in the flash ROM 13 in step S130. Then, the control CPU 12 records the new control software stored in the area 0x00110000 to 0x0011FFFF in the RAM 14 into the deleted block of the flash ROM 13.

Next, the control CPU 12 judges in step S131 whether or not the processing of the rewrite command illustrated in FIG. 8 has been completed. When the processing is not completed, the control CPU proceeds to the processing of step S122.

Then, the control CPU 12 repeats the processing of the above-mentioned steps S122 to S131 until the processing of all rewriting instructions is completed.

As described above, according to the third embodiment, in the control software stored in the flash ROM 13 of the terminal device 1, only the data that needs to be updated in the terminal device 1 can be read and updated.

In the third embodiment, as shown in FIG. 8 , the rewrite instruction is composed of a combination of a rewrite start address 801 , a number of rewrite data items 802 and actual rewrite data 803 . Furthermore, as shown in FIG. 10 , the rewrite command may be composed of a rewrite start address 1001 , a rewrite end address 1002 , and actual rewrite data 1003 . In this case, for example, as shown in FIG. 10, by comparing the rewriting start address 0x00010030 with the rewriting end address 0x00010033, the number of rewriting data items is derived as 0x04. Therefore, the same effect as that of the rewrite command shown in FIG. 8 can also be obtained with the rewrite command shown in FIG. 10 .

Therefore, in the third embodiment, as shown in FIG. 8 , the rewrite command is composed of a rewrite start address 801 , the number of rewrite data items 802 and actual rewrite data 803 . In addition, as shown in FIG. 11, the rewrite command may be composed of a rewrite start address 1101, actual rewrite data 1102, and specific data 1103 indicating the end of rewrite. In this case, for example, in the rewriting instruction No.1 of FIG. 11 , the data in the address 0x00110030 in the RAM 14 (wherein, the program on the rewriting start address 0x00010030 is expanded) is updated to 0x43. In addition, update the data at address 0x00110031 to 0xBF, update the data at address 0x00110032 to 0x00, and update the data at 0x00110033 to 0x10.

Therefore, since the data following 0x10 is dedicated data indicating the end of rewriting, it can be determined that the next data following this specific data is the next rewriting start address. In this way, the rewrite command shown in FIG. 11 can achieve the same effect as the rewrite command shown in FIG. 8 by repeating the above-described process.

Also, in the third embodiment, the rewrite address is incremented by 1 in step S126, and then the number of rewrite data items is decremented by 1 in step S127. However, the same effect can also be obtained by first decrementing the number of rewriting data items by 1 and then adding 1 to the rewriting address.

(fourth embodiment)

In the third embodiment, as shown in FIG. 8 , the rewrite command may be composed of a rewrite start address 801 in the nonvolatile memory, a rewrite data item number 802 and actual rewrite data 803 . In the fourth embodiment, as shown in FIG. 12, a command is composed of a command 1201 including a rewrite command command and data 1202 for executing the command. In this way, the same effects as those of the third embodiment can be obtained.

In addition, an example of a functional block diagram and an example of a memory map of a terminal device according to a fourth embodiment of the present invention are the same as those of the first embodiment shown in FIGS. 1 and 2, respectively.

The operation when the rewrite instruction shown in FIG. 12 is supplied will be described below with reference to the flowchart shown in FIG. 13 .

In addition, in the operation of the rewrite command in FIG. 12, expansion in RAM and writing back to ROM are the same as in the second embodiment. In addition, this rewriting means writing to the address indicated by the data following the instruction with subsequent actual data corresponding to the number of data items indicated by the data following the address.

In step S141, when the instruction shown in FIG. 12 is supplied as a rewrite instruction on the program stored in the flash ROM 13, the control CPU 12 reads instruction No. 1.

Next, in step S142, the control CPU 12 checks whether the read command is a rewrite termination command. When the instruction is not a rewriting termination instruction, the control CPU 12 enters the process of step S143.

In step S143, the control CPU 12 checks whether the read instruction is an extended instruction in the RAM 14. When the instruction is an extended instruction in the RAM 14, the control CPU 12 enters the processing of step S144, and when the instruction is not an extended instruction in the RAM 14, it enters the processing of step S145.

In step S144, when the read command is command No. 1 in FIG. 12, the command is an extended command in the RAM 14. Therefore, the control CPU 12 expands the data at the addresses 0x00010000 to 0x0001FFFF in the flash ROM 13 at the addresses 0x00110000 to 0x0001FFFF in the RAM 14. Then, the control CPU 12 proceeds to the processing of step S141.

When the read command is command No. 2 in FIG. 12, the control CPU 12 reads the command in step S141. Then, the control CPU 12 proceeds to the processing of S145 through the processing of steps S142 to S143.

In step S145, the control CPU 12 checks whether the read command is a data rewrite command. When the read command is a data rewrite command, the control CPU 12 proceeds to the processing of step S146. Meanwhile, when the read command is not a data rewrite command, the control CPU 12 proceeds to the processing of step S151.

Command No. 12 in FIG. 12 is a data rewrite command. Therefore, the control CPU 12 proceeds to the processing of step S146.

In step S146, the control CPU 12 determines that the address 0x00110030 in the RAM 14 is the rewrite start address according to instruction No. 2 in FIG. 12, and the number of rewrite data items is 0x04.

Then, in step S147, the control CPU 12 changes the content of address 0x00110030 to 0x43 according to the rewriting data of instruction No.2 in FIG. 12 . Then the control CPU 12 adds 1 to the rewrite address in step S148 to become 0x00110031.

In step S149, the control CPU 12 decrements the number of rewritten data items by 1 to 0x03.

In step S150, the control CPU 12 checks whether the number of rewritten data items is 0, and when the data is not 0, enters the processing procedure of step S147.

Then, the control CPU 12 repeats the above-mentioned processing of steps S147 to S150 until the number of rewritten data items becomes zero. When the number of rewritten data items is 0, the control CPU 12 enters the process of S141.

In the case of command No. 4 in FIG. 12, the control CPU 12 reads the command in step S141. Then control CPU 12 enters the processing procedure of S151 by the processing procedure of steps S142, S143 and S145. Then, in step S151, control CPU 12 checks whether this read instruction is the instruction of writing back flash ROM 13, when this instruction is the instruction of writing back flash ROM 13, it enters the processing procedure of step S152, and when this instruction When the instruction is not an instruction to write back to the flash ROM 13, it enters the processing procedure of S141.

Instruction No. 4 among Fig. 12 is the instruction of writing back to flash ROM 13. Therefore, the control CPU 12 proceeds to the processing of step S152.

In step S152, the control CPU 12 erases the block in the flash ROM 13 indicated by the read command written back to the ROM, that is, 0x00010000 to 0x0001FFFF in the case of command No. 4 exemplarily shown in FIG. 12 . Next, the control CPU 12 records the new control software stored in 0x00110000 to 0x0011FFFF of the RAM 14 in the erased block of the flash ROM 13. Then, the control CPU 12 proceeds to the processing of step S141.

The control CPU 12 repeats the foregoing processing until it is determined in step S142 that the command read in step S141 is a rewriting termination command.

As described above, according to the fourth embodiment, of the control software stored in the flash ROM 13 of the terminal device 1, only data that needs to be updated can be read into the terminal device 1.

In addition, in the fourth embodiment, the rewriting command exemplified in FIG. 12 can be supplied through the external interface 11 shown in FIG. 1, and further, the content of the command for executing the rewriting process can be sequentially supplied. In addition, instructions stored in the RAM 14 can be given to the terminal together so that rewriting processing can be performed in accordance with the stored instructions.

Furthermore, the fourth embodiment described the case where the determination processing of the instruction content read in step S141 is performed in the order of steps S142, S143, S145, and S151, but the determination order may be optionally exchanged.

Also, in the fourth embodiment, the rewrite address is incremented by 1 in step S148, and then the number of rewrite data items is decremented by 1 in step S149. However, the same effect can also be obtained by first reducing the number of rewriting data items by 1, and then adding 1 to the rewriting address.

(fifth embodiment)

14A and 14B show the block structure of the program in the fifth embodiment of the present invention, FIG. 14A shows the structure before the program error is corrected, and FIG. 14B shows the structure after the program error is corrected.

In other words, the program shown in FIG. 14A is composed of three modules, namely module A1401, module B1402 and module C1403. In the program shown in FIG. 14A , that is, the program before correction, module A is located at 0x00000000 to 0x000001FF, module B is located at 0x00000200 to 0x0000021F, and module C is located at 0x00000220 to 0x000005FF.

In addition, in the program shown in FIG. 14B, as a result of the correction of the program in FIG. 14A, the block B1402 is changed, which is located at 0x00000200 to 0x0000022F, and becomes the block B'1404. Module A is unchanged from that in Figure 14A. The content of module C is unchanged, but its bits are shifted from 0x00000230 to 0x0000060F.

It is assumed that an example of a functional block diagram and an example of a memory map diagram of the terminal device 1 in the fifth embodiment of the present invention are the same as those shown in FIGS. 1 and 2, respectively.

On the premise that the program in FIG. 14A is stored in the flash ROM 13, a method for updating the program in FIG. 14A to the program in FIG. 114B in the terminal device 1 will be described below. Here, the operation when the terminal device 1 receives the rewriting instruction shown in FIG. 15 will be described with reference to the flowchart shown in FIG. 16 .

In addition, when the instruction 1501 in Fig. 15 is an extension instruction in the RAM 14, the data 1502 behind the instruction 1501 is the start address 1503 of the extension source, and the data after the start address 1503 of the extension source is the end address 1504 of the extension source , and the data following the end address 1504 of the extension source is the extension destination address 1505 . Afterwards, the control CPU 12 expands the data of the flash ROM 13 into the RAM 14 using these data.

Thereby, extension data can be specified using address information instead of actual data. Thereby, the data amount of the rewrite command can be reduced, and the program update operation time including the data transfer time can be shortened.

Writing back the ROM 13 is the same as the operation described in the second embodiment of the present invention, and rewriting is the same as the operation described in the fourth embodiment of the present invention.

In step S161, when the instruction 1501 shown in FIG. 15 is supplied through the external connection interface 11 as a rewriting instruction of the program stored in the flash ROM 13, the control CPU 12 reads instruction No. 1.

Next, in step S162, the control CPU 12 checks whether the read command is a rewrite termination command. When the instruction is not a rewriting termination instruction, the control CPU 12 enters the process of step S163.

In step S163, the control CPU 12 checks whether the read command is an extended command in the RAM 14. Because the instruction is an extended instruction in the RAM 14, the control CPU 12 enters the processing of step S166. When the read instruction is not an extended instruction in the RAM 14, the control CPU enters the processing of step S164.

Instruction No.1 in FIG. 15 is an extended instruction in RAM 14. Therefore, in step S166, the control CPU 12 determines that the starting address of the extension source is 0x00000000 in the flash ROM 13 according to the data of the instruction No. 1, the end address is 0x000001FF, and the extension destination address is 0x00110000 in the RAM 14.

Next, in step S167, the control CPU 12 expands the data of the flash ROM 13 into the RAM 14 according to the address determined in step S166.

In the case of instruction No.1 shown as an example in FIG. 15, the data on 0x00000000 to 0x000001FF in the flash ROM 13, that is, the module A1401 in FIG.

Next, the control CPU 12 proceeds to the processing of step S161.

Command No. 2 in FIG. 15 is a command expanded in RAM, and is the same as command No. 1. Therefore, the control CPU 12 expands the data from the flash ROM 13 to the RAM 14 according to the same processing procedure as the instruction No.1.

In this way, module C1403 in Figure 14A is extended at 0x00110230 to 0x0011060F of RAM 14.

Then, in the case of command No. 3 in FIG. 15, the control CPU 12 reads the command in step S161, and then proceeds to the process of step S164 via the processes of steps S162 and S163.

In step S164, the control CPU 12 checks whether the read command is a data rewrite command. When the read instruction is a data rewrite instruction, the control CPU 12 enters the processing of step S170. Meanwhile, when the read command is not a data rewrite command, the control CPU 12 proceeds to the processing of step S165.

Command No. 3 in FIG. 15 is a data rewrite command. Therefore, the control CPU 12 proceeds to the processing of step S170. In step S170, the control CPU 12 determines that the address 0x00110200 in the RAM 14 is the rewrite start address according to the rewrite instruction No. 3 in FIG. 15, and the number of rewrite data items is 0x30.

Next, in step S171, the control CPU 12 changes the content of the address 0x00110200 according to the rewriting data instruction of No. 3 in FIG. 15 .

Then, in step S172, the control CPU 12 adds 1 to the rewrite address to become 0x00110201. Next, in step S173, the control CPU 12 decrements the number of rewrite data items by 1 to 0x2F.

In step S174, the controlling CPU 12 checks whether the number of rewritten data items is 0, and when the number is not 0, it proceeds to the processing of step S171.

Then, the control CPU 12 repeats the above-described processing of steps S171 to S174 until the number of rewritten data items becomes zero. When the number of rewritten data items becomes 0, the control CPU 12 proceeds to the processing of S161.

Assuming that the follow-up data corresponding to 0x03 provided by instruction No. 3 is the module B'1403 in Fig. 14B, when the number of rewriting data items is determined to be 0 in step S174, on 0x00110200 to 0x0011022F of RAM 14 Module B'1404 is extended.

As mentioned above, in RAM 14, the program shown in Figure 19 begins to expand by address 0x00110000.

It should be noted that since module B becomes module B' due to the update, and the capacity increases, the position of module C is shifted backward by the capacity difference between module B and module B'. In other words, the module C is shifted when expanding in the RAM 14 so that the relative value between the positions of the update target module B and the following module C stored in the flash ROM 13 increases.

In this way, even when module B becomes module B' due to renewal and capacity increase, overlapping of module B' and module C can be avoided.

In addition, when there is an amount of program code (including direct data) of the rewriting part (module B), a part of the code (module C) can be shifted without rewriting, and thus can be shifted without rewriting the part (module B') Rewrite the program with the information of the subsequent code (module C). Therefore, rewriting instructions transmitted from the outside of the terminal device 1 can be reduced. In other words, the module C can be shifted with a smaller amount of data. As a result, the update operation time of the program including the data transfer time can be shortened.

Next, in the case of command No. 4 in FIG. 15, after the control CPU 12 has read the command in step S161, it proceeds to the processing of step S165 through steps S162, S163 and S164.

In step S165, the control CPU 12 judges whether the read command is a write-back command in the ROM, and when the read command is a write-back command in the ROM, it enters the process of step S168.

When the read instruction is not a ROM write-back instruction, the control CPU 12 enters the processing of step S161.

Command No. 4 in FIG. 15 is a ROM write-back command. Therefore, the control CPU 12 proceeds to the processing of step S168.

In step S168, in the case of instruction No.4 shown in Figure 15, the control CPU 12 determines the new control software address 0x00110000 to 0x0011FFFF stored in the RAM 14 according to the read ROM write-back instruction, and the flash ROM 13 write-back blocks, namely 0x00000000 to 0x0000FFFF.

Next, in step S169, the control CPU 12 deletes the blocks 0x00000000 to 0x0000FFFF of the flash ROM 13 determined in step S168. Then, the control CPU 12 records the new control software stored in the RAM 14 at 0x00110000 to 0x0011FFFF in the deleted block of the flash ROM 13.

Control CPU 12 enters the processing procedure of step S161.

Then, the control CPU 12 sequentially repeats the aforementioned processing until the command read in step S161 is judged as a rewriting termination command in step S162.

As described above, according to the fifth embodiment, the control software stored in the flash ROM 13 in the terminal can be updated without downloading the entire correction program shown in FIG. 14 . As a result, shortening of software update time is realized due to reduction of rewriting instructions.

In addition, according to the fifth embodiment, when the capacity of the module B is increased due to updating, the module C can be shifted during the expansion of the RAM 14 to increase the module B and the update target stored in the flash ROM 13. The relative value between the position of the following module C. Thus, it is possible to reduce rewrite instructions transmitted from outside the device. As a result, the rewrite update operation time including the data transfer time can be shortened.

In addition, although the fifth embodiment describes the case where the program is composed of three modules, the number of modules and the module capacity are not limited to those described above.

In addition, although the "RAM extension" in FIG. 15 is composed of the start address 1503 and the end address 1504 in the flash ROM 13 as the extension source, and the start address 1505 in the RAM as the extension destination, as shown in FIG. 17 , the same effect can also be obtained by combining the start address 1703 of the extension source, the number of subsequent extension data items 1704, and the start address 1705 in the RAM as the extension destination.

In addition, in FIG. 15, the area in which the program in the flash ROM 13 is expanded in the RAM 14 is designated by an absolute address. However, since the area in the RAM 14 is used only as an operation area, the control CPU 13 in the terminal device 1 can set an optional area in the RAM 14.

In this case, in the RAM 14, it is possible to use the shift value from the start address of the optional area to specify the address when expanding or to rewrite the RAM 14 during the specified process. In other words, in the rewrite instruction shown in FIG. 18, "extension of the RAM 14" consists of the start address 1803 in the flash ROM 13 as the extension source, the number of expansion data items 1804, and the relationship with the start address of the optional area. The shift value 1805 is combined.

For example, instruction No. 2 indicates that in the start address of the optional area plus 0x00000230, the subsequent data corresponding to 0x3E0 starting from address 0x00000220 in the flash ROM 13 is expanded.

In addition, "rewrite" is composed of a shift value 1806 relative to the start address in the optional area, the number of rewrite data items 1807, and actual rewrite data 1808 corresponding to the number of data items. For example, in instruction No.3, the data corresponding to 0x30 is rewritten from the start address of the optional area plus the address of 0x0000200.

The command to write back the ROM 13 instructs to write back based on the deleted block of the flash ROM 13. Therefore, this instruction only instructs to write back the header of the block. For example, in instruction No.4, 0x00000000 is indicated as the header of the write-back block, after deleting the block 0x00000000 to 0x0000FFFF of the memory map shown in Figure 2, the header in the RAM optional area The area to which the head of the optional area is added with 0x0000FFFF is written back to the flash ROM 13.

In addition, the fifth embodiment described the case where determination processing is performed on the instruction content read in step S161 in the order of steps S162, S163, S164, and S165, but the determination order may also be changed in an optional manner.

In addition, in the fifth embodiment, the rewrite address is incremented by 1 in step S172, and then the number of rewrite data items is decremented by 1 in step S173. However, the same effect can also be obtained by first reducing the number of rewriting data items by 1, and then adding 1 to the rewriting address.

(sixth embodiment)

20A and 20B show the block structure of the program in the sixth embodiment of the present invention, FIG. 20A shows the structure before the program error is corrected, and FIG. 20B shows the structure after the program error is corrected.

In other words, the program shown in FIG. 20A is composed of three modules, namely module A2001, module B2002 and module C2003. Module A is located at 0x00000000 to 0x000001FF, module B is located at 0x00000200 to 0x0000021F, and module C is located at 0x00000220 to 0x000005FF.

In the program shown in FIG. 20B, module A2001 is changed as a result of correction of the program shown in FIG. 20A.

Specifically, module A2001 becomes module A'2004 at 0x000001FF. Module B2002 becomes module B'2005 at 0x00000200 to 0x0000022F. The content of module C is unchanged, but its location is moved from 0x00000230 to 0x0000060F.

Fig. 21A shows a part of module A2001 whose program error has not been corrected, and Fig. 21B shows a part of module A'2001 whose program error has been corrected.

FIG. 22 shows an example of a branch command of the control CPU 12 of the terminal device 1 in the sixth embodiment.

The operation code 2201 prepares to branch the operand 2202 following the operation code 2201 as an address.

Specifically, opcode 0xEA prepares to branch the operand 32 bits following this opcode as an absolute address. In addition, the operation code 0xE9 sets 8 bits after the operation code as a relative value, and transfers to the address indicated by the sum of the address stored in the operation code and the relative value.

In other words, as shown in Figure 21A, when the address (2101) 0x00000010 (data (2102) of 2103) is 0xEA (2104), this part is to translate the data (2106) stored in the address 0x00000011 to 0x00000014 (2105) into transferable 00000318 for the 32-bit address command.

In addition, as shown in FIG. 21A, when the content of the address 0x000001F8 (2107) is 0xE9 (2108), it is to set the data 0x38 on the address 0x000001F9 (2109) as a relative value, and then transfer as 0x000001F8 and the relative value Sum of 0x00000230 commands.

Fig. 21B shows the control program shown in Fig. 20B in which the program error of the control program shown in Fig. 20A has been corrected.

Specifically, as shown in Fig. 20B, the capacity of the module B'2005 is 0x10 bits larger than that of the module B2002. As a result, the position of module C2003 following module B2002 is shifted by 0x10 bits. Therefore, the transfer destination of the absolute address transfer command stored in 0x00000010 (2103) becomes 0x00000328. In addition, the transfer destination of the relative address transfer command stored in 0x000001F8 (2109) becomes 0x00000240.

The terminal device in the sixth embodiment is described below. An example of a functional block diagram and an example of a memory map of the terminal device 1 of the sixth embodiment of the present invention are the same as those of the first embodiment and shown in FIGS. 1 and 2, respectively. Furthermore, it is assumed that 0x00110000 to 0x0011FFFF are used as an operation area where the control CPU 12 corrects the control program.

In the case where the program of FIG. 20A is recorded in the flash ROM 13, the method for updating the program shown in FIG. 20A by the terminal device 1 to the program shown in FIG. 20B will be described below. Here, the operation when the rewriting instruction shown in FIG. 23 is given to the terminal device 1 will be described with reference to the flowchart shown in FIG. 24 .

In addition, in the process of operating each instruction of FIG. 23, rewriting is the same as that of the fifth embodiment.

Also, in the case of expansion in the RAM 14, the data 2302 is located in the rear part of the instruction 2301 No. 1. In the data 2302 are arranged the start address 2303 of the extension source, the number of data items 2304 to be extended after the start address 2303 in the extension source, and the address 2305 of the extension destination after the number of data items 2304 to be extended.

The control CPU 12 expands data from the flash ROM 13 into the RAM 14 using these information.

Under the situation of writing back ROM 13, the header of the data 2302 behind instruction 2301 No. 6 represents to be recorded into the starting address 2306 of the target block in the flash ROM 13. After deleting the block starting with the head address 2306, the data in the area of the RAM 14 operation area will be determined in an optional manner to be recorded in the deleted block starting with the head address 2306 in the flash ROM 13. in the block.

Relative to the change in the address, the initial part of the data 2302 behind the instruction No. 4 is its shift value 2307 with the head in the optional area for the expansion program in the RAM 14. It instructs to interpret the opcode stored in the address indicated by the sum of the start address and the shift value 2307, and to update the operand corresponding to the interpreted opcode.

First, in step S181, when the command shown in FIG. 23 is supplied as a rewriting command of the program stored in the flash ROM 13 through the external connection interface 11, the control CPU 12 reads command No. 1.

Next, in step S182, the control CPU 12 checks whether the read command is a rewrite termination command. When the instruction is not a rewriting termination instruction, the control CPU 12 proceeds to the processing of step S183.

In step S183, the control CPU 12 checks whether the read command is an extended command in the RAM 14. If this instruction is the instruction that carries out expansion in RAM 14, control CPU 12 enters the processing procedure of step S186, and if when this read instruction is not the expansion instruction in RAM 14, it enters the processing procedure of step S184.

Instruction No.1 in FIG. 23 is an extended instruction in RAM 14. Therefore, in step S186, the control CPU 12 determines that the address of the extension source is 0x00000000 in the flash ROM 13 based on the data of the instruction No.1, the number of data items to be extended is 0x200 bytes, and the extension destination address is 0x00110000, as The starting address 0x00110000 of the previous operation area in RAM 14 plus the sum of shifting 0x00000000.

Next, in step S187, the control CPU 12 expands the data from the ROM 13 into the RAM 14 according to the address and the number of data items determined in step S186.

In the case that instruction No. 1 is the instruction shown in FIG. 23 , the data in 0x00000000 to 0x000001FF (that is, module A2001 in FIG. 20A ) is expanded on 0x00110000 to 0x00110FF of RAM 14.

Then, in step S195, the control CPU 12 writes down the displacement amount of the area 0x00000000 to 0x000001FF in the flash ROM 13 in the optional area except the operation area 0x00110000 to 0x0011FFFF of the RAM 14 is 0x00000000, then enters the processing of step S181 process.

Afterwards, because instruction No.2 among Fig. 23 is the same as instruction No.1, is the instruction that expands in RAM, so controls CPU 12 to carry out the expansion of data from flash ROM 13 to RAM 14 according to the mode same as aforementioned process process.

In this way, module C2003 in Figure 20A is extended at 0x00110230 to 0x0011060F of RAM 14.

Further, like the procedure described above, in step S195, the control CPU 12 records that the shift amount of the area 0x00000220 to 0x000005FF in the flash ROM 13 is 0x00000010.

Through the aforementioned process, records of the shift area start address 2501 and end address 2502 and the shift amount 2503 of the area shown in FIG. 25 are obtained.

The start address 2501 and end address 2502 of the shift area are actually the start address and end address of the shift area. This eliminates the need to describe the shifted area with actual data, thus reducing the amount of data.

Then, in the case that the command is command No. 3 in FIG. 23, the control CPU 12 reads the command in step S181, and then proceeds to the process of step S184 through the processes of steps S182 and S183.

In step S184, the control CPU 12 checks whether the read command is a data rewrite command. When the read command is a data rewrite command, the control CPU 12 proceeds to the processing of step S190, and when the read command is not a data rewrite command, it proceeds to the process of step S196.

Command No. 3 in FIG. 23 is a data rewrite command. Therefore, the control CPU 12 proceeds to the processing of step S190.

In step S190, the control CPU 12 determines that the address 0x00110200 obtained by adding the shift 0x00000200 to the start address 0x00110000 of the operating area in the RAM 14 is the rewrite start address by using the rewrite instruction No. 3 in FIG. The number of write data items is 0x30.

After that, in step S191, the control CPU 12 changes the content of address 0x002202000 according to the rewrite data of command No. 3 in FIG. 23 .

Then, in step S192, the control CPU 12 adds 1 to the rewrite address to become 0x00110201.

In step 193, the control CPU 12 subtracts 1 from the number of the rewritten data items to become 0x2F.

In step S194, the controlling CPU 12 checks whether the number of rewritten data items is 0, and when the number is not 0, it proceeds to the processing of step S191.

Then, the control CPU 12 repeats the above-described processing of steps S191 to S194 until the number of rewritten data items becomes zero.

When the number of rewritten data items becomes 0, the control CPU 12 proceeds to the processing of step S181.

Here, assuming that the subsequent data corresponding to 0x30 given by instruction No. 3 is module B'2005 in FIG. to 0x0011022F on extension module B'2005.

Through the aforementioned process, the program shown in Figure 19 starts to expand from the address 0x00110000 in the RAM 14.

Figure 26 shows the state of the RAM 14 at this point. Addresses (2601) 0x00110010 (2603) and 0x001101F8 (2605) have peripheral data (2602), 0xEA (2604) and 0xE9 (2606), respectively.

Then, in the case that the command is command No. 4 in FIG. 23, the control CPU 12 reads the command in step S181, and then proceeds to the process of S196 through the processes of steps S182, S183, and S184.

In step S196, the control CPU 12 checks whether the read command is an address change command. When the read command is an address change command, the control CPU 12 proceeds to the processing of S197. When the read instruction is not an address change instruction, the control CPU 12 proceeds to the processing of S185.

Command No. 4 in Fig. 23 is an address change command. Therefore, the control CPU 12 proceeds to the processing of S197.

In step S197, the control CPU 12 determines that the shift value 0x00000010 (2307) represented by the read address change command is an address change command of address 0x00110010 (which is to be added to the start address 0x00110000 of the operating area in the RAM 14).

Further, the control CPU 12 interprets the opcode 0xEA (2604) stored in the address 0x00110010 (2603) shown in FIG. 26 as an address to address 0x00000318 using the opcode shown in FIG. Transfer order.

Further, the control CPU 12 confirms that blocks 0x00000220 to 0x000005FFF including 0x00000318 have a shift amount of 0x00000010 using the module shift information record shown in FIG. 25 . Therefore, the control CPU 12 calculates that the branch destination address in the correction program is 0x00000328 obtained by adding the shift amount 0x00000010 to the uncorrected branch destination address 0x00000318.

Then, in step S198, the control CPU 12 updates the byte operands behind the opcode (data) (2702) 0xEA (2704) of addresses (2701) 0x00110010 (2703) to 0x00000328.

Control CPU 12 to enter the processing procedure of S181.

Furthermore, in command No. 5 of FIG. 23, the control CPU 12 reads the command in step S181, and then proceeds to the process of S197 through the processes of steps S182, S183, S184, and S196.

In step S197, the control CPU 12 judges whether the shift value 0x000001F8 indicated by the read address change command is an address change command to be added to the address 0x001101F8 on the start address 0x00110000 of the operation area of the RAM 14.

For example, the control CPU 12 interprets the opcode (2702) 0xE9 (2706) stored in the address (2701) 0x001101F8 (2705) of FIG. 27 as the address The transfer command of 0x00000230, the address 0x00000230 is obtained by adding 0x38 to 0x000001F8. Further, the control CPU 12 recognizes that blocks 0x00000220 to 0x000005FF including 0x00000230 have a shift amount of 0x00000010 using the shift record shown in FIG. 25 .

Therefore, the control CPU 12 can determine that the branch destination address in the correction program is 0x00000240 obtained by adding the shift amount 0x0000010 to the uncorrected branch address 0x00000230, and calculates that the relative address of 0x00001F8 with the opcode is 0x48.

Then, in step S198, the control CPU 12 transfers 1 word after the operation code (data) (2802) 0xE9 (2806) of address (2801) 0x001101F8 (2805) shown in Figure 28 according to the transfer destination address determined in step S197 The section operand is updated to 0x48.

Therefore, when the operand used for the operation code is shifted due to the capacity change of the module B, the control CPU 12 can automatically correct the operand based on the module shift information record shown in FIG. 25 . Therefore, it is not necessary to instruct the corrected content of the operand fetched from the outside, thereby reducing the data amount of the instruction.

Next, the control CPU 12 proceeds to process S181.

Afterwards, in the case that the command is command No. 6 in FIG. 23, the control CPU 12 reads the command in step S181, and then proceeds to the processing of step S185 via steps S182, S183, S184, and S196.

In step S185, the control CPU 12 checks whether the read instruction is an instruction to write back to the ROM, and when the read instruction is an instruction to write back to the ROM 13, it enters the processing of step S188, and when the read instruction is not to write When returning the instruction of ROM 13, it enters the processing procedure of step S181.

Instruction No.6 among Fig. 23 is the instruction of writing back ROM 13. Therefore, the control CPU 12 proceeds to the processing of step S188.

In step S188, the control CPU 12 determines the block in the flash ROM 13 indicated by the read command to write back to the ROM 13. For example, in the case where the command is command No. 6 exemplarily shown in FIG. 23, the control CPU 12 determines addresses 0x00000000 to 0x0000FFFF as this block.

Next, in step S189, the control CPU 12 deletes the blocks at 0x00000000 to 0x0000FFFF of the flash ROM 13 determined in step S188. Then, the control CPU 12 records the new control software stored in the operation area 0x00110000 to 0x0011FFFF of the RAM 14 onto the deleted block of the flash ROM 13.

Control CPU 12 enters the processing procedure of step S181.

Then, the control CPU 13 repeats the foregoing processing until the command read in step S181 is judged as a rewriting termination command in step S182.

As described above, according to the sixth embodiment, the control software stored in the flash ROM 13 of the terminal can be updated without downloading the entire correction program as shown in FIG. 20B.

In addition, although the sixth embodiment describes the case where the program is composed of three modules, the number of modules and the module capacity are not limited to those described above.

Although FIG. 22 will be shown in the sixth embodiment as an example of the operation code of the transfer command, depending on the type of control CPU 12 used in the terminal device 1, the same effect can be obtained by using an operation code other than that shown in FIG. 22.

In addition, the sixth embodiment describes the case where the absolute value transfer and relative value transfer operands are corrected using the block shift information record shown in FIG. 25 . However, function call commands and transfer commands are also applicable.

Furthermore, according to the sixth embodiment, when a branch command and a function call command (each having a relative specified address) are used and they both exceed the address range available in the relative address specified branch command, support for downloading through the external interface is canceled. Data for indicating a relative conversion from a relative address-specified branch command or a relative address-specified function call command to an absolute address-specified branch command or an absolute address-specified function call command to become a request for updating a program. Thus, the amount of data indicated through the external interface is reduced. As a result, the program update operation time including the data transfer time can be shortened.

In addition, in the case where there is a look-up table configuration consisting of events such as alarms, key presses, and address of the presence of processing modules of the present invention, the module shift information record shown in FIG. 25 can be used to correct the location of the processing modules on the look-up table. Address exists.

In the case of calibrating the look-up table, the look-up table position can be indicated externally or by using an address preloaded in the terminal device 1 . When loading the look-up table address, the look-up table can be corrected automatically without external instructions.

In addition, in the sixth embodiment, an instruction for changing an address in which a command is stored can be performed using an address (operand) such as an absolute value branch and a relative value branch. However, the control CPU 12 can automatically judge whether an command such as an absolute value transfer or a relative value transfer exists in the address in the process of receiving an instruction indicating only an address, and when the command exists, utilize the command shown in FIG. 25 The block shift information records the correction operand.

It is thus possible to dispense with fetching instructions from the outside. In addition, operands employed in commands can be automatically corrected without knowing that commands such as absolute value transfers or relative value transfers are stored.

Also, by disassembling the program from the beginning, it is possible to extract a branch (function call) instruction, and correct an address used in the instruction. Thus, the instruction fetched from the outside is reduced.

In this case, since it is difficult to separate the program part when the program and data parts are combined, it is possible to designate the program part from the outside in advance, disassemble only the designated part, and then recalculate the address.

In this way, the need to externally designate the position of a branch (function call) command is eliminated, so that instructions fetched externally can be reduced.

Furthermore, the sixth embodiment described the case where the determination processing of the instruction content read in step S181 is performed in the order of steps S182, S183, S184, S196, and S185, but the determination order may also be optionally changed.

Also, in the sixth embodiment, the rewrite address is incremented by 1 in step S192, and then the number of rewrite data items is decremented by 1 in step S193. However, the same effect can also be obtained by first reducing the number of rewriting data items by 1, and then adding 1 to the rewriting address.

Furthermore, in the sixth embodiment, after determining the address of the expansion source, the number of data items to be expanded, and the address of the expansion destination in step S186, the data is expanded from the flash ROM 13 to the RAM 14 in step S189. This shift is recorded in step S195. However, the same effect can be achieved by first recording the shift and then expanding the data from the flash ROM 13 into the RAM 14.

This application is based on Japanese Patent Applications 2002-294499 filed on October 8, 2002 and 2003-347561 filed on October 6, 2003, the entire contents of which are hereby expressly incorporated by reference.

Industrial Applicability

According to the present invention, in the process of updating the software stored in the nonvolatile memory of the terminal for correction, the software can be corrected without downloading all correction software to the terminal, and it is advantageous to efficiently update the software in the terminal. software.

Claims (27)

1. A program update method, comprising: In updating a program stored in a rewritable nonvolatile memory, wherein the rewritable nonvolatile memory is composed of a plurality of blocks, and the blocks include a block storing an update target portion of the program , expanding the program part in the block storing the update target part of the program in the RAM; updating only the update target portion of the program portion expanded in the RAM according to a rewrite instruction instructed through an external interface, writing the updated portion of the program back to the non-volatile memory together, and When the capacity of the update target portion changes due to the update, the rewrite command is an instruction to move the address position of the subsequent portion when expanding the subsequent portion in the RAM, thereby changing the address position stored in the The relative position between the update target portion and the subsequent portion of the update target portion in the nonvolatile memory. 2. The program update method according to claim 1, wherein when the capacity of the update target portion is increased due to update, the rewrite instruction is used to shift the a subsequent portion, an instruction for increasing a relative positional relationship between the update target portion and a subsequent portion of the update target portion stored in the nonvolatile memory. 3. The program updating method according to claim 2, wherein said rewriting instruction includes address information determining said subsequent portion and a start address of extending said subsequent portion within said RAM. 4. The program updating method according to claim 3, wherein determining the address information of the subsequent part comprises a start address and a number of data items of the subsequent part in the nonvolatile memory or in the RAM. 5. The program updating method according to claim 3, wherein determining the address information of the subsequent portion includes a start address and an end address of the subsequent portion in the nonvolatile memory or the RAM. 6. The program update method according to claim 2, wherein the shift information of the subsequent part in the RAM is recorded in another area of the RAM different from the program extension area, when the nonvolatile When the address of the volatile memory or the RAM is indicated by a program instruction, the absolute address value stored in the indicated address is corrected according to the shift information. 7. The program updating method according to claim 6, wherein said shift information includes address information determining a position of said subsequent part and a start address of extending said subsequent part in said RAM. 8. The program updating method according to claim 7, wherein determining the address information of the subsequent part comprises a starting address and a number of data items of the subsequent part in the nonvolatile memory or the RAM, or A start address and an end address of the subsequent part in the non-volatile memory or the RAM. 9. The program updating method according to claim 7, wherein the start address of the subsequent part when expanding the subsequent part in the RAM is the same as that in the nonvolatile memory or the RAM according to Relative address to the start address of the optional area. 10. The program updating method according to claim 6, wherein a rewriting instruction indicates an address in said nonvolatile memory or said RAM, and corrects the absolute value stored in said indicated address according to said shift information. address specifies the absolute address value used by the branch command. 11. The program updating method according to claim 6, wherein a rewriting instruction indicates an address in said nonvolatile memory or said RAM, and corrects an absolute value stored in said address indicated by said shift information in accordance with said shift information. address specifies the absolute address value used by the function call command. 12. The program updating method according to claim 6, wherein a rewriting instruction indicates an address in said nonvolatile memory or said RAM, and corrects the relative value stored in said indicated address according to said shift information. address value. 13. The program updating method according to claim 6, wherein a rewriting instruction indicates an address in said nonvolatile memory or said RAM, and corrects a relative value stored in said address indicated in accordance with said shift information. address specifies the relative address value used by the branch command. 14. The program updating method according to claim 6, wherein a rewriting instruction indicates an address within said nonvolatile memory or said RAM, and a relative address stored in said address indicated is corrected according to said shift information Specifies the relative address value used by the function call command. 15. The program updating method according to claim 12, wherein in the process of correcting the relative address value of the program according to the shift information, the corrected relative address value exceeds a range allowing relative address designation , convert the relative address value into an absolute address value. 16. The program updating method according to claim 13, wherein in the process of correcting the relative address value of the program according to the shift information and correcting the corrected relative address value into an absolute address value, using The uncorrected relative address value converts a relative address specifying branch command into an absolute address specifying branch command. 17. The program updating method according to claim 14, wherein in the process of correcting the relative address value of the program according to the shift information and converting the corrected relative address value into an absolute address value, using The uncorrected relative address value converts a relative address specifying function call command into an absolute address specifying function call command. 18. The program updating method according to claim 1, wherein the rewriting instruction includes a starting address of the expansion of the program part in the nonvolatile memory or the RAM, the number of data items to be rewritten and the subsequent actual rewriting of the data. 19. The program updating method according to claim 1, wherein said rewriting instruction includes a start address of said program part expanding in said nonvolatile memory or in said RAM, subsequent actual rewriting data and specific data indicating the termination of the rewrite. 20. The program updating method according to claim 3, wherein in the process of specifying the address of the rewrite instruction, an absolute value is first used for address specification, and then a relative address according to the address just specified before is used for subsequent address specification . 21. The program updating method according to claim 3, wherein in the process of specifying the address of the rewrite instruction, the address is specified using an absolute value first, and then when the subsequent rewriting process is completed by the specified address, the address is specified according to the address. Subsequent address specification for the relative address. 22. The program update method according to claim 3, wherein in the process of specifying the address of the rewriting instruction, the address specified in advance is used as a reference to specify the address, and the subsequent specification is to use the previously specified address as a reference A relative address specification for an address. 23. The program update method according to claim 3, wherein in the address designation process of the rewrite instruction, an absolute value is first used for address designation, and then a subsequent address designation is performed using an address determined in advance as a reference, and the subsequent address Designation is based on relative address designation of the address when the subsequent rewriting process is completed by the designated address. 24. A terminal device comprising: Rewritable non-volatile memory with programs stored in multiple blocks; RAM; an external interface for receiving a rewriting instruction of the program; and a controller that expands, in RAM, the program portion in the block storing the update target portion of the program, and performs only the expanded program portion in the RAM in accordance with the rewrite command. updating the target part to update, and then writing the updated program part back to the non-volatile memory together, Wherein, when the capacity of the update target part changes along with the update, the rewrite instruction is an instruction for moving the address position of the subsequent part when expanding the subsequent part in the RAM, thereby changing the address position stored in the RAM. A relative position between the update target portion of the nonvolatile memory and the subsequent portion of the update target portion. 25. The terminal device according to claim 24, wherein the external interface is a wired connection interface. 26. The terminal device according to claim 24, wherein the external interface is a wireless connection interface. 27. The terminal device according to claim 24, wherein the external interface is a memory card interface, and the controller reads the rewriting instruction from a memory card inserted into the memory card interface.

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