CN100337201C - Method for safety startup of system and device thereof - Google Patents
Method for safety startup of system and device thereof Download PDFInfo
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- CN100337201C CN100337201C CNB2005100709911A CN200510070991A CN100337201C CN 100337201 C CN100337201 C CN 100337201C CN B2005100709911 A CNB2005100709911 A CN B2005100709911A CN 200510070991 A CN200510070991 A CN 200510070991A CN 100337201 C CN100337201 C CN 100337201C
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Abstract
本发明涉及一种系统安全启动的方法及装置。所述方法包括：A、将引导程序和应用程序同时保存到第一和第二程序掉电保存介质中；B、设置用于启动引导程序和应用程序的标志，并保存在逻辑介质中；C、系统上电后，根据所述启动标志启动第一程序掉电保存介质的程序；D、如果所述第一程序掉电保存介质的程序启动失败，则启动第二程序掉电保存介质的程序。所述装置包括：系统中央处理器、第一程和第二序掉电保存单元以及逻辑单元。以解决当主FLASH芯片被损坏，导致系统无法启动，用户通过使用新增的FLASH芯片作为主芯片来启动系统，以实现通信设备程序的可靠备份及其升级，进而提高通信设备的使用效率。
The invention relates to a method and device for system safety startup. The method includes: A. simultaneously saving the boot program and the application program to the first and second program power-down storage media; B. setting a sign for starting the boot program and the application program and storing them in the logical medium; C. , after the system is powered on, start the program of the first program power-down storage medium according to the startup sign; D, if the program startup of the power-down storage medium of the first program fails, then start the program of the second program power-down storage medium . The device includes: a system central processing unit, a first program and a second program power-down storage unit and a logic unit. To solve the problem that the system cannot start when the main FLASH chip is damaged, the user starts the system by using the newly added FLASH chip as the main chip, so as to realize reliable backup and upgrade of the communication equipment program, thereby improving the use efficiency of the communication equipment.
Description
Technical field
The present invention relates to the start-up technique field of data communications equipment, specifically, particularly relate to a kind of method and device thereof of safety startup of system.
Background technology
Along with the development of data communications equipment, the user constantly strengthens the functional requirement of data communication facilities, and increasing communication facilities all provides the function of program upgrade, with protection user's investment.In customer upgrade procedure, if the environment of upgrading is more abominable, such as power down in the escalation process, perhaps Sheng Ji document copying mistake, perhaps the user is not very familiar to escalation process and upgrade method of the mistake selected or the like all may cause data communications equipment not turn round normally; On the one hand, the program of data communications equipment all is stored in the FLASH device generally speaking in addition.Described FLASH is the abbreviation of Flash Memory, but is a kind of non-volatile flash memory that can wipe field programming fast.Because it is non-volatile that the FLASH device has, it is widely used in BOOTROM, online erasable and occasions such as power down protection data and partition protecting data, uses very extensive at modern communications and microelectronic.But if extraneous abominable environment for use may cause the FLASH components from being damaged when customer upgrade, institute thinks the reliability of raising data communications equipment, is necessary the program's memory space of data communication facilities is carried out Redundancy Design.
At present, program's memory space to data communication carries out Redundancy Design, see Fig. 1 for details, this figure is the synoptic diagram of program memory system, by among the figure as can be known, mode now commonly used is that the program with data communications equipment is divided into two sections, and first section program is the BOOT boot, and second section program is application program.In use, if require first section program not to be upgraded, the user is only to upgrade second section application program.In the time of the customer upgrade application program,, all may cause the upgrading failure, and system can't be used because of maloperation, upgrade file mistake or other reason.When system can't use, the user can also pass through first section BOOT boot again, restarted, and promptly ROMPaq again makes system's operate as normal.
But only designing on the circuit board in the more and more data product now has a slice FLASH, has wherein both deposited the BOOT boot, also deposited application program, and application program generally all requires online upgrading.BOOT boot in the FLASH chip might be write when upgrade applications by mistake, perhaps causes loss of data when software breaks down.To cause veneer not restart after the BOOT boot is destroyed.
The system design of the system central processor of described data communications equipment comprises as shown in Figure 2: system central processor 11 (system central processor), Flash1 chip 12, clock signal 15 and watchdog circuit 16 (watchdog).Wherein, described clock signal 15, watchdog circuit (watchdog) 16 link to each other with system central processor 11, and system central processor 11 links to each other with the Flash chip with read-write and chip selection signal by address bus, data bus.This watchdog circuit is used for system reset, and when system breaks down can not normally start the time, this watchdog circuit is finished system reset to restart.
This shows, the shortcoming of above-mentioned open scheme is: 1) only exist in the FLASH chip when the BOOT of data communications equipment boot and application program, not backup, BOOT boot in the FLASH chip has significant deficiency, and in the time of must upgrading to the BOOT boot again, if the data communications equipment that BOOT boot upgrading is not provided just can't start-up system; 2) when the FLASH of data communications equipment chip because of unpredictable reason (such as system's power down, BOOT boot upgrading failure) when causing damaging, unless give the burned new procedures of FLASH chip again, otherwise system can not restart.
Summary of the invention
The technical matters that the present invention solves provides a kind of method and device thereof of safety startup of system, when the main FLASH chip of data communications equipment is damaged by unpredictable reason, when causing system to start, the user can be by using newly-increased FLASH chip, and make it come start-up system as master chip, with need for reliable backup, reliably use and the reliable upgrading thereof that realizes the data communications equipment program, and then the service efficiency of raising data communications equipment.
For addressing the above problem, the invention provides a kind of method of safety startup of system, described method comprises step:
A, boot and application program be saved in simultaneously medium is preserved in the first program power down and the second program power down is preserved in the medium;
B, be provided for starting the sign of boot and application program, and be kept in the logical media, described startup sign comprises that the switching signal that height changes still is the program of the first program power down medium to select starting second, when the system start-up success, and the state of the current switching signal of system lock; Described switching signal changes once every time T;
After C, system powered on, logical media started the program that medium is preserved in the first program power down according to the described startup sign that is used for boot and application program;
If the program start failure of medium is preserved in the described first program power down of D, start the program that medium is preserved in the second program power down.
Described step C specifically comprises:
31) when the switching signal output low level, judge that the boot of first program power down preservation medium starts in the T at the fixed time;
32), judge that then the application program of first program power down preservation medium starts in the T at the fixed time if the boot of medium is preserved in the first program power down can be started;
33) if the application program of medium is preserved in the first program power down can not be started, then judge whether to preserve the application program updating of medium to the first program power down by the operator, if not, switching signal jumps to high level; If then switching signal is locked as low level.
Step 33) in, adopt following step to start the second program power down and preserve medium:
41) when switching signal output high level, judge that the guiding of second program power down preservation medium starts in the T at the fixed time, if can, then execution in step 42), otherwise, the outputting alarm signal;
42) application program of judgement second program power down preservation medium starts in the T at the fixed time, if energy, system moves normal, and switching signal is output as high level, otherwise, return step 41).
In addition, the present invention also provides a kind of safety startup of system device, comprising:
System central processor;
The unit is preserved in the first program power down, is used to store boot and application program;
The unit is preserved in the second program power down, is used to store boot and application program, preserves medium with the first program power down respectively by data bus, address bus and control bus and links to each other with system central processor; Logical block is preserved the unit with system central processor, the first program power down respectively and is connected with second program power down preservation unit, selects to start the program that the unit is preserved in the described first and second program power down by the high-low level that switching signal in it is set;
Described logical block comprises:
First register, its internal state just change and are described switching signal, and state changed once every the predetermined T time; When the system start-up success, central processing unit locks its current state;
Comprise second register again, whether successful in order to the startup of expression application program and boot.
Also comprise the 3rd register, this moment, whether the 3rd register was successful in order to the expression application program launching, and whether second register only starts success in order to the expression boot.
Compared with prior art, the present invention has following beneficial effect: the present invention adopts the mode of " initial back-up ", the programming simultaneously of boot that will be used to start and application program is preserved medium and second program power down preservation medium (two flash memories) to the first program power down, when system powers on, during the switching signal output low level, in interior boot and the application program that starts first program power down preservation medium respectively, if start unsuccessful, i.e. upgrading failure, or damaged by unpredictable reason, cause system to start.When powering on once more, during switching signal output high level, logical device conducting chip selection signal is connected to the second program power down and preserves on the medium (flash memory), and the program space of this device is carried out updating operation, comprises the upgrading to boot and application program.The up-to-date version of can upgrading, the program that also can copy on the second program power down preservation medium is preserved in the medium to the first program power down, this is freely selected by the user, thereby avoided when the BOOT of data communications equipment boot has significant deficiency or unpredictable reason when causing damaging, system can't start-up system or permanent can't the use.Therefore, the present invention has realized the need for reliable backup and the upgrading thereof of the program of data communications equipment to the Redundancy Design of program's memory space, and then improves the reliability of data communications equipment.
Description of drawings
Fig. 1 is the synoptic diagram of data communications equipment program memory system in the prior art;
Fig. 2 is the theory diagram of data communications equipment cpu system design in the prior art;
Fig. 3 is the process flow diagram of safety startup of system method of the present invention;
Fig. 4 is the synoptic diagram of data communications equipment program memory system of the present invention;
Fig. 5 is the synoptic diagram of logical process flow process of the present invention;
Fig. 6 is the theory diagram that the cpu system of the device of safety startup of system of the present invention designs;
Fig. 7 is the synoptic diagram of logic switch signal among the present invention.
Embodiment
Core of the present invention be to use two program power down preserve media (such as, flash memory, FALSH chip), store the complete code of two covers respectively.For convenience of description, described two program power down are preserved medium and are respectively first program power down preservation medium and second program power down preservation medium below.Under the normal process situation, the procedure stores of data communications equipment is preserved in the medium in the first program power down, and system central processor carries out start-up operation by boot and application program that address bus, data bus, read-write operation and chip selection signal are preserved in the medium the first program power down.And in technical solutions according to the invention, at first will guide (Boot) and application program to be cured to the first program power down simultaneously and preserve in medium and the second program power down preservation medium; Secondly, be provided for starting the startup sign of boot and application program; Once more, after system powers on, start boot and the application program that medium is preserved in the first program power down according to described startup sign; If the user starts the application program failure that medium is preserved in (upgrading) first program power down.The user can utilize the first program power down to preserve the BOOT program of medium, continues the application program of first program power down preservation medium is started; When if the BOOT program start of user's first program power down preservation medium is also failed, system can start the second program power down and preserve medium, the dielectric device program's memory space is preserved in the first program power down carried out updating operation, described program memory system comprises BOOT program and application program, see Fig. 3 for details, be the synoptic diagram of program memory system.When startup second program power down preservation medium is upgraded to first program power down preservation medium, can adopt up-to-date ROMPaq, the program in the medium of also the second program power down can being preserved copy the first program power down to and preserve in the medium, and which kind of mode the user is free to select to adopt the operation that the program's memory space of medium is upgraded is preserved in the first program power down.In addition, if preserving medium, the first program power down causes damaging by unpredictable reason, when perhaps causing first program power down preservation medium again can't start up with other reason, the user can use the second program power down to preserve medium, comes start-up system as master chip.When the application program updating of second program power down preservation medium was also failed, in this case, the user can preserve medium BOOT program by the second not scalable program power down and upgrade to the application program of second program power down preservation medium.By technical solutions according to the invention, realized the need for reliable backup and the upgrading thereof of data communications equipment program, and then put forward the reliability of system.
The present invention is further illustrated below in conjunction with accompanying drawing.
See also Fig. 3, be the process flow diagram of safety startup of system method of the present invention, described method comprises:
Step S10: boot and application program are saved in first program power down preservation medium and the second program power down preservation medium simultaneously;
Step S11: be provided for starting the sign of boot and application program, and be kept in the logical media;
Step S12: after system powered on, logical media started the program that medium is preserved in the first program power down according to the described startup sign that is used for boot and application program;
Step S13:, then start the program that medium is preserved in the second program power down if the program start failure of medium is preserved in the described first program power down.
For convenience of description, existing is that example describes with program power down preservation medium with flash memory (FALSH chip).
The present invention will guide (Boot) program and application program to be cured to simultaneously in FALSH1 chip and the FALSH2 chip (step S10) by fever writes, and the storage mode of its program sees Fig. 4 for details; The startup sign that starts boot and application program is set, and this sign is stored in (step S11) in the logical media; When communication facilities just often, producing one-period according to the clock signal of the system counter by logical block is the switching signal of 2T, the described cycle is that the width of the switching signal of 2T decides according to the startup speed of system central processor, debugging, can control by programming in logic.After system powers on, when the switching signal output low level, the chip selection signal that is system central processor according to described startup sign is conducting to first chip selection signal, select to use the FLASH1 chip, in interval T at the appointed time, if system can start up (illustrating that the FLASH1 start-up system is normal), the CPU (central processing unit) of system can force to be set to low level (step S12) by this logic switch inside signal.Otherwise, then the FLASH1 chip damages or upgrades to fail and causes program not start up, the time T that surpasses switching signal, when logical block switch inside signal arrives high level, chip selection signal is conducting to second chip selection signal, thereby select to use the FLASH2 chip, in T at the appointed time, system can start up from the FLASH2 chip.After system got up, the CPU (central processing unit) of system can be according to the state of logical block inside, provided corresponding upgrading interface for users whether to select upgrading restoring FLASH1 chip, still just used the program (step S13) in the FLASH2 chip.
The specific implementation process of described step S12 and step S13 sees Fig. 5 for details, is logical process flow process of the present invention.Its implementation procedure is: after system powers on, during the switching signal output low level, judge that can the boot of FLASH1 chip start in predetermined; If can not start, switching signal output high level; If can start, judge that then can the application program of FLASH1 chip start in predetermined; If the application program of FLASH1 chip can not start, then judge whether and if then switching signal forces to be set to low level, otherwise to start the program of FLASH2 chip to the application program updating of FLASH1 chip.Wherein said switching signal forces to be set to low level, can not carry out updating operation to this chip again after just being meant mandatory the setting.
The specific implementation process that described step S13 starts the program of FLASH2 chip is: when the application program of FLASH1 chip in the time can not starting, in the time of can not upgrading to this again, the flogic system switching signal is set to high level, promptly be connected on the FLASH2 chip by chip selection signal, can boot that judge the FLASH2 chip in predetermined interior startup, if can not, the outputting alarm signal, illustrate that this procedure stores chip all can not re-use, or print error message; If can, judge again that then can the application program of FLASH chip also in predetermined interior startup, if can start, the illustrative system operation is normal, and the flogic system switching signal is set to high level, if can not start, then switching signal is set to low level, re-executes above-mentioned steps S12.Wherein, the described schedule time is the half period of switching signal.
In addition, the present invention also provides a kind of safety startup of system device, sees Fig. 6 for details, and described device comprises: unit 12 is preserved in system central processor (such as the BCM4704 chip) 11, the first program power down, unit 13 and logical block 14 are preserved in the second program power down; And clock signal 15, chip selection signal, first chip selection signal and second chip selection signal.The wherein said first program power down is preserved unit 12 and is linked to each other with logical block 14, is to be used to store boot and application program; Unit 13 is preserved in the described second program power down, preserving unit 12 with the first program power down respectively by data bus, address bus and control bus links to each other with system central processor 11, be used for described boot of back-up storage and application program, preserve the unit by the first preface power down of upgrading of second chip selection signal; Described logical block 14, preserving unit 12 with system central processor 11, the first program power down respectively links to each other with second program power down preservation unit 13, clock signal by system central processor is the 2T switching signal by logical block 14 generation one-periods, realize conducting first chip selection signal or second chip selection signal by the high-low level that switching signal is set, realize the described first and second program power down are preserved the control of unit.
The described first and second program power down are preserved the unit and comprised: flash memory (FLASH chip) or electrically alterable storage come, so long as the medium of obliterated data can not after the power down.Described FLASH chip is a kind of program's memory space, and program is not lost after the power down.
Described logical block 14 can use programmable logic device (PLD) to realize usually; Also can be combined into device by simple logic chip with logic function.No matter the present invention is to adopt programmable logic device (PLD), still adopts simple logic chip to be combined into the device with logic function.That can realize switching signal is provided with conducting first chip selection signal and second chip selection signal, to start different program's memory space (being that the unit is preserved in FLASH1 or the FLASH2 first and second program power down).
Described logical block comprises: first register, second register, the 3rd register sum counter and other combinational logic.Described counter is normally realized by a plurality of d type flip flops.And clocking capability is provided, according to the clock of system, count, and to produce one-period be the switching signal of 2T, described switching signal as shown in Figure 7, when the switching signal output low level, the first chip selection signal conducting, the user selects to use the FLASH1 chip operation; Otherwise, when switching signal output high level, the second chip selection signal conducting, the user selects to use the FLASH2 chip operation.Described register provides the handshake function of logical block and system central processor, the logic software program run is in the system central processor chip, can read and write the state of register in the logical block, thereby reach the handshake function between system central processor unit and the logical block.
As shown in Figure 6, the address bus that the FLASH chip is operated, data bus, read-write control bus are connected on two FLASH chips simultaneously.Chip selection signal is connected respectively on two FLASH chips by logical block.Chip selection signal wherein, read-write, address bus, data bus are all from the system central processor unit of system.And clock signal is any unit that clock can be provided in the data communications equipment system (such as system clock and pass through the clock signal that crystal oscillator produces).Therefore, realize that the present invention relies the control of system's CPU (central processing unit) to logical block, the sheet selected control system to the FLASH chip that described logical block realizes by programming in logic.
The principle of its logic realization is: the switching signal of at first utilizing the clock signal generation one-period of logical block.The clock of described logical block can produce by an external crystal oscillator, but generally, each system is general all by the clock of oneself, and logical block can directly be used the clock of system, need on veneer, not increase clock again, like this can be with low cost.The width of the cycle 2T of described clock is regulated according to the startup speed of system central processor, and generally speaking, the system start-up that dominant frequency is high is fast, and is more a lot of soon than the toggle speed of the system of 50MHz as the toggle speed of the system of 266MHz.The program start that the program start that programming efficiency is high is lower than programming efficiency is fast.All be different the start-up time of each system, and therefore, the speed of start-up time has determined the length of the counter timing of logical block, with the optimal function of performance system.Such as: the dominant frequency of a 266MHz of system, system just can start up in 1 minute, if design clock half period T is 5 minutes, can waste very much the resource and the time of system.If the half period T of clock is adjusted to 1.2 minutes.Such design is an optimal design.Described cyclical signal, half period T requires to satisfy system requirements, and just the width of half period T decides according to startup speed, the debugging of system central processor, can control this process by programming in logic.Promptly when low level, chip selection signal is conducting to first chip selection signal, thereby select to use the FLASH1 chip, in half period T at the appointed time, system start-up is got up (illustrating that the FLASH1 start-up system is normal), and the CPU (central processing unit) of system can be this logic switch inside signal force values a low level.Causing program otherwise damage of FLASH1 chip or upgrading failure are led can not start up, when overtime T, when logical block switch inside signal arrived high level, chip selection signal was conducting to second chip selection signal, thereby select to use the FLASH2 chip, system starts in FLASH2.After system got up, the CPU (central processing unit) of system can be according to the state of logical block inside, provided corresponding upgrading interface for users whether to select upgrading restoring FLASH1, also was to use the program among the FLASH2.It realizes that principle is: if a register is arranged in the logical block, the state that this register is set when state starts as described above when system is 1, and system central processor is by reading the state that signal reads this register.When buffer status is 0, illustrate not to be above-mentioned starting state 0; When register is a state when being 1, the software in system central processor is carried out corresponding program, and the interface of hommizations such as client's guiding function is provided.
For the clearer description of energy, please refer to following example: after system powers on, there is one first register logic of propositions inside, state variation in it is represented switching signal, change once every the T time, its initial state is defaulted as low level, thereby first chip selection signal of system is connected on the FLASH1 chip when powering on, when the BOOT section program start success of the program of FLASH1 chip, system central processor can write 1 (being defaulted as 0 when powering on) in second register of logical block; When its application program section also starts when successful, system central processor can write 1 (acquiescence 0 when powering on) in another one the 3rd register of logical block; When time of arrival of switching signal during T, logical block checks whether above-mentioned second is identical with the 3rd register write state, if identical, and be 1, show that then system starts normally from FLASH1.If the state of second register is 1, and the state of the 3rd register is 0, illustrates that the application program of FLASH1 is incorrect, logic software output this moment choice menus: the 1) application program among the recovery FLASH1; 2) come start-up system from the FLASH2 program.When the user selected 1, the user began again the application program in the upgrading FLASH 1, was equivalent to re-power start-up system then.When the user selected 2, the user began to start the program of FLASH2, comes start-up system.The start-up course of same FLASH2 program is identical with the start-up course of FLASH1, promptly starts the boot of FLASH2 earlier, as if can start in time T the time, restart the application program of FLASH2, if its application program also can start in time T, then, illustrative system normally moves.Certainly, also can select the example of a simplification to illustrate: the situation that does not promptly have the 3rd register, have only first and second registers, this moment, first register functions was constant, second register then characterizes the FLASH chip and whether starts success, have only when priming program and application program and all start when successful, just second register is put 1, otherwise put 0, the meaning can not normally start from the FLASH1 chip in other words, system can not lock first register, when time T arrives, the first register redirect high level, system will start from FLASH2.
From the above, the chip selection signal of the different FLASH chips that system central processor provides according to logical block starts different FLASH chips.No matter from which FLASH device, start up, all starting state must be write in the register of logical block, make logical block know the current system central processor state of operation at present; Otherwise system central processor also can read present system and start from which FLASH device from logical block, thereby makes the user know the startup and the running status of current data communication facilities.Said process is realized by software program, described software program is stored in the FLASH chip, behind the chip that starts FLASH, software program moves in system central processor, is equivalent to software program and has begun to carry out, software program is by the address bus of system central processor, data bus, reading writing signal line or GPIO pin, the logical address space of register in the access logic unit, described register is carried out read-write operation, thereby reach the function of shaking hands with logical block.
Therefore, adopt technical scheme of the present invention to have following technique effect: A, reliability height.The present invention does not introduce new unit when solving the facility communication system clean boot, do not introduce new input signal yet.All Primary Components are all had by common communication system.B, be widely used.In general general system CPU, can adopt the present invention.Described logical block is provided with buffer status as long as support to power on, logical block is identical and for high level (promptly 1) by searching state with at least two register-stored after comparison system powers on, judges whether the program in normal startup or the upgrading FLASH chip.And other device is not required.C, flexible design.Boot guides to the physical address of program and can adjust by the chip selection signal of logical block, so that the need for reliable backup and the upgrading thereof of procedure stores are provided.
The above; only be the preferable embodiment of the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in technical scope disclosed by the invention; under the prerequisite that does not break away from the principle of the invention; can make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
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| CNB2005100709911A CN100337201C (en) | 2005-05-19 | 2005-05-19 | Method for safety startup of system and device thereof |
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| CN114116299A (en) * | 2020-08-31 | 2022-03-01 | 上海禾赛科技有限公司 | Lidar, Lidar start system and its multiple start method |
| CN112130914A (en) * | 2020-09-04 | 2020-12-25 | 山东云海国创云计算装备产业创新中心有限公司 | Uboot starting method, device, equipment and medium |
| CN114968380A (en) * | 2021-02-26 | 2022-08-30 | 南宁富联富桂精密工业有限公司 | Electronic device and multiple starting method |
| CN118093056B (en) * | 2024-04-24 | 2024-07-02 | 中电科申泰信息科技有限公司 | Primary starting program starting method adopting self-adjusting starting medium technology |
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| US20030188223A1 (en) * | 2002-03-27 | 2003-10-02 | Alexis Alan Previn | BIOS shadowed small-print hard disk drive as robust, always on, backup for hard disk image & software failure |
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| CN1598773A (en) * | 2003-09-17 | 2005-03-23 | 三星电子株式会社 | Booting and boot code update method and system thereof |
Also Published As
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| CN1725179A (en) | 2006-01-25 |
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