CH687423A5 - Multi-function counter incorporating electricity meters - Google Patents

Abstract

The counter has a respective electricity meter (20,21,22) for each phase, providing output pulses with a frequency (fr, fs,ft) proportional to the power of the corresponding phase. The measuring stage (21) for each phase indicates a phase loss when no zero transitions of the phase voltage are detected and is followed by a respective evaluation stage with a pulse duration decoder for activating a phase loss display.

Description

       

  
 



  The invention relates to a multifunction counter according to the preamble of claim 1.



  A multifunction counter of the type mentioned in the preamble of claim 1 is known from US Pat. No. 4,742,296.



  The invention has for its object to improve the known multifunction counter so that a determined direction of energy flow and a detected phase failure can be recognized.



  According to the invention, this object is achieved by the features specified in the characterizing part of claim 1. Advantageous embodiments of the invention result from the dependent claims.



  An embodiment of the invention is shown in the drawing and will be described in more detail below.



  Show it:
 
   1 is a block diagram of a multifunction counter,
   2 is a block diagram of a power supply with an associated voltage monitoring arrangement,
   3 shows a block diagram of a signal processing arrangement,
   4 shows a block diagram of a signal evaluation arrangement,
   5 is a block diagram of an error detection arrangement,
   6 shows a state diagram of a 5-bit up / down counter,
   7 is a state diagram of a 3-bit up / down counter,
   8 shows a register arrangement of a measuring unit,
   9 shows a first variant of a bus interface connection between three measuring units and a master computer
   10 shows a second variant of a bus interface connection between three measuring units and a master computer.
 



  The same reference numerals designate the same parts in all figures of the drawing.



  The multifunction meter includes a single-phase or multi-phase electricity meter 20; 21; 22, an overvoltage protection arrangement 23, a power supply 24, a fault detection arrangement 25, a microcomputer 26, an optional ripple control receiver RCR, a liquid crystal display LCD and a clock circuit 27; 28; 29, which in addition to a calendar clock 27, which is a real-time clock, also contains a driver 28 for the liquid crystal display LCD and a voltage divider and temperature compensation arrangement 29. In addition, there are a large number of input and / or output arrangements 30 to 36, which are arranged as interface circuits between auxiliary inputs and / or auxiliary outputs of the multifunction counter and so-called PORT connections of the microcomputer 26.



  The liquid crystal display LCD is preferably a customer-specific display with special display images, e.g. Numbers, a key, a clock, etc. Driver 28 outputs are e.g. Connected via a 32-bit and a 4-bit bus connection 28a and 28b to a bus input of the liquid crystal display LCD, which enables the latter to be multiplexed four times. The driver 28 feeds the arrangement 29 with a BIAS supply voltage; GND, while three voltage outputs of the arrangement 29 are each connected to a separate input VLC0 or VLC1 or VLC2 of the driver 28. The arrangement 29 supplies the voltage levels required by the driver 28 and corrects the reading angle of the liquid crystal display LCD as a function of the temperature.

  The calendar clock 27 shows the time (in hours, minutes and seconds), the date (in years, months and days), weekday numbers, week numbers, summer and winter time and leap years. A quartz or an external one, from the arrangement 25 to the synchronization input SYNC of the clock circuit 27; 28; 29 supplied synchronization signal. If the latter is faulty, the quartz is automatically switched over.



  In addition to a central processor CPU, the microcomputer 26 also has at least one read / write memory RAM, a read-only memory ROM and an electrically erasable programmable read-only memory E. <2> PROM as well as several input and / or output interface circuits, so-called PORTS. It always works as a master computer and processes peripheral signals, from which it forms energy and / or power values, which it passes on to the liquid crystal display LCD and / or to output arrangements (e.g. 34, 35 and 36) if necessary. Billing data is stored every time there is a power failure and periodically in the programmable read-only memory E <2> PROM saved captive.



  Arrangements 30 and 31 are e.g. Multi-bit input arrays, while array 32 e.g. is a multi-bit output arrangement. The arrangements 30 and 32 each contain an optocoupler or an electromagnetic relay per bit for the purpose of electrical isolation, the light-emitting diode of the optocoupler or the relay coil forming an input and the phototransistor of the optocoupler or the relay contact forming an output of the arrangement 30 and 32, respectively . The arrangement 30 is arranged as an interface circuit between a bus input 30a of the multifunction counter and the microcomputer 26, its outputs being connected to PORT inputs of the microcomputer 26 via a bus connection 30b.

  Bus input 30a preferably includes control inputs for control purposes, such as a tariff changeover, a cumulation of measured values or a time limit for a maximum measurement. The arrangement 31 contains a push button per bit, which is connected via a line of a bus connection 31 a to a PORT input of the microcomputer 26. A first, freely accessible pushbutton is preferably used to call up the display, while a second, sealed pushbutton is used to accumulate measured values or to switch between winter and summer seasons. With both pushbuttons together e.g. certain parameters can also be programmed, e.g. the time or date of the calendar clock 27.

  The arrangement 32 is arranged as an interface circuit between the microcomputer 26 and a bus output 32a of the multifunction counter, PORT outputs of the former being connected to inputs of the arrangement 32 via a bus connection 32b. The bus output 32a preferably contains control outputs, with the aid of which e.g. Loads or control inputs can be controlled by additional multifunction counters.



   Arrangements 33 and 36 are e.g. Serial 1-bit output arrangements, which are constructed similarly to the arrangement 32, with the difference that the arrangement 36 contains only a single optocoupler and the arrangement 33 contains only a single electromagnetic relay. A contact e of the latter forms a two-pole auxiliary output 33a of the multifunction counter, while a two-pole PORT output of the microcomputer 26 is connected to the associated relay coil via a two-pole connection 33b. An input of the arrangement 36 is fed via a two-pole connection 36a from a PORT output of the microcomputer 26 and its output is routed to a two-pole auxiliary output +/- r53 of the multifunction counter. The auxiliary output r53 provides, e.g. for remote counting purposes, fixed quantity pulses, i.e. Pulses per kWh.



  The arrangements 34 and 35 are standardized serial interface circuits, both of which basically perform the same function. The former is preferably an optical interface circuit OPT and the latter is preferably a current loop interface circuit CS. Outputs of the arrangements 34 and 35, which face the microcomputer 26, are connected via a common single-pole change-over switch 37 to a PORT input of the microcomputer 26, either the associated output signal of the arrangement 34 or the associated output signal of the arrangement 35 as the signal RxD relevant PORT input of the microcomputer 26 is supplied. A control input of the changeover switch 37 is controlled by a control signal SEL present at a further PORT output of the microcomputer 26, which selects the arrangement 34 or 35.

  In contrast, inputs of the arrangements 34 and 35 which face the microcomputer 26 are connected to one another and are fed by a PORT output of the microcomputer 26 with a signal TxD. An optical output 34a and an optical input 34b of the arrangement 34 each form an optical auxiliary input or auxiliary output of the multifunction counter, while the arrangement 35 has a two-pole connection 35a, which serves as a +/- auxiliary input / output of the multifunction counter. The interface circuits OPT and CS serve e.g. for bidirectional communication with reading and / or parameterization devices. The OPT interface circuit preferably represents an asynchronous interface according to DIN standard 66258, in which protocols according to IEC standard 1107 are normally processed. However, other protocols are also possible on customer request.

  In contrast, the interface circuit CS is an internally galvanically isolated two-wire interface for communication via a plug connection.



  The electricity meter 20; 21; 22 measures active energy and / or reactive energy and / or apparent energy. When measuring a single type of energy, for each phase it has a voltage / current converter 20 belonging to the relevant phase and a measuring unit 21 belonging to the respective phase. It also has a central signal processing arrangement 22 that is common to all phases. In contrast, when measuring two or three different types of energy, there are twice as many components 20 and 21.

  In the following and in FIG. 1, the assumption applies that the electricity meter 20; 21; 22 is a pure active energy three-phase electricity meter which has three voltage / current converters 20 and three measuring units 21 and is connected to four wires N (neutral conductor), R, S and T of an electrical power supply network which is connected via the overvoltage Protective arrangement 23 feeds four feed inputs R1, S1, T1 and N1 of supply device 24 and four feed inputs R2, S2, T2 and N2 of arrangement 25. To prevent overvoltages and / or surge voltages, the overvoltage protection arrangement 23 preferably contains one voltage-dependent resistor per phase, which is arranged in each case between the relevant phase and the neutral conductor N.

  To filter very fast line-bound interference signals or interference voltage peaks, suppressor diodes or inductors for damping high-frequency currents can also be present.



  Among other things, four DC voltages VCSP, VDD, GND (0 volt) and VSS, two reset signals POR and rst, a power reserve voltage GARES for the calendar clock 27 and an interruption signal INTP for the microcomputer 26 are generated in the supply device 24. VCSP is e.g. 10 volts, VDD e.g. 5 volts and VSS e.g. -5 volts. The three direct voltages VDD, GND and VSS feed all measuring units 21 as well as the arrangements 22 and 25. The two direct voltages VDD and GND feed the microcomputer 26, the clock circuit 27; 28; 29, the input and / or output arrangements 30, 31, 34 and 35 and, if present, the ripple control receiver RCR. The two direct voltages VCSP and GND feed the output arrangements 32, 33 and 36.



  The reset signal rst sets the arrangement 22 via input W and the reset signal POR the microcomputer 26, the clock circuit 27; 28; 29 and, if necessary, the ripple control receiver RCR. The power reserve voltage GARES is fed to a first input and a reset signal RST present at a further PORT output of the microcomputer 26 to a second input of a power reserve arrangement 40, the output of which is connected to an input RES of the clock circuit 27; 28; 29 is connected. The interrupt signal INTP is routed to a further PORT input of the microcomputer 26.



  In a three-phase electricity meter 20; 21; 22, which measures a single type of energy, feeds each phase voltage of the energy supply network via the overvoltage protection arrangement 23 directly, if an active energy is measured, or via a subsequent 90 ° phase shifter, not shown in FIG. 1, if a reactive energy is measured Input of the voltage / current converter 20 belonging to the relevant phase.



  The internal structure of the measuring units 21 is not shown in the drawing, since it is known at least from US Pat. No. 4,742,296 or US Pat. No. 4,728,886. Each measuring unit 21 contains a preferably U-shaped current loop 21a, which is either directly from an associated phase load current iR or iS or iT of the energy supply network (see FIG. 1) or via an associated current transformer (not shown) with a phase associated with this -Last current iR or iS or iT proportional current is fed. Within each measuring unit 21 belonging to a phase, a Hall element (not shown) is preferably arranged between the parallel current conductors of the current loop 21a, the current input of which is fed by a supply current which is proportional to a phase voltage uR or uS or UT of the phase in question.

   For this purpose, an output of the voltage / current converter 20 belonging to the respective phase is connected to a first pole of the current input concerned and the output of the overvoltage protection arrangement 23 belonging to the neutral conductor N is connected to a second pole of this current input. Since the magnetic field to which the Hall element is exposed is proportional to the associated phase load current iR or iS or iT, the output voltage of the Hall element in question is proportional to the measured power value uR.iR or uS.iS or UT.iT respectively associated phase. Within each measuring unit 21, its Hall element is followed by a voltage / frequency converter, not shown, in which the associated power value uR.iR or uS.iS or uT.iT is converted into a proportional frequency fR or fS or fT.

  At the output of the voltage / frequency converter of the three measuring units 21, which is also the signal output OES of the respective measuring unit 21, there is a measuring signal MINP1 or MINP2 or MINP3, which consists of pulses whose frequency fR or fS or fT is in each case proportional to the power value uR.iR or uS.iS or uT.iT measured in the relevant phase by the associated measuring unit 21. The measurement signals MINP1, MINP2 and MINP3 are each conducted to a separate signal input 22a or 22b or 22c of the arrangement 22. Each measuring unit 21 is calibrated before it is installed in the multifunction counter.

  The temperature dependency of the transmission factor of each Hall element can either be compensated for by an equally large temperature dependency of a reference voltage contained in the downstream voltage / frequency converter or by means of the temperature dependence of the semiconductor resistance of the Hall element. In the latter case, a temperature-dependent resistor is connected in parallel to the feed input of the Hall element, which derives a temperature-dependent portion of the feed current of the Hall element. As the temperature increases, the transmission factor of the Hall element increases, but at the same time the semiconductor resistance of the Hall element also increases, so that the supply current of the latter decreases accordingly.

  With the value of the temperature-dependent resistance arranged in parallel, the two opposing influences can be set to be of the same size, so that the overall transmission of the Hall element becomes temperature-independent.



  In addition to using the Hall element to measure the power values, it is also possible to use other measuring principles. E.g. can also be inductively coupled to each U-shaped current loop 21 a according to US Pat. No. 4,810,989, the values diR / dt or diS / dt or diT / dt of the derivative of the first order of the phase load currents iR or iS or iT is determined, which is then converted into the values of iR or iS or iT in a downstream integrator.



  The voltage / frequency converters of the three measuring units 21 all require the same reference frequency, e.g. 4096 Hz, which is fed from a reference signal output 22d of the arrangement 22 in the form of a reference clock signal FREF, which consists of pulses as a function of time, via a clock input IRF. The reference clock signal FREF on the one hand and the measurement signals MINP1, MINP2 and MINP3 on the other are asynchronous to one another. The input side of the connections belonging to the signals FREF, MINP1, MINP2 and MINP3 is each equipped with a Schmitt trigger, which is not shown in the drawing for the sake of simplicity of the drawing.

  This allows the installation of a low-pass filter with any large phase shifts as protection against high-frequency interference, which considerably improves the robustness of the measuring arrangement against high-frequency interference.



  The arrangement 22 has two signal outputs 22e and 22f, at which a signal MDIR or MPULS is present, which is led to a separate further PORT input of the microcomputer 26. A test output TSTOUT of the arrangement 22 is e.g. connected to a cathode of a light-emitting diode 38, the anode of which is led to a cathode of a light-emitting diode 39, the anode of which is in turn connected to the direct voltage VDD. One of the two LEDs 38 and 39 is e.g. an infrared light-emitting diode that is used for transmission purposes and / or for machine-readable reading. The test output TSTOUT supplies a power-proportional frequency of rectangular pulses and serves as an optical interface to a test device in which the measuring accuracy of the measuring units 21 and the signal processing arrangement 22 can be checked.

  Instead of two light-emitting diodes 38 and 39, a plurality of light-emitting diodes can also be connected in series with the same polarity and used for a wide variety of display purposes, such as for the separate display of a high and low tariff and / or for the separate display of a positive and negative energy value. The light-emitting diodes connected in series are then preferably fed by a constant current source and are each short-circuited by a switching transistor which e.g. is switched to the rhythm of pulses which represent the data to be displayed.



  Four control outputs A, B, C and D of the arrangement 22, at each of which one of the four signals PF1, PF2, PF3 and RRST is present, are each connected to a separate control input E or F or G or H of the arrangement 25. A control output J of the latter, at which a signal rstRR is present, and three control signals ST1, ST2 and ST3 are each connected to a separate control input K or L or M or V of the arrangement 22.



  A synchronizing output SYNC of the arrangement 25 is each with a synchronizing input SYNC of the clock circuit 27; 28; 29 and the microcomputer 26, while a further PORT output of the latter, at which a signal CYC is present, is connected to a further control input P of the arrangement 25. An output of the clock circuit 27; 28; 29, at which a signal BUSY is present, is connected to a further PORT input of the microcomputer 26. If a ripple control receiver RCR is present, its input is connected to a signal output RCOUT of the arrangement 25, while three outputs of the ripple control receiver RCR, to which one of three output signals INT, UND120VO or RCROUT is present, each have a separate additional port input of the microcomputer 26 are performed.

   The ripple control signal input of the ripple control receiver RCR is automatically connected to one of the three phases of the power supply network that has no undervoltage. The ripple control receiver RCR thus receives, via the arrangements 23 and 25 and the signal output RCOUT of the latter, information which is transmitted in the form of sound-frequency pulses over a single phase of the energy supply network which has no undervoltage. A single healthy phase is sufficient to ensure the function of the run control receiver RCR. The latter filters the received signal in order to free it from interference signals such as the 50 Hz voltage signal, its harmonics and external ripple control signals. It then decodes the information received, which usually contains commands that are executed immediately or with a delay.

  The ripple control receiver RCR is preferably used, among other things, to switch tariffs. In this case, the tariff can e.g. instead of using the bus input 30a, can be controlled with the aid of certain ripple control commands received. The functionality and evaluation of the information received is the same as for known ripple control receivers.



  The calendar clock 27 can in turn also be used for tariff changes and then represents a third possibility for controlling the same.



  A bus connection SPI1 or SPI2 or SPI3 is provided for the purpose of bidirectional communication between the microcomputer 26 on the one hand and the arrangement 25 or the clock circuit 27; 28; 29 or the ripple control receiver RCR available.



  The supply device 24 shown in FIG. 2 contains an ohmic capacitive voltage divider 41, two shunt regulators 42 and 43, a buffer capacitor C1, a voltage divider 44, a series regulator 45, two monitoring arrangements 46 and 47, a power reserve voltage source 48 and optionally a light indicator 49. As already mentioned, the four feed inputs R1, S1, T1 and N1 of the feed device 24 are fed via the overvoltage protection arrangement 23 (see FIG. 1) from the power supply network with a three-phase voltage which is ohmic in the immediately downstream capacitive voltage divider 41 into a regulated DC voltage VCSP; VCSN is converted.



  The ohmic capacitive voltage divider 41 preferably contains a three-phase bridge circuit 41a consisting of six diodes D1 to D6, the two-pole direct current output of which is connected via a series resistor R1 or R2 to the first pole of a suppressor diode D7 or D8 and the first pole of one Inductor L1 and L2 is connected, the second poles of the two inductors L1 and L2 forming the inputs to the two shunt controllers 42 and 43. The second poles of the two suppressor diodes D7 and D8 are connected to one another, to the neutral conductor N1 and to a first input of the light indicator 49. The three three-phase inputs of the three-phase bridge circuit 41a are each connected via a series capacitor C2 to one of the three feed inputs R1 or S1 or

  T1 of the supply device 24 is connected, the poles of the series capacitors C2 facing away from the supply inputs R1, S1 and T1 each being additionally connected to one of three further inputs of the light indicator 49. The latter, not shown, contains a resistor / light emitting diode series connection per phase, which is arranged in each case between the relevant phase and the neutral conductor N1, with each light emitting diode preferably having a reflux diode connected in parallel in the opposite direction.



  The potential at the neutral conductor N1 is e.g. the ground potential GND. The shunt regulator 42 is arranged between the positive output pole and the neutral conductor N1 and the second shunt regulator 43 between the neutral conductor N1 and the negative output pole of the ohmic capacitive voltage divider 41. The DC voltage VCSP; GND is a positive voltage, which is regulated in the shunt regulator 42 and charges the buffer capacitor C1 connected in parallel with the latter for the purpose of energy storage, which is used for data recovery in the event of a possible mains voltage failure. It also feeds the voltage divider 44 connected in parallel, in which the DC voltage VCSP; GND is reduced to a positive DC voltage VCSDIV. The latter in turn feeds an input to the monitoring arrangement 47.

  The DC voltage VCSN; In contrast, GND is a negative voltage, which is regulated in the second shunt regulator 43. The DC voltage VCSP; VCSN feeds the input of series regulator 45, which converts it into an additionally regulated DC voltage VDD; VSS converts. The DC voltage VDD; GND supplies the two monitoring arrangements 46 and 47 as well as the power reserve voltage source 48 in a two-pole manner. A second two-pole supply input of the latter is fed by a supercap, an accumulator or a battery 48a. The monitoring arrangement 46 monitors the DC voltage VDD; GND and generates at its output the reset signal POR, which among other things also feeds an input of a low-pass filter 50, where it is filtered and converted into the reset signal rst.

  The reset signal POR is a logic signal for starting the microcomputer 26 as soon as the DC voltage VDD; GND has exceeded a predetermined threshold. It also puts the microcomputer 26 in a controlled state as soon as the DC voltage VDD; GND has fallen below a predetermined threshold. The monitoring arrangement 47 monitors the DC voltage VCSDIV; GND and generates the interrupt signal INTP at its output. The latter is generated as soon as the DC voltage VCSDIV; GND has exceeded a specified value and it is ensured that enough energy is saved for any data recovery. It is also used to trigger data recovery in the event of a power failure.

  The power reserve voltage source 48, at the output of which the power reserve voltage GARES is present, supplies the energy for the operation of the clock circuit 27; 28; 29 and thus the calendar clock 27 during a power failure.



  3 is processed via a separate input from the direct voltages VDD, GND and VSS and from the signals rstRR (via input K), ST1 (via input L), ST2 (via input M), ST3 (via input V) and rst (via input W). It contains an oscillator 51, which is preferably a quartz oscillator, a frequency divider 52, a signal evaluation arrangement 53 per phase, a synchronizing arrangement 54 per phase, a counter 55, three OR gates 56, 57 and 58, a nand Gate 59, three frequency dividers 61, 62 and 63, a pulse shaper 64, three Nand gates 65, 66 and 67 and a driver 68.



   The oscillator 51 generates pulses whose frequency is e.g. 32, 768 kHz (2nd < <1> <5>> Hz) and which are fed to an input of the downstream frequency divider 52, where the frequency is divided down in order to generate e.g. four internally required clock signals CL1, CL2, CL3 and CL4 as well as the reference clock signal FREF, the latter being fed to the three measuring units 21 via the output 22d of the arrangement 22 (see FIG. 1). The frequencies of the signals FREF, CL1, CL2, CL3 and CL4 are preferably 4096 Hz (2nd <1> <2> Hz), 32 kHz, 500 Hz, 32 Hz, 1 Hz. In order to avoid synchronization problems, the pulses of the clock signal CL1 are preferably out of phase by half a period with respect to the pulses of the same frequency generated by the oscillator 51.



  The signals CL1 and rst each feed one input of the components 53, 54, 55, 61, 62, 63 and 64, the signals ST3, CL4 and rstRR each an input of the three arrangements 53, the signal CL2 an input of the pulse shaper 64 and Signals ST2 and ST3 each have a separate input to the frequency dividers 62 and 63. The three outputs A, B and C of the arrangement 22, at each of which one of the phase failure signals PF1 or PF2 or PF3 is present, are each by an output PF three arrangements 53 are formed. Each output RR of the three arrangements 53, at which a reverse run signal RR1 or RR2 or RR3 is present, is connected to a separate input of the OR gate 58, the output signal RRST of which is led to the output D of the arrangement 22. One output CR each of the three arrangements 53, at each of which an idle signal CR1 or CR2 or

  CR3 is present, is led to a separate input of the nand gate 59, the output signal TCR of which feeds a first input of the nand gate 67.



  The measuring signal MINP1 or MINP2 or MINP3 at the output of the measuring unit 21 belonging to a phase (see FIG. 1) feeds a signal input MINP of the downstream associated with the respective phase via an input 22a or 22b or 22c of the arrangement 22 Arrangement 53, in which it is converted into two signals MPOS and MNEG, both of which are routed to a separate input of the synchronizing arrangement 54 belonging to the relevant phase, each having a first and a second output. The first outputs of the three arrangements 54 are each connected to separate inputs of the OR gate 56 and the second outputs of the three arrangements 54 are each connected to separate inputs of the OR gate 57. Three control outputs of the counter 55 are connected to a control input of one of the three arrangements 54.

  The outputs of the two OR gates 56 and 57 are each connected to a separate input of the frequency divider 61, the two outputs of which are routed via the frequency divider 62 and 63 to a separate input of the pulse shaper 64, which has two outputs on which the Signal MDIR or MPULS is present and the two two outputs 22e and 22f of the arrangement 22 form. The signal MDIR, inverted, feeds a first input of the nand gate 65, at the second input of which the control signal ST1 is present and whose output is connected to a first input of the nand gate 66, at the second input of which the signal MPULS is present and the output of which second input of the nand gate 67 is guided. The output of the latter is connected to the test output TSTOUT of the arrangement 22 via the driver 68.



  The duration of the pulses of the measurement signals MINP1, MINP2 and MINP3 and the signals MPOS and MNEG is preferably 32 ms. The signals MPOS and MNEG each consist of pulses, the frequency of which is proportional to the measured positive and negative power. If a pulse of the signal MPOS or MNEG appears at one of the two outputs of an arrangement 53, this is temporarily stored in the arrangement 54 belonging to the relevant phase until the moment at which the relevant phase is queried. The counter 55 counts to "three" in each case and cyclically polls the stored pulses of the signals MPOS and MNEG of the three phases in the arrays 54 in order to immediately forward the query value found to the associated output of the arrangement 54 in question. Returns a phase of negative-value pulses, i.e.

  Pulses of the signal MNEG, and another phase positive-value pulses, i.e. Pulses of the signal MPOS, these pulses do not cancel each other out, but all pulses are passed on to the associated OR gate 56 or 57. The three arrangements 54 and the two OR gates 56 and 57 together form two time multiplexers 54; 56 and 54; 57, whose common control device is counter 55. One of the two time multiplexers 54; 56, the output of which is the output of the OR gate 56, is present for the positive-value pulses and the other, the output of which is the output of the OR gate 57, for the negative-value pulses.

  The two time multiplexers 54; 56 and 54; 57 are controlled by the counter 55 in such a way that the three arrangements 54 pass their pulses one after the other to the two OR gates 56 and 57, where they appear at different times, so that the output pulses of all arrangements 53 belonging to different directions of energy flow for the purpose of energy Summation in each of the two time multiplexers 54; 56 and 54; 57 can be connected in series in the time multiplexer. The output frequency of the OR gate 56 or 57 is then in each case equal to the sum of the associated output frequencies of the three arrangements 54 and accordingly proportional to the measured positive or negative three-phase power.

  A key advantage of this type of digital addition is the robustness of the associated digital interface against interference, the flexibility in the choice of the adjustment concept, the division of the analog and digital functions into two specialized customer-specific circuits and finally a smaller number of connections of the different modules. A frequency irregularity resulting from the pulse addition can be reduced to a tolerable small value by choosing a sufficiently small energy value for the pulses.



   One output each of the two time multiplexers 54; 56 and 54; 57 is connected via the downstream frequency dividers 61 and 62 or 61 and 63 to a separate input of the microcomputer 26. In the frequency dividers 61 and 62 or 61 and 63, the sum values found, i.e. the output frequencies of the OR gates 56 and 57 divided to obtain a certain pulse weight or counter constant. In the frequency divider 61, the output frequencies of the OR gates 56 and 57 are preferably divided by sixteen. It then takes sixteen pulses at the input for a pulse to appear at the output of the frequency divider 61, which in this case represents a 16 times higher energy value than a pulse at the input of the frequency divider 61. The latter is preferably a 5-bit up / down counter which operates according to the state diagram shown in FIG. 6.

  Since also with energy supply (e.g. with cos PHI <1) negative energy values can occur and only an average, e.g. B.  The frequency divider 61 also works as a low-pass filter by means of sixteen pulses, which provides information about the energy direction.  For example, change. B.  positive and negative value pulses continuously and never appear more than fifteen pulses of the same type, a pulse will never appear at the output of the frequency divider 61.  



  The two output frequencies of the frequency divider 61 are then in the frequency divider 62 or  63 divided again so that a pulse at the output of the latter is always 1 Wh positive or  corresponds to negative energy.  For this purpose, the division ratio of the two frequency dividers 62 and 63 must be programmed accordingly using the two control signals ST2 and ST3, depending on the size of the mains voltage present, 230 volts or 110 volts, and the type of measuring unit 21 used.  The division ratio is e.g. B.  at 230 volts equal to "2" (if ST2; ST3 = "11") or "4" (if ST2; ST3 = "10") and at 110 volts equal to "4" (if ST2; ST3 = "01") or "8" (when ST2; ST3 = "00").  



  In the pulse shaper 64, the duration of the pulses and pulse gaps delivered by the frequency dividers 62 and 63 are each increased to 10 ms with the aid of intermediate storage.  In addition, the pulses delivered separately for both energy directions are fed as signal MPULS to a single common output of the pulse shaper 64 and thus also to a single output 22f of the arrangement 22.  In addition, information regarding the energy direction of the pulse in question is supplied as a signal MDIR to a further output of the pulse shaper 64 and thus to the output 22e of the arrangement 22.  The signal MDIR z. B.  a logic value "one" if a simultaneous pulse of the MPULS signal belongs to a positive energy, and a logic value "zero" if a simultaneous pulse of the MPULS signal belongs to a negative energy. 

  If there is no pulse of the MPULS signal, the MDIR signal is e.g. B.  equals zero".  The pulse shaper 64 is a state machine which, for. B.  has ten states "zero" to "nine".  If no pulses are received, the pulse shaper 64 is in the "zero" state.  After a pulse is received, the pulse shaper 64 cycles through all states at the clock frequency 500 Hz of the clock signal CL2.  In state "one" the signal MDIR goes to a logic value "one" if the pulse belongs to a positive energy and in state "four" if necessary  MPULS to one.  In the "nine" state, the processed pulse is deleted and the signals MPULS and MDIR are reset to zero.  After the "nine" state, the pulse shaper 64 automatically returns to the "zero" state in order to  to process the next received pulse.  



  The control signal ST1 controls in normal operation, i. H.  if there is no idle, the signal present at the test output TSTOUT.  In normal operation, the output signal TCR of the Nand gate 59 is "one" and the Nand gate 67 is thereby continuously released.  If the control signal ST1 has a logic value "one", then the nand gate 65 is continuously released and a logic value "zero" appears at the output of the nand gate 66 and a logic value "one" at the output of the nand gate 67 only if both signals MDIR and MPULS have a logic value "one", i. H.  when the pulse of the MPULS signal belongs to a positive energy.  In this case, only positive-value pulses operate the test output TSTOUT.  The LEDs 38 and 39 connected to the latter (see Fig.  1) then only flash in the rhythm of these positive impulses. 

  If, on the other hand, the control signal ST1 has a logic value of zero, then the nand gate 65 is permanently blocked and a logic value of one at its output continuously releases the nand gate 66, so that all pulses of the signal belonging to both positive and negative energy are present MPULS reach the output of the NandGatter 67 and thus the test output TSTOUT.  In this case, the LEDs 38 and 39 connected there flash (see Fig.  1) in the rhythm of the impulses belonging to both positive and negative energy.  The two types of pulses can then no longer be distinguished at the TSTOUT test output.  Each pulse at the TSTOUT test output and each pulse of the MPULS signal have both a pulse duration and a minimum pulse gap of 10 ms each and a value of 1 Wh.  



  The idling is monitored separately in each of the three phases and, if present, is displayed as logic value "one" at the output CR of the arrangement 53 belonging to the phase in question.  If three-phase idling occurs, the output signal TCR of the nand gate 59 assumes a logic value "zero" and the output signal of the nand gate 67 continuously assumes a logic value "one".  The LEDs 38 and 39 connected to the test output TSTOUT (see Fig.  1) then no longer flash, but in this case light up continuously.  



  The in the Fig.  The signal evaluation arrangement 53 shown in FIG. 4 contains a pulse duration decoder 69, a digital low-pass filter 70, an idle suppression arrangement 71, an energy backward detector 72, a frequency divider 73 and an enable arrangement 74; 75, which consists of two AND gates 74 and 75 .  



   The pulse duration decoder 69 arranged at the input of the arrangement 53 contains two nor gates 76a and 76b, a "logic zero" counter 77, two AND gates 78a and 78b, a "logic one" counter 79, a decoder 80, an exclusive -Or gate 81 and two AND gates 82a and 82b.  The counter 77 is preferably a 3-bit counter and the counter 79 is preferably a 4-bit counter.  Their clock inputs are each fed by the clock signal CL1.  The signal input MINP of the arrangement 53 is connected to a first input of the gates 76a, 78a and 81.  The output of the latter is fed to a serial input of counter 77, the serial output of which is connected to a second input of gate 81 and a first input of gate 76b. 

  The reset signal rst is fed to a second input of the gates 76a and 76b, the outputs of which each have a reset input RS of the counter 77 or  79 are connected.  The output of gate 78a, the second input of which is connected to the serial output of counter 79, is connected to a serial input of the latter.  The serial output also forms the output PF of the arrangement 53 and is additionally connected to a first input of the gate 78b, the output of which is led to a first input of the two gates 82a and 82b.  The parallel output of the counter 79 is connected via a bus connection to a bus input of the decoder 80 which has two outputs, one of which is connected to a second input of the gate 82a or  82b is guided. 

  The outputs of the latter two each form one of two outputs of the pulse duration decoder 69.  A parallel output of counter 77 is also connected to a second input of gate 78b.  



  The pulse duration decoder 69 serves on the one hand to separate the pulses belonging to different directions of energy flow and on the other hand to block the latter pulses and to generate a missing phase display if there is a phase failure.  It thus determines in each case whether the pulses in question belong to a positive or negative direction of energy flow or whether there is a phase failure for the phase in question.  A phase failure occurs when the associated measuring unit 21 does not have a zero crossing of the associated phase voltage uR or  uS or  uT can detect.  The pulse duration decoder 69 also suppresses the pulses of the measuring signal MINP1 or signal present at the signal input MINP of the arrangement 53 or  MINP2 or  MINP3. 

  For each phase, both information relating to a determined energy flow direction and information relating to the presence of a phase failure are contained in the duration of the output pulses of the associated measuring unit 21.  The direction of energy flow is therefore contained as a pulse duration in the pulses of the three measurement signals MINP1, MINP2 and MINP3.  A pulse duration less than 3 periods of the clock signal CL1 is e.g. B.  interpreted as an interference signal and ignored.  A pulse duration of 3 to 6 periods corresponds to e.g. B.  a negative energy pulse and a pulse duration of 7 to 10 periods z. B.  a positive energy pulse during a pulse duration greater than 10 periods e.g. B.  corresponds to a phase failure. 

  A distinction between the energy flow direction is necessary for the following reasons: On the one hand, the measuring units 21 can measure the energy in both directions and for certain applications the energy impulses for both energy flow directions have to be recorded separately.  On the other hand, if there is a reactive power component in the energy supply network, the instantaneous power changes four times within a network period, ie. H.  with a high resolution of the quantization, the sign belonging to the pulses changes accordingly often.  These short-term changes in the sign of the pulses can, for. B.  can be suppressed by means of digital filters, which will be explained later.  



  The counters 77 and 79 are reset to zero by the reset signal rst.  During a pulse present at the input MINP of the arrangement 53, the latter resets the counter 77 to zero via the gate 76a, which then resets and remains out of operation for as long as the relevant pulse is present.  The counter 79 is at each start of the pulse of the measuring signal MINP1 appearing at the input MINP or  MINP2 or  MINP3 started with the help of the AND gate 78a and counts the number of periods of the clock signal CL1 during the duration of each pulse.  The count value stored in counter 79 at the end of the pulse is a measure of the pulse duration and is decoded in decoder 80.  Depending on whether the pulse duration corresponds to a negative or positive energy quantum, a logic value "one" appears on the first or  second output of decoder 80. 

  The logic value "one" is then via one of the gates 82a or  82b, if this is released by the counter 77 via the gate 78b, forwarded to the associated output of the pulse duration decoder 69.  



  If there is a phase failure, the counter 79 reaches a count value elf, which has the consequence that a logic value "zero" appears at its serial output and thus also at the output PF of the arrangement 53, as a sign that there is a phase failure.  It is used as phase failure signal PF1 or  PF2 or  PF3 via control output A or  B or  C of the arrangement 22 (see Fig.  3) forwarded to the arrangement 25 (see FIG.  1).  At the same time, the gates 78a, 78b, 82a and 82b are blocked, so that the counter 79 stops counting and the output signals of the decoder 80 no longer reach the outputs of the pulse duration decoder 69.  



  A pulse can be temporarily erased by interference signals, so that the counter 79 cannot recognize whether a real pulse end or a pulse end pretended by a pulse cancellation is present.  Therefore, the counter 77 is present, the counting process of which is started with the exclusive-OR gate 81.  As soon as a real or simulated pulse end appears at the signal input MINP, the reset of the counter 77 present via the gate 76a is canceled and a logic value "one" appears at the output of the exclusive-OR gate 81, since at the serial output of the counter 77 after the reset a logic value "one" appears and thus different logic values are present at the two inputs of the gate 81.  The counter 77 counts the pulses of the clock signal CL1 during the pulse gap present at the signal input MINP. 

   If there is a logic value zero for a pulse gap on two successive rising edges of the clock signal CL1, then it is a real pulse gap and a logic value "one" is stored in each of the first two counter flip-flops of the 3-bit counter 77.  This is decoded by means of an AND gate, not shown, so that a logic value "one" appears at the parallel output of counter 77, which, if there is no phase failure, enables gate 78b and thus also gates 82a and 82b.  As a result, the count value of the counter 79 decoded in the decoder 80, which belongs to the pulse that preceded the real pulse gap, is correctly forwarded to the output of the pulse duration decoder 69, since the counter value of the counter 79 is the real pulse duration thereof Represents impulse. 

  On the next rising edge of the clock signal CL1, a logic value "one" is then loaded into the third counting flip-flop of the 3-bit counter 77, which results in a logic value "zero" at the output of the latter, which, via gate 76b, the counter 79 to zero.  The latter is then ready to evaluate the next pulse appearing at the MINP signal input.  If, however, the pulse gap was only simulated by a pulse cancellation, a logic value "one" belonging to the current pulse reappears at the signal input MINP after the pulse cancellation has ended.  The counter 79 is started again, while at the same time the counter 77 is reset to zero via the gate 76a, which has the consequence that a logic value "zero" appears at the parallel output of the counter 77, which the gate 78b and thus also the gates 82a and 82b locks. 

  The count value of the counter 79 decoded in the decoder 80 is therefore not yet forwarded to the output of the pulse duration decoder 69, since the count value of the counter 79 does not yet correspond to the pulse duration sought before the counting process has ended.  



  "Offset" pulses are pairs of pulses, each consisting of a positive and a negative-value pulse, which in an absent magnetic field, i. H.  with an absent phase load current iR or  iS or  iT, can be generated in the measuring unit 21 belonging to the relevant phase.  In the digital low-pass filter 70 connected downstream of the pulse duration decoder 69, the "offset" pulses present in the relevant phase are eliminated, i. H.  two successive impulses must result in the same positive or  belong negative energy direction so that they are forwarded to the output of the low-pass filter 70.  A single pulse for a specific energy direction is considered an "offset" pulse and is suppressed.  The low-pass filter 70 is fed by the clock signal CL1 and the reset signal rst.  



  The arrangement 71 contains an OR gate 83, a reset arrangement 84, a counter 85, a nand gate 86 and a flip-flop 87.  Counter 85 is a 16 or 32 second counter.  The two outputs of the low-pass filter 70 are each connected to one of two inputs of the gate 83, the output of which is connected to an input of the arrangement 84 and a first input of the gate 86.  An output of the arrangement 84 is fed to a reset input RS of the counter 85.  A clock input of the arrangement 84 is fed by the clock signal CL1 and that of the counter 85 by the clock signal CL4 (1 Hz).  The control input ST3 is connected to a switch input of the counter 85. 

  A logic value "one" or "zero" applied to it takes a first counting flip-flop of the counter 85 into or out of operation, so that the counter 85 counts either sixteen or thirty-two one-second periods of the clock signal CL4.  The values "sixteen" or  "Thirty-two" seconds can thus be programmed using the control input ST3.  A non-inverting serial output Q of the counter 85 is connected to a z. B.  D input of the flip-flop 87 is connected, while its inverting serial output is connected to its serial input and to the second input of the gate 86, the output of which is led to a reset input RS of the flip-flop 87.  The clock input of the latter is fed by the clock signal CL1. 

  An inverting output of flip-flop 87 is connected to the first input of gates 74 and 75, the second inputs of which are each controlled by one of the two outputs of low-pass filter 70.  A non-inverting output Q of the flip-flop 87 forms the output CR of the arrangement 53, while the outputs of the two gates 74 and 75 form the two outputs of the arrangement 53, at which the signals MPOS and MNEG are present.  The arrangement 71 can be reset to zero with the reset signal rst.  Outputs of the low-pass filter 70 and thus of the pulse duration decoder 69 are thus via the release arrangement 74; 75 is connected to outputs of the signal evaluation arrangement 53, the release arrangement 74; 75 is controlled by an output of the idle suppression arrangement 71.  



  An idle corresponds to a state of the multifunction counter in which there is no longer a difference between a valid signal and an interference signal, e.g. B.  Noise, is noticeable.  The idle suppression arrangement 71 determines whether during a predetermined programmed time value, e.g. B.  for 16 or 32 seconds, no pulses at the output of the low-pass filter 70 or  appeared at the output of the pulse duration decoder 69.  The output signals of the latter then no longer reach an associated output of the arrangement 53 until the time interval between two successive pulses is again less than the predetermined programmed time value.  The arrangement 71 thus determines whether neither positive nor negative-value pulses have appeared at the output of the low-pass filter 70 for 16 or 32 seconds. 

  If this is the case, a logic value "zero" appearing at the inverting output of the flip-flop 87 blocks the two gates 74 and 75, so that the output signals of the low-pass filter 70 no longer reach the associated output of the arrangement 53 until the time interval between two successive pulses again less than the programmed time value "sixteen" or  "Thirty-two" seconds is.  In addition, a logic value "one" appears at the output CR of the arrangement 53 as a sign that there is an idle.  This logic value "one" is in the arrangement 22 as an idle signal CR1 or  CR2 or  CR3 each fed to an input of the nand gate 59, whose output signal TCR blocks the gate 67 when all three phases are idle (see FIG.  3). 

   The microcomputer 26 in turn receives no information about the status of the idle or  idle suppression.  



  For each pulse that appears at one of the two outputs of the low-pass filter 70, a short pulse gap is generated in the arrangement 84, which briefly resets the counter 85 to zero, so that it then, starting from zero, the time elapsing until the next pulse can be determined by counting the pulses of the clock signal CL4.  If a next pulse appears before the counter 85 reaches the count "sixteen" or  Has reached "thirty-two", then it sets the flip-flop 87 to zero via the gate 86, if this has not already been reset to zero. 

  On the other hand, the counter 85 reaches the count value "sixteen" or  "Thirty-two", the gate 86 is blocked and a logic value "one" is loaded into the flip-flop 87 with the next rising edge of the clock signal CL1, which results in a logic value "one" at the output CR of the arrangement 53 as a sign that there is an idle state .  At the same time, gates 74 and 75 are blocked.  The counter 85 can only be reset to zero by means of the reset signal rst, whereupon the next pulse at one of the two outputs of the low-pass filter 70, via the gates 83 and 86, resets the flip-flop 87 to zero.  



  The output signals of the two gates 74 and 75 are still fed to the frequency divider 73 in the arrangement 53, where their frequencies are still z. B.  to be divided by four.  The frequency divider 73 can be reset to zero by means of the reset signal rst and its clock input is fed by the clock signal CL1.  The frequency divider 73 is preferably a 3-bit up / down counter, which according to the in the Fig.  7 shown state diagram works.  Since negative energy values can occur for a short time even when purchasing energy and only an average value, e.g. B.  The frequency divider 73 also works as a low-pass filter via four pulses, which provides information about the energy direction.  For example, change. B.  positive and negative value pulses continuously and never appear more than three pulses of the same type, a pulse will never appear at the output of the frequency divider 73. 

  The pulses at the output of the latter have a four times greater energy value than the pulses at its input.  If there are only pulses of a single energy direction, four pulses are required at the input in order to generate a pulse at the output of the frequency divider 73.  



  Inputs of the energy backward detector 72 are via the frequency divider 73 at the outputs of the release arrangement 74; 75 and thus also connected to the outputs of the arrangement 53.  The energy backward detector 72 is used to determine whether, over a predetermined time, pulses have appeared at the outputs of the arrangement 53 which belong exclusively to a negative energy flow direction.  



  The energy backward detector 72 includes an AND gate 88, two NOR gates 89 and 90, a frequency divider 91 and a flip flop 92.  The clock signal CL1 feeds the clock inputs of the flip-flop 92 and the frequency divider 91.  The frequency division ratio of the latter can be set to the value "eight" or by means of a logic value "one" or "zero" at the control input ST3.  "Sixteen" can be programmed by putting an additional counting flip-flop in or out of operation in the frequency divider 91.  Only the output pulses of the frequency divider 73 belonging to negative energy values are fed to an input of the frequency divider 91 and their frequency there by "eight" or  "Sixteen" shared.  The output of the frequency divider 91 is connected to an input of the flip-flop 92, while its reset input RS is driven by the output of the gate 89. 

  The reset input RS of the flip-flop 92 is driven by the output of the gate 90.  The Q output of the flip-flop 92 forms the output RR of the arrangement 53 and is simultaneously connected to a first input of the gates 88 and 89.  The reset signal rstRR supplied by the arrangement 25 (see FIG.  1) is led to a second input of gate 88, the output of which is connected to a first input of gate 90.  The reset signal rst feeds a second input of gates 89 and 90.  The output pulses of the frequency divider 73 belonging to positive energy values are led to a third input of the gate 89.  



  Reverse energy is present if only negative energy values are measured over a certain time and e.g. B.  for a total of 1 Wh negative energy is determined, which is eight or  corresponds to sixteen pulses at the input of the energy backward detector 72.  So step there one after the other without any positive impulses in between, eight or  sixteen negative-value pulses, their frequency in the frequency divider 91 is divided by eight or  divided sixteen, d. H.  after eight or  A logic value "one" appears at sixteen such pulses at the serial output of the frequency divider 91.  The logic value "one" is then stored in the flip-flop 92, where it appears at the Q output and thus also at the output RR of the arrangement 53, as a sign that there is a reverse energy direction. 

  At the same time, the frequency divider 91 is reset to zero via the gate 89 and the gate 88 is released for the reset signal rstRR.  If, in the meantime, before a logic value "one" reaches the serial output of the frequency divider 91, a positive-value pulse appears at the output of the frequency divider 73, then this resets the frequency divider 91 to zero via the gate 89, so that it starts again at zero when dividing the frequency .  The reset signal rst resets the frequency divider 91 and the flip-flop 92 via the gates 89 and 90.  



  The output signal RRST of the OR gate 58 (see Fig.  3) assumes a logic value "one" if reverse energy was measured in at least one phase.  Its information content is transferred into the most significant bit of register 115 and, with a delay, into the most significant bit of shift register 120 (see FIG.  5) in order to then be transferred to the microcomputer 26 via the bus connection SPI1 (see FIG.  1).  After each such reading, in which the status of the output signal RRST was "one", the latter provides via the bus connection SPI1 and an AND gate 114 (see FIG.  5) using the output signal rstRR of the latter in each arrangement 53 the flip-flop 92 (see Fig.  4) return to zero.  After this reset, the frequency divider 91 is released again. 

   On the other hand, if the microcomputer 26 reads a "zero" status of the output signal RRST, the flip-flop 92 is not reset.  There may be a reverse energy measurement in all three phases, but the microcomputer 26 cannot determine which phase the reverse energy measurement is in.  



  The in the Fig.  Fault detection arrangement 25 shown in FIG. 5 contains two three-phase voltage dividers 93 and 94, six Schmitt triggers 95 to 100, two time window arrangements 101 and 102, three event detectors 103 to 105, a single-pole switch 106 and  107 or  108 per phase, control electronics 109, optionally a two-phase failure display arrangement 110, three event counters 111 to 113, an AND gate 114, a register 115, an amplifier 116, a low-pass filter 117, a converter 118, an inverter 119, a shift register 120 and a driver 121.  



  Within the arrangement 25, the four from the power supply network via the overvoltage protection arrangement 23 (see FIG.  1) fed supply inputs R2, S2, T2 and N2 each with a separate input of both the three-phase voltage divider 93 and the three-phase voltage divider 94.  Each three-phase voltage divider 93 and 94 contains e.g.  B.  one voltage divider consisting of two resistors per phase and therefore one output per phase.  It shares the relatively high phase voltage of z. B.  220 volts or 110 volts of the power supply network down to a voltage value common in electronic devices.  



  The three outputs of the three-phase voltage divider 94 are each via one of the Schmitt triggers 95 to 97, each with a separate input of the time window arrangement 101, and via one of the Schmitt triggers 98 to 100, each with a separate input of the time window arrangement 102 connected.  The arrangements 101 and 102 each have one output per phase.  The Schmitt trigger 95 or  96 or  97 generates a logic value "one" at its output when it detects an undervoltage for the phase voltage associated with it, i.  H.  determines that this has a certain value, e.g. B.  90% of the nominal voltage. 

  Likewise, the Schmitt trigger 98 or  99 or  100 each have a logic value "one" at its output if it detects an overvoltage for the phase voltage associated with it, ie. H.  determines that this has a certain value, e.g. B.  110% of the nominal voltage.  



  The three outputs of the time window arrangement 101 are each connected to a separate input of the event detector 103, while the three outputs of the time window arrangement 102 are each connected to a separate input of the event detector 104.  Event detectors 103 and 104 also have one output per phase.  If the undervoltage or  If the overvoltage for a certain phase lasts longer than 500 ms, the associated logic value one present at the output of the relevant Schmitt trigger in the relevant event detector 103 or  104 saved. 

  For this purpose, the output signals of the six Schmitt triggers 95 to 100 in the time window arrangement 101 or  102 sampled every 30 microseconds and, if a logic value one appears once in a time window lasting 31.25 ms, as an event taking place in the associated time window arrangement 101 or  102 taken over.  If the event in question occurs 16 times in a row, i.e.  H.  if the event is present continuously for 500 ms, then the relevant event detector 103 or  104, which counts the successive occurrence of the event, a logic value one stored as a sign that an undervoltage or  Overvoltage of the phase concerned occurred during 500 ms.  This sufficiently long occurrence of a lower or  Overvoltage is separated for each phase in the event counter 111 or  Counted 112. 

  For this purpose, the three outputs of the event detector 103 or  104 each to a separate input of the event counter 111 or  112 led.  In addition, the three outputs of the event detector 103 are each connected to a separate input of the control electronics 109 and, if present, the two-phase failure display arrangement 110.  The latter determines and indicates a sufficiently long undervoltage in two phases.  That input of the arrangement 25 at which the signal CYC originating from the microcomputer 26 is present is connected to a further input of the arrangement 109, while three control outputs of the latter each have a control input of one of the three switches 106 or  107 or  108 is connected.  



  The three outputs of the three-phase voltage divider 93, at each of which a signal RCIN1 or  RCIN2 or  RCIN3 is pending, are each one of the three switches 106 or  107 or  108 is connected to the signal output RCOUT of the arrangement 25 and to an input of the amplifier 116.  The latter, the low-pass filter 117 and the converter 118 are connected in series in the order given.  The converter 118 is e.g. B.  a comparator or a zero detector.  The output of converter 118 forms the synchronization output SYNC of arrangement 25.  The control electronics 109 controls the switches 106 to 108 such that only a single one of these switches 106 or  107 or  108 is closed, namely one that belongs to a phase of the energy supply network that does not have an undervoltage lasting 500 ms. 

  Accordingly, a phase voltage of the power supply network which is reduced in the three-phase voltage divider 93 and does not have an undervoltage lasting 500 ms is always present during operation at the synchronizing output SYNC of the arrangement 25 and at the input of the amplifier 116.  This sinusoidal phase voltage is amplified in amplifier 116, filtered in low-pass filter 117 and thus freed from interference signals, such as network harmonics and / or ripple control signals, in order to be converted in converter 118 into a digital signal which is regular in function of time and which is used to synchronize the microcomputer 26 and the clock circuit 27; 28; 29 is used.  With at least one connected functional phase, their z. B.  50 Hz phase voltage as the time base for the microcomputer 26 and the calendar clock 27.  



   The signal processing arrangement 22 supplies the arrangement 25 via the three inputs E, F and G for each phase a phase failure signal PF1 or  PF2 or  PF3, and the signal RRST via input H.  The three phase failure signals PF1, PF2 and PF3 are handled in two ways.  On the one hand, they are fed to three separate inputs of the event detector 105, which detects them as events, which are then counted in the event counter 113, the three inputs of which are each connected to a separate output of the event detector 105.  On the other hand, the logic values of the three phase failure signals PF1, PF2 and PF3 and the signal RRST in the four most significant bits of register 115 are read for status purposes.  



  The event counters 111, 112 and 113 are e.g. B.  4-bit counter and then each have four outputs.  These outputs of the event counters 111, 112 and 113 and the four inputs E, F, G and H of the arrangement 25 are each connected to a separate input of the register 115 in the order given, starting with the least significant bit LSB and ending with the most significant bit MSB , just as many, d.  H.  has a total of sixteen outputs, which in turn are each connected to a separate parallel input of the shift register 120, in which sixteen bits 0 to 15 are thus stored.  The corresponding bits of the event counters 111 to 113 as well as the signals PF1, PF2, PF3 and RRST are stored in the register 115 if this is e.g.  B.  by means of a logic value "one" pending at an enable input EN of register 115.  



  The bidirectional bus connection SPI1 has four conductors.  Via three of these conductors, the microcomputer 26 feeds the arrangement 25 with one of three signals CEB ("chip enable"), SCK ("system clock") and MOSI ("master out, slave in"), while the arrangement 25 via the fourth conductor feeds the microcomputer 26 with a signal MISO ("master in, slave out").  The microcomputer 26 selects the arrangement 25 as the master computer with the aid of the signal CEB and supplies the latter with the clock signal SCK.  



  The signal CEB is an enable signal and feeds the enable input EN of the register 115 and, via the inverter 119, an enable input of the driver 121 and a first input of the AND gate 114.  A second input of the latter is fed by the signal RRST, while an output of the AND gate 114 forms an output J of the arrangement 25, at which the reset signal rstRR is present.  The signal SCK is a clock signal and is fed to a clock input of the shift register 120, while the signal MOSI is fed to a serial signal input thereof.  A serial signal output of the shift register 120 is connected to an input of the driver 121, at whose output the signal MISO is present. 

  The shift register 120 is loaded in parallel with the content of the register 115 by means of the signal CEB at a suitable moment, so that the content stored in the shift register 120 is then serially bit by bit via the driver 121 and the associated conductor of the bidirectional bus connection SPI1 as a signal MISO to the microcomputer 26 can be transferred.  Conversely, information bits of the latter can be transmitted time-serially bit by bit as a signal MOSI from the microcomputer 26 via the associated conductor of the bidirectional bus connection SPI1 to the arrangement 25, where they are shifted into the shift register 120 by means of the clock signal SCK via the serial input and temporarily stored.  In practice, however, the MOSI signal is only used for test purposes.  



  In the register 115 of the arrangement 25, the presence or absence of overvoltages and undervoltages and of phase failure signals PF1, PF2 and PF3, a count of the latter and a collective result RRST of a reverse energy detection are thus temporarily stored for all phases.  The information temporarily stored in register 115 is then adopted in shift register 120 for the purpose of subsequent time-serial transmission to microcomputer 26 via bus connection SPI1.  The measurement signals MINP1, MINP2 and MINP3 of the three measurement units 21 are transmitted from the respective measurement unit 21 to the arrangement 22 via a single-wire connection (see FIG.  1).  However, this transmission can also take place via a standardized bidirectional bus connection SPI4, which is constructed similarly to the bus connection SPI1. 

  This has the advantage that the correspondingly modified measuring unit, which is referred to below as 221, in addition to energy measurement values, also digitized instantaneous values of the associated phase load current iR or  iS or  iT and the associated phase voltage uR or  uS or  uT can deliver.  



  In this case, the arrangement 22 contains an additional microcomputer 222, which works as a master computer, and the measuring units 221 each have an SCK, a MOSI, a BCIR ("bidirectional interrupt request") and an SSB in addition to the clock input IRF Input ("sensor select bar") and a MISO output.  The by the oscillator 51 and the frequency divider 52 (see Fig.  3) formed clock generator 51j52 feeds the microcomputer 222 with a clock signal 223.  If there are several measuring units 221, the SSB input serves in each case to select the relevant measuring unit 221 and to put its MISO and MOSI connections into operation.  The BCIR input can be used for start-up purposes or for interrupt purposes.  



  As in Fig.  8, each measuring unit 221 preferably contains five registers 224, 225, 226, 227 and 228, which are connected in series in the order given, each form an output shift register and preferably each have eight bits.  The serial output of register 228 is connected to the MISO output of the relevant measuring unit 221, while its MOSI input is connected to a serial input of an input shift register 229, the serial output of which is connected to a serial input of register 224.  A parallel output of the input shift register 229 is connected to a parallel input of a register 230 of control logic 231.  The two registers 229 and 230 preferably have 4 bits and serve as serial programming data register SPDR or  as mode register MREG. 

   In register 228 z. B.  a measured energy value (5 bits) and three flags (3 bits) are stored.  The latter show e.g. B.  the result of a Hall impedance measurement, a zero voltage measurement and an error determination.  In register 227 z. B.  the most significant and in register 226 the least significant current byte CMSB or  CLSB of a 16-bit sample value of an associated phase load current iR or  iS or  iT saved.  In register 225 z. B.  the most significant and in register 224 the least significant voltage byte VMSB or  VLSB of a 16-bit sample value of an associated phase voltage uR or  uS or  uT saved.  



  The SCK inputs of the three measuring units 221 are connected to one another and are supplied with the same clock signal SCK by the microcomputer 222 via a first conductor of the bidirectional bus connection SPI4.  The MOSI inputs of the three measuring units 221 are connected to one another and are fed by the microcomputer 222 with the same signal MOSI via a second conductor of the bidirectional bus connection SPI4.  The MISO outputs of the three measuring units 221 are connected to one another and feed the microcomputer 222 with a same signal MISO via a third conductor of the bidirectional bus connection SPI4.  The SSB input of the three measuring units 221 is each with a separate output SSB1 or  SSB2 or  SSB3 of the microcomputer 222 connected.  



  The measuring units 221 have two operating modes, which are each stored in the mode register 230.  In the first mode, the information is transmitted from a measuring unit 221 to the microcomputer 222 at a predetermined clock frequency.  In the second mode, the microcomputer 222 queries the information at its own clock frequency and a measuring unit 221 only outputs its information on request from the microcomputer 222.  In the first, in Fig.  9 mode, the clock inputs IRF of the three measuring units 221 are connected to one another and are generated by the clock generator 51; 52 fed with the same reference clock signal FREF.  In addition, the BCIR inputs of the three measuring units 221 are connected to one another and to a connection INT of the microcomputer 222. 

   In the second, in Fig.  10 shown mode, the clock inputs IRF of the three measuring units 221 from three separate outputs of the clock generator 51; 52 fed with the same clock frequency and the BCIR input of the three measuring units 221 is each with a separate output SC1 or  SC2 or  SC3 of the microcomputer 222 connected.  


    

Claims (10)

      1. Multi-function meter with an electricity meter (20; 21; 22), which for each phase has a measuring unit (21) belonging to the respective phase, the output pulses of which have a frequency (fR, fS, fT), each of which is proportional to the one in question Phase measured by the associated measuring unit (21) power value (uR.iR, uS.iS, UT.iT), characterized in that for each phase, both information regarding a determined energy flow direction and information regarding the presence of a phase failure in the Duration of the output pulses of the associated measuring unit (21) is included, a phase failure occurring if the associated measuring unit (21) cannot detect a zero crossing of the associated phase voltage (uR, uS, UT) for the phase in question,  and that in each phase of the associated measuring unit (21) there is a signal evaluation arrangement (53) associated with the relevant phase, at the input of which a pulse duration decoder (69) is arranged on the one hand for the purpose of separating the pulses belonging to different energy flow directions and on the other hand for the purpose of blocking the latter pulses and generating a phase failure indicator if there is a phase failure. 2nd Multifunction counter according to Claim 1, characterized in that outputs of the pulse duration decoder (69) are connected to the output of the signal evaluation arrangement (53) via a release arrangement (74; 75), the release arrangement (74; 75) being connected to an output of an idle suppression Arrangement (71) is controlled, which determines whether no pulses have appeared at outputs of the pulse duration decoder (69) during a predetermined programmed time value, and that output signals of the latter no longer reach an associated output of the signal evaluation arrangement (53), until the time interval between two successive pulses is again less than the predefined programmed time value. 3rd Multifunction counter according to Claim 1 or 2, characterized in that inputs of an energy backward detector (72) are connected to the outputs of the signal evaluation arrangement (53) for determining whether pulses at the outputs of the signal evaluation arrangement (53) over a predetermined time. appeared that belong exclusively to a negative energy flow direction. 4. Multi-function counter according to one of claims 1 to 3, characterized in that the output pulses belonging to different directions of energy flow of all signal evaluation arrangements (53) are fed to one of two time multiplexers (54; 56 or 54; 57) for the purpose of energy summation, in which they are switched in series. 5. Multifunction counter according to Claim 4, characterized in that one output of each of the two time multiplexers (54; 56 and 54; 57) is connected to a separate input of a microcomputer (26). 6. Multi-function counter according to claim 5, characterized in that an error detection arrangement (25) is present, in the register (115) of which for all phases the presence or absence of overvoltages and undervoltages and of phase failure signals (PF1, PF2, PF3 ), a count of the latter and a collective result (RRST) of an energy backward detection are temporarily stored, that a shift register (120) is available for taking over the information temporarily stored in the register (115) for subsequent time-serial transmission via a bus connection (SPI1) to the microcomputer ( 26). 7. Multifunction counter according to Claim 5 or 6, characterized in that at least one input arrangement (30) serving for control purposes is arranged as an interface circuit between a bus input (30a) of the multifunction counter and the microcomputer (26), the input arrangement (30) among others serves to switch tariffs. 8. Multi-function counter according to one of claims 1 to 7, characterized in that a calendar clock (27) is present which serves, among other things, a tariff changeover. 9. Multi-function meter according to one of claims 1 to 8, characterized in that a ripple control receiver (RCR) is present, the ripple control signal input is automatically connected to one of the three phases of an energy supply network which has no undervoltage. 10th  Multifunction counter according to claim 9, characterized in that the ripple control receiver (RCR) is used, among other things, to switch tariffs.       1. Multi-function meter with an electricity meter (20; 21; 22), which for each phase has a measuring unit (21) belonging to the respective phase, the output pulses of which have a frequency (fR, fS, fT), each of which is proportional to the one in question Phase measured by the associated measuring unit (21) power value (uR.iR, uS.iS, UT.iT), characterized in that for each phase, both information regarding a determined energy flow direction and information regarding the presence of a phase failure in the Duration of the output pulses of the associated measuring unit (21) is included, a phase failure occurring if the associated measuring unit (21) cannot detect a zero crossing of the associated phase voltage (uR, uS, UT) for the phase in question,  and that in each phase of the associated measuring unit (21) there is a signal evaluation arrangement (53) associated with the relevant phase, at the input of which a pulse duration decoder (69) is arranged on the one hand for the purpose of separating the pulses belonging to different energy flow directions and on the other hand for the purpose of blocking the latter pulses and generating a phase failure indicator if there is a phase failure. 2nd Multifunction counter according to Claim 1, characterized in that outputs of the pulse duration decoder (69) are connected to the output of the signal evaluation arrangement (53) via a release arrangement (74; 75), the release arrangement (74; 75) being connected to an output of an idle suppression Arrangement (71) is controlled, which determines whether no pulses have appeared at outputs of the pulse duration decoder (69) during a predetermined programmed time value, and that output signals of the latter no longer reach an associated output of the signal evaluation arrangement (53), until the time interval between two successive pulses is again less than the predefined programmed time value. 3rd Multifunction counter according to Claim 1 or 2, characterized in that inputs of an energy backward detector (72) are connected to the outputs of the signal evaluation arrangement (53) for determining whether pulses at the outputs of the signal evaluation arrangement (53) over a predetermined time. appeared that belong exclusively to a negative energy flow direction. 4. Multi-function counter according to one of claims 1 to 3, characterized in that the output pulses belonging to different directions of energy flow of all signal evaluation arrangements (53) are fed to one of two time multiplexers (54; 56 or 54; 57) for the purpose of energy summation, in which they are switched in series. 5. Multifunction counter according to Claim 4, characterized in that one output of each of the two time multiplexers (54; 56 and 54; 57) is connected to a separate input of a microcomputer (26). 6. Multi-function counter according to claim 5, characterized in that an error detection arrangement (25) is present, in the register (115) of which for all phases the presence or absence of overvoltages and undervoltages and of phase failure signals (PF1, PF2, PF3 ), a count of the latter and a collective result (RRST) of an energy backward detection are temporarily stored, that a shift register (120) is available for taking over the information temporarily stored in the register (115) for subsequent time-serial transmission via a bus connection (SPI1) to the microcomputer ( 26). 7. Multifunction counter according to Claim 5 or 6, characterized in that at least one input arrangement (30) serving for control purposes is arranged as an interface circuit between a bus input (30a) of the multifunction counter and the microcomputer (26), the input arrangement (30) among others serves to switch tariffs. 8. Multi-function counter according to one of claims 1 to 7, characterized in that a calendar clock (27) is present which serves, among other things, a tariff changeover. 9. Multi-function meter according to one of claims 1 to 8, characterized in that a ripple control receiver (RCR) is present, the ripple control signal input is automatically connected to one of the three phases of an energy supply network which has no undervoltage. 10th  Multifunction counter according to claim 9, characterized in that the ripple control receiver (RCR) is used, among other things, to switch tariffs.