CH629320A5 - DATA PROCESSING FACILITY. - Google Patents

Description

The object of the invention is to improve the situation which arose in the prior art.

According to the invention, this object is achieved by the presence of the characters set out in claim 1.

The dependent claims define particularly advantageous embodiments, in particular as regards the constitution of the channel unit and of its channel memory, forming part of the installation according to the invention.

The details and particularities of the invention will emerge from the description below, given by way of example and with reference to the appended drawings, in which:

Figure 1 is a block diagram of the general data processing installation according to the invention.

Figure 2 is a schematic representation of the channel unit.

Figure 3 is a more detailed schematic representation of the channel unit.

FIG. 4 is a schematic representation of the data manipulator which constitutes a part of the channel unit of FIG. 3.

Figure 5 is a more detailed schematic representation of the channel control logic which is part of the channel unit of Figure 3.

Figure 6 is a schematic representation of the data access control logic which is part of the channel control logic of Figure 5.

Figure 7 is a representation of the area in the offset channel state memory.

Figure 8 is a representation of the shift channel state area for an input operation.

FIG. 9 is a representation of the shift channel state areas for an output operation.

In FIG. 1, the data processing installation according to the invention is represented as comprising a main memory 2, a storage control unit 4, an instruction unit 8, an execution unit 10, a unit channel 6 with associated input / output means and a console unit 12. The system of FIG. 1 works under the command of system instructions, an organized group of which forms a system program. The system instructions and the data on which the instructions work are introduced from the input / output equipment, via the channel unit 6 and the storage control unit 4, into the main memory 2. From the latter, the system instructions and the data are sought by the instruction unit 8, by means of the storage control unit 4, and are processed by so as to control the execution in the execution unit 10. One can refer to this subject to a publication "IBM System / 370 Principles of Operation", SRL GA22-7000-3 published by IBM Corporation, which teaches the general details of a data processing system compatible with the present invention.

In FIG. 2, the channel unit 6 of FIG. 1 is represented in a schematic form as connecting the input / output control devices 411 ′ to the unit S 4. The number N of 35 channels is variable but, at the For the purposes of this description, N is 16, which indicates 16 channels. The CCL 403 'channel control logic operates to control the channel apparatus and the allocation of its different parts to particular channels. The channel control logic 403 'includes 40 a memory addressing and priority allocation unit 444 for determining which part of the channel control logic 403' will be allocated to a given channel. The logic 403 'further comprises four control segments (parts) which are attached to the memory addressing unit 444. 45 Although Figure 2 shows a division into four segments, other divisions are possible. Each of the control logic segments can be dedicated to particular functions, in which case each segment operates independently of the others. In Figure 2, a status command 428 'receives an instruction for a particular addressed channel from unit I on input wiring 426. The status command 428' then properly addresses and modifies the location among the sixteen channel state memory locations contained in channel memories 448 which corresponds to the channel addressed. Later on, other logic control segments execute operations required to carry out the instruction from unit I. These operations typically include access to unit S by the logic of unit access S 430 ', command word processing by operation command 429' 60 or data transfer to a control unit 411 '. Typically, each logical segment 428 ', 429', 430 'or 432' will itself modify the channel state memory in the channel memories 448 as it executes its operations. Operations typically require access to 65 other channel memories contained in memory 448.

The input from unit 18 of FIG. 1 via line 426 is derived from the effective address register (not shown) of this unit I when, at appropriate times

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required, a channel number (four lower order bits of an eight bit byte) is produced to designate, in a sixteen channel system, that of the sixteen channels which is then processed. The channel specified on line 426 is processed by different parts of the channel unit at different times. For a given transfer, the state control logic 428 ′ receives the order and the channel number from the unit I and modifies the channel state memory location associated with this channel, so that other logical control segments perform coordinated actions.

In the example with sixteen channels, the channel state memory comprising i0 takes sixteen locations and the particular location associated with the specified channel on line 426 is addressed by circuits 444.

The operations that can be executed by the channel unit 6 of FIG. 1 include information transfers between the unit S 4 and the channel memory 448 and information transfers between the channel memory 448 and the input / output devices, via the input / output control units 411 '. Transfers between the unit S and the channel memory 448 are located under the control of the access memory of unit S and of the commands 430 '. Likewise, transfers between the channel memory 448 and the input / output control devices 411 'are under the control of the access memory CTLR and the commands 432'.

In Figure 3, the channel unit 6 shown in Figures 1 and 2 is illustrated in more detail, with the channel memory 448 of Figure 2 divided into three physical parts and the control logic in four physical parts. The parts of the channel memory are the shift channel state memory (SCS) which comprises stages SCSO to SCS15, including a delay 431, the local channel memory (LCS) 406 which comprises a buffer memory of channel (CBS) and a subchannel state memory (SSS) and also the subchannel buffer memory (SBS) 408. The parts of the control logic include the state commands 428, the OCL commands 429 , 35 DACL 430 commands and CIC432 commands. Furthermore, in FIG. 3, the channel unit 6 comprises register circuits 404, a data manipulator 405 and a remote interface logic 407. The latter (RIL) communicates with a multiplicity of input control devices. / output 411. The unit C 40 6 operates so as to interconnect input / output devices associated with the input / output control devices 411 with the rest of the data processing system of FIG. 8.

The channel control logic (CCL) 403 comprises, a shift register memory (SCO to SCS15) which is addressable for each channel of the unit C 6. In FIG. 3, this memory includes state locations 428 for controlling and specifying the status of an addressed channel, operation and control logic (OCL) slots 429 for specifying and controlling the operations of the channels, access control logic locations data (DACL) 430 for controlling access of data information from and to unit S in Figure 1, and central interface control logic (CICL) locations 432 for the access of information to and from the input / output control devices 411, via the remote interface logic (RIL) 407. In the present embodiment of the invention, the stages 428, 429, 430 and 431 are produced by stages of shift register which circulate their content. In another embodiment, the storage 60 in the stages 428 to 431 is carried out with a direct access memory. In each embodiment, there is a storage location associated with each channel and a method for accessing that location in memory.

In addition, the channel control logic (CCL) 403 includes 65 a command 433 which communicates with the desk unit 12 of Figure 1 to carry out orders specified by the desk.

An order lock register 450 receives, on the input wiring, thirteen bits of control data which are locked in the order lock register 450 under an order on the lock command line 545 designated by valid C . The bits in the order register 450 are output on the wiring 455 where the output bits 12 and 11 are applied to the sub-channel buffer memory 408 in order to control this memory 408 in response to commands from the console.

Bit 10 from register 450 is applied to local channel memory (LCS) 406 in order to control local channel memory under the command from console 12.

Bits 9, 8 and 7 from register 450 are applied to registers 404 to control the registers with input information on wiring 543.

Commands 433 include a channel clock network 454 which is blocked or started under the control of bits 6,5 and 4 of register 450. Commands 433 also include an initial program load mode (IPL) circuit 453 which controls the channel unit during the IPL operating mode in response to bit 3 from register 450. Bit 2 of register 450 is communicated therefrom as input to stage SCS15 of the stages of state 428. Bit 1 of register 450 is applied to register access commands 452 which control the loading of register circuits 404 via input wiring 543. Bit 0 of register 450 is applied to commands of resetting to the initial state 451 which operate so as to reset the circuits of the unit C 6, in response to bit 0 of the order register 450.

The registers (REG) 404 of the unit C include a 32-bit storage unit address register (SUAR) 464, a 32-bit storage unit data register (SUDR) 465, a register of 32-bit work (WR) 466, a 13-bit local channel memory address register (LCSAR) 467 and a 32-bit local channel memory search data register (LCSFDR) 468. The WR register 466 receives information from unit S via input wiring 394 and its output is connected by wiring 424 as an input to the channel data manipulator (CHDM) 405. The register WR 466 also has an input derived from the LCS register FDR468 and the subchannel buffer memory (SBS) 408, via cabling 423. The data path widths have been given in general for the simplicity of the description, ignoring the parity bits that are present in a conventional way. For example, for 32 bits, 4 parity bits are present at the rate of 1 per 8-bit byte.

The SUAR register 464 also receives an input from the LCS FDR register 468 and provides its output to an address decrease (DECR) 435 which has an input on the wiring 353 which is connected as an input to the buffer address register ( not shown) in the unit S. The SUAR register 464, in cooperation with the decreasing device 435, acts so as to specify the address in the memory unit where the information is stored or sought by the unit C 6. The SUDR register 465 acts to store data in the storage unit via a byte shifter 436 and an output wiring 358. The data sought on the wiring 394 in the working register 466 or stored through wiring 358 are located at the location in the storage unit specified by the address on address wiring 353.

The information sought in the storage unit is stored in the WR register 466 and transmitted by wiring 424 to the channel data manipulator 405. The data originating from the channel data manipulator is received again by wiring 425 and stored in the data manipulator output register (DMOR) 437. The latter is connected by its output as an input to a data manipulation register (DHR) 439 whose output, in turn, is connected as that entered the local channel memory

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(LCS) 406 and to the subchannel buffer memory (SBS) 408. Partly of the local channel memory 406, by causing furthermore, the DHR register 439 receives an entry from the access register to the SSS on the basis of the successively increased content of the interface logic data (ILGDR) 438. The latter is device address register 479. The state logic 482 exa-

connected so as to receive via its cabling mine information on cabling 424 in search of the sub-

input 415, data from the highest priority 5-channel remote interface logic. The subchannel state logic

(RIL) 407. 482 communicates an input to the OCL on the wiring

Remote Interface logic 407 shown in Figure 497 and receives an output from the OCL on wiring 499. In addition, the

3 is connected to the logic input / output control devices for sub-channel status 482 responds to information on the

(control units) 411 and therefore the wire transfer 482 and, in the device address register 479,

data in the data processing system from i0 blit a priority which is offered as entry to the doors of entry / exit devices is done via the entry selection register 487 for storage in the locations- ILGDR 438. When data is received in the sub-channel status registers of the local channel memory 406.

404 via remote interface logic 407, Wiring 424 is also connected as an input to pass through data register 438 to device address register memory 479 when it is used

local channel 406 or the sub-channel buffer memory 408 before 15 to specify which device is to be processed under the command to be still transmitted to the data processing system of the unit C of FIG. 3. The register d device address 479

born. When information is to be transmitted from is also loaded directly from the registers address register 404 to input / output devices, this effective (EAR, not shown) is accessed on the wiring 426. The address information from the local channel memory via device on this wiring 426 applied to register 479 is diary of wiring 421 and it is locked in the 8 bit register. These 8 bits together with 4 bits of higher rank,

local channel memory search data 468, of which the one for specifying the channel number, is applied as output is connected as input to register ILPDR 440. Has input on wiring 426 to control multiplexer 704

from the latter, the data to be transmitted to a device in the state logic 428 of FIG. 6.

input / output are selected 1 or 2 bytes at a time The device address register 479 is updated by starting from register 440, by a byte selector 441. The increase of 8 by means of the increase device 8,480

output wiring 416 of selector 441 includes 16 bits of which receives output from register 479 and forms a new

data, two 8-bit cables (plus parity), which are connected for this one. A comparator 481 receives an input du as input to the remote interface logic 407. For register 479 and input wiring 424 to detect that summarize, the registers 404 act so as to store the registers d device address 470 specifies the same data device sought from unit S via 30 which is identified on wiring 424. The results of the comparison

wiring 394 or for storing data in this unit S sound in comparator 481 is stored in a register via wiring 458 at a location of a- 486 whose output is connected to the OCL as part of the stands in the unit S specified by the address on wiring 353. wiring 498.

The information transferred between the registers 404 and the imitated S is The wiring 424 also serves as an input for the manipulator also stored in the local channel memory 406 or the data 483. The manipulator or adder 483 receives buffer memory 408, via cabling also inputs of the data access control logic 419, to an address specified by wiring 420 and it is (DACL) on wiring 495 for use in combination returned to the registers 404 from these memories, by with data transfers between the unit S and the memories through the intermediary of the cabling 421 and 423. For channel transfers. The adder 483 is connected by its output to the data gates between the registers 404 and the input / output devices, input selection 40, by means of a wiring 492, so that the information is output via of the logic of inter- conditionally transmitting main memory addresses

face remote on the wiring 416 and is entered into the blades and data counts in the channel memory registers 404 from the remote interface logic. local 406 and the sub-channel buffer 408 of the mete

FIG. 4 shows the channel memory manipulator in greater detail, when they are available for access to channel data 405 of the unit C of FIG. 3. This manipulation in combination with transfers of information. The adder adder 405 receives the 32-bit input on the wiring 424 which is 483 also receives an input from a support generator 491

connected to numerous locations in the manipulator which under control, via input wiring

405. More specifically, the input cabling 424 is connected at 497, from the OCL, operates so as to correct the address in the as input to the status registers 476, to the bits of channel memory flags at l '' completion of procedures in conjunction with

477 and order register 446. 50 one channel.

The status register 476 operates so as to maintain In FIG. 4, the data manipulator adder the state information concerning the operation of the registers 483 receives an input from the counting selection circuits of channels in the unit C 6 in FIG. 3. The registers 476 have buffer byte 474. The circuits 474 receive a count an input to the selected input gates 487 and make a byte in 5-bit buffer (BBC) which consists of the 5 part of the input to OCL 429, as part of the 55-bit lower order cabling of the total 16-bit counting area. The

498. Flags 477 function as counting zone devices defines the total number of bytes of storage donation intended to indicate that certain functions are born to be transferred between the channel unit and the storage unit.

occurred and, similarly, they have an entry to OCL through the intervention. In most cases, byte counting in tam-

wiring medium 498. The order register 446 works pon (BBC) is received from the action register DACL 736 so as to lock the order words and make them available on line 460. Under certain conditions , when errors or via a door 487. Likewise, the content of other interruptions have occurred, the count of byte register 446 is recoded in a more useful format, in a log-in buffer is received from the OCL on line 461. The circuits for recoding 478 and it is then applied as input to 474 can also select the information from the wiring

OCL, via wiring 498. 424, which is derived from working register 466 in Figure 3.

In addition, the input wiring 424 is connected to the logic "During the start-up sequence and whenever a rete-

482 subchannel status which acts to control and bare is required from the higher ranking bits of the area to analyze the information associated with the counting sub-channel information, the working register of the Figure 3 is loaded with the stored in the sub-channel state memory (SSS) which is the counting area. During start-up and above all trans-

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multiplet fert, the counting area is applied as a data manipulator output register 437 in the unit

input to the right connection of adder 483. A of register 404 in FIG. 4. The content of the 32 bits is selected

other times during processing and while the area of tié and formulated under the command of the selection commands

higher rank of the byte count must be updated, tion 488. The selection commands 488 select the higher rank bits are obtained from the 5 information register from the input wiring 424, from the working logic 466 and the lower rank bits (subchannel state byte count 482, status registers 476, buffer register) are obtained on line 460 and are applied to device address 479, the manipulator adder joined to the right connection of the adder 483. The data 492, the order register 446 and the input wiring received transfer length is usually 4, being given 475.

born that this is the maximum number of bytes that can be 10 Input wiring 475 to the input selection doors sent to the storage unit each time. This quantity 487 receives 8 bits respectively constituted by the information of must also be subtracted from the counting area (and by channel number, the flag register information triggered consequently by BBC) at each transfer from storage unit, and channel state information. In addition, cabling 475 receives 4

The left connection of the adder 483 receives the Ion data bits concerning the new effective byte transfer byte status information (TL) which is 4 in 15 subchannels on the 497 wiring from OCL . Likewise, the usual conditions, which means a transfer of 4 multi-cabling 475 receives input information from the cabling 495

plets. The effective byte transfer length is sub-derived from the state computer 703 of FIG. 6, by means of

deals with the remaining part of the counting area in the 495 wiring addendum.

actuator 483, under the control of the functional control The channel control logic (CCL) 403 in the device

of the data manipulator (DM FCN CTL) 490. 20 reil of Figure 3 is shown in more detail in Figure 6. At the

The output 492 of the adder 483 includes the new figure 5, the status logic 428, the operating control logic

remaining count. During a start-up operation, nothing (OCL) 429, the data access control logic is subtracted from the initial count area and therefore (DACL) 430 and the central interface control logic the total count area appears on the wiring 492. A (CICL) 432 form the main parts of the short sequence logic occurs during processing to set 25 channel control which cooperate with the day count memory of the count buffer byte (5 bits of inferior channel rank. Each of these parts can be assigned to a laughing channel), when one is retained from the bits of higher rank times and each can be assigned to different channels relative

is not required. In this short sequence, port counting to others.

Updated buffer byte appears on wiring 492 and the channel state memory is made up of higher-order bit stages are ignored. A long sequence over shift register 710, one for each channel. The comes when there is a need to carry out from the shift register stages 710 include a memory of higher rank bits, which are first obtained from the offset channel state memory (SCS) which determines the status of each channel for working register 466. The bits of higher-order rank and indicate which channel is available for allocation to riors of the working register, together with the counting of parts of the control logic of cemal (CCL). The 16 buffer bytes (lower rank bits) coming from the 35-stage circuits 710 identified as SCS0, SCSI, ..., SCS15 containing selection 474, are applied to the adder 483. The ion each at a time given over time, an effective transfer informator is subtracted so as to produce tion associated with a particular corresponding channel among the new counting wedges remaining on the output wiring 492. channels identified as channels CH0, CHI, .. CH15. Pen-

The output of the adder 483 sends the counting of an initial cycle at a point in time, SCS0 contains full buffer (5 bits of lower rank) on the wiring 427 to 40 an information concerning CH0, SCSI contains a informa-

result register DACL 737. Similarly, the 11 bits of rank tion associated with CH15, and so on, until SCS15

higher are applied to the extended bit calculator (EX contains information associated with CHI. During the cycle

CAL) 471. The computer 471 includes an OR gate with the following clock 11, SCS0 contains information associated with

inputs (not shown) which detects the existence of a logic 1 CHI, SCSI contains information associated with CH0. Each time in a bit of any higher rank in the next clock cycle area, the channel information is advanced stepwise. The output of the OR gate is selected each time that one of the stages 710 in the manner of a shift register classi-new selection signal EX appears on line 456 and on that. After 16 cycles, the information is again located as line 418. In the absence of a signal on line 456, the old one in the initial cycle.

value of EX on line 457 is retained and output on line As mentioned, the offset channel state (SCS) is a

418. The value of EX on line 418 is defined as the 50th set of 16 shift registers, that is, stages from 0 to 15.

new value and it is sent directly to the register of each channel status information occupies a position and is DACL 737 result and also locked in the shift register by one stage at each machine cycle, in a byte counting manner in buffer (BBCR) 470, jointly annular. A given channel in stage 0 reappears

with the new value of the buffer byte count tra in this location 16 machine cycles later.

from wiring 492 at the time the OCL provides a 55 Channel status information defines states of the latch signal process on line 462. input / output and command and error information for

The addition or particular function performed by the addition - each channel. The operations control logic, the neur logic 483 is specified by the data access control function control device and the data manipulator control logic 490 including the interface device communication com functions. order have access to this information

mands are specified by the operation control logic 60 tion at specified points along the SCS path. this allows

OCL on input wiring 496, from point decoding processing of 16 channels on a time sharing basis,

OCL 706. The six inputs on the 496 cabling to the Global Transfer State (GTS) is a 6-bit area which from the OCL are correct counting, support counting, defines the state of interface control logic of device correct data, support data, increase of 4 command (CICL) for a channel. The 6 bits are interpreted and the increase of 8. The entry on line 417 from 65 following an octal code and the GTS states are numbered from 00 to

DACL specifies whether to add or subtract. 77.

The DMOR 487 input selection gates produce the OCL local state (OLS) is a 6-bit area which is deco-

the outputs on 32-bit wiring 425 which serves as input for the dee according to an octal code and represents the state of the logic of

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operation command (OCL) in progress for a channel. The main states defined are as follows:

State

OCL inactive Initial selection SIOF

Chain

Maintenance

Transfer

Wait, data flow Possible hold

OLS bits 012345

101E00

100ETT

1100TT

111000

111010

111100

OCPPPP

1101TT

Note:

The set bit “E” indicates that a channel or interface command check has been detected before returning to a condition code and releasing the unit I during the execution of an input / output instruction .

The TT zone in initial selection and SIOF are initialized from the interface clock and used to detect an interface time lapse.

The TT possible hold zone is reset to the initial state from the possible hold clock.

The CPPPP area awaiting data linking is a copy of the CICL last byte indicator kept during the preliminary search.

The OLS area defines the internal state of the operation control logic (OCL). The fundamental difference between the global transfer state (GTS) and OLS is that the latter is a state in OCL only, while GTS concerns both OCL and the control device interface control logic (CICL) and can be browsed by one or the other. The purpose of OLS is to assign a separate state to each OCL order step for a particular TS. For example, when GTS is the "initial state" state, OLS makes a difference depending on whether the state is initiated by an input / output start (SIO) or an order chain.

The 2-bit transfer operation area (TOP) contains the type of data transfer operation specified by the channel command word (CCW).

00: input / output test 01: output or command 10: input

11: back entry.

The 3-bit interrupt status (IS) area contains the interrupt status of the channel. It does not change when subchannels are exchanged. The interrupt states of all the subchannels assigned to a particular channel are stored in the subchannel state memory (SSS). Zone I translates the highest priority interrupt state of these subchannels. The 8 states represented by this area are listed below from highest to lowest priority:

010: Fatal order verification. An order check was detected in the channel. 111: Equipment check. The channel contains an interruption in progress due to an equipment malfunction.

110: Primary interrupt. An "end of channel" interrupt is in progress in the channel or sub-channel. 100: Secondary interruption. There is an asynchronous interrupt which does not include "end of channel". A secondary state is not memorized in the channel, but is maintained as in progress in the input / output device.

011: Channel available. There is an "available channel" interruption in progress. This applies to block multiplexer channels only.

001: None. There is no current interruption in the channel or subchannels.

000: SSS not sampled. This code indicates that an interrupt state is not known, because the subchannel state memory (SSS) has not been sampled. This will occur after an interrupt has been processed and will remain until the operation control logic (OCL) can begin sampling.

The 10-bit Unusual Termination Area (UTF) code represents a condition that terminates data transfer for any unusual conditions. If there must be more than one unusual condition, the condition for which a higher value is assigned is set.

15,000: OK (no termination of data transfer) 001: Stop. This is asked when receiving an input / output stop instruction.

010: Eminent protection check. 011: Eminent program verification.

20

Note:

The two preceding conditions are set when either the protection check or the program check is detected for an order or data previously searched in a data chain processing for an output operation. These conditions are transformed into actual verifications when the entry / exit operation condition passes to the new order or when the protection delimitation is crossed.

30

100: Protection check.

101: Program verification.

110: Interface command check. Error detected on the input / output interface.

35 111: Channel command check. Error detected for an internal command operation at imity C.

The channel type (CH. TYPE), a 2-bit code, represents the channel type. Figures 1 and 6 show how the channel type is determined using information from the channel address memory (CAS). The two channel type bits have the following meaning:

00: Multiplexer of multiplet 01: Block multiplexer 45 10: Selector channel 11: Not installed.

The 1-bit OCL distinction code (OCLDIST.) Is set if the OCL goes through the OCL chain order circulation before entering the start-up input / output raso pide circulation (SIOF). This gives the OCL a process for distinguishing whether SIOF was started from a fast input / output start instruction or via chain order circulation.

The distinction bit OCL is also used during 55 of a flow data operation. In this case, the bit is set when the CICL indicator exceeds the CPPPP (last CCW byte indicator in progress).

In either of the cases described above, the distinction bit is set in the SCSI stage by the OCL. 60 The 5-bit Data Access Control Logic (DACLP) flag indicates the next byte of data that the DACL will have access to in the channel buffer.

The Buffer Byte Count (BBC) bits, 0-4, are the 5 lowest rank bits of the Byte Count originating from the Channel Command Word (CCW). During CCW search, the operation control logic (OCL) copies the 5 lower rank bits from the CCW count area into the shift channel state.

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The available 3-bit DACL buffer (ADB) is the flow data output. If there is a number of bytes of data or data locations in a CCW prior to the sequence of data born available for processing by DÀCL. with its PCI flag set, the current PŒ flag is set.

When input / output transfer is initiated for this CCW

ADB is a measure of buffer constraint. 5 (i.e. the previous CCW is completed), this bit is transmitted

CICL contributes to the constraint (ADB). fée to the PCI flag.

DACL decreases the constraint (ADB). We will now examine the 3-bit checks.

ADB at 0 is a maximum output constraint and an Interruption of the minimum input program control device (empty data buffer (PCI). This bit is set if the channel command word contains the in both case). 10 PCI flag. A PCI interrupt is presented to unit I when-

ADB represents two things: that this bit is set.

1 °) as input, ADB represents the filling of the Note buffer:

LCS data and is the number of bytes of data in the although this bit is located in the verification area of SCS,

buffer. it is logically part of the flag area in SCS.

2) at output, ADB represents the vacuum of the data buffer 15 Chain verification (CCK) indicates that a verification

and is the number of byte locations that are empty web cation occurred. Detection is performed by in the buffer. the priority logic of DACL. When an audit of

ADB is a measure of the linkage buffer constraint has been detected, the CCK bit is set in SCS 3 by born, the larger ADB and the greater the constraint. The priority logic of DACL.

control device interface control logic 20 Channel Data Check (CDC) indicates that DACL

(CICL) increases the constraint, while the logic of where CICL has detected a channel data check.

data access request (DACL) reduces this constraint. We will now examine CICL (CCL), 2 bits.

During an entry operation, an available DACL buffer. The CICL indicator (CICL IND.) Is written in SCS 0 or 8 to

(ADB) of 0 means that there is no byte on two occasions:

channel data buffer and that the buffer is at its 25 1 °) During the initial selection if the address from the minimum constraint. While bytes are received from the input / output devices (at the input address time) corresponding

of the input / output device, CICL places them in the pond buffer at the address sent to the input / output device (at the given time and increases the ADB, that is to say the output address buffer).

data is subject to a higher constraint. Given that 2 °) During the initial selection if the initial state (at time the DACL removes these bytes from the data buffer and the 30 entered state) was equal to 0.

sends to unit S, it also reduces the ADB, i.e. the CICL parity error (CICL P.E.) is written in SCS 1

the data buffer is subjected to a lower constraint. or 9 if CICL:

During an output operation, the DACL buffer available 1 °) detects a parity error in the interface data

(ADB) at 0 is also an empty buffer. However, the buffer reaching the local channel memory (LCS), which is data is at a maximum constraint, because the CICL 35 detected in the data maintenance register (DHR), or does not have data to transfer to the input device / 2 °) if a parity error is detected for output data. While DACL places data in the buffer, it retrieved from LCS, what is detected in the registry decreases the ADB and the data buffer is subjected to more data collected in the local low-stress channel memory. When the interface control logic (LCSFDR).

from the control device (CICL) withdraws its data, it increases 40 We will now examine the interface transfer width also lies the ADB, which imposes a greater constraint (ITW), of 3 bits.

to the data buffer. A 4 byte interface (FBI) is used to indicate

As an example, imagine a data buffer when this channel works as half of a pair of channels in an output operation. The DACL decreases ADB and the CICL used for an interface operation of 4 bytes,

increases it. If 4 bytes are placed in the buffer by 45 The bits 0—1 have two functions:

DACL, ADB is reduced from 0 (32 empty positions) up to 28 1 °) Bit 0 is used to signal a new order test

(29 empty positions). Some data is then available to OCL during state entry, if the state is not zero. This is for the CICL and the buffer is subject to a lower count by transferring the mark input bit 0 from the drag interface. Whereas CICL sends a byte of the input / output device to bit 0 of ITW.

input / output, ADB is increased to 29 (29 locations 50 2 °) At times other than the status time, bits 0-1 indicate

empty buffers) and the buffer is subjected to a larger conquer the logical width of the input / output interface, as follows: drag.

We will now examine the 4-bit flags. 00 - width 1 multiplet

Chain data (CD) comes from the zone of dra- 01 - width 3 bytes skin of channel command word (CCW). It is kept in the 55 10-width 2 bytes

SCS by the reset instruction SCS (observed in 11 - width 4 bytes.

OCL traffic diagrams). We will examine below the distance to the page (DTP), from

Chain order (CC) comes from the 4-bit flag area.

CCW and is kept in the SCS by the setting instruction. The page bit indicates, when set, that the channel is

the initial SCS state (observed in the 60 cute traffic diagrams, either indirect channel addressing or a logical operation

OCL). than. Bits 0-2 have the following meaning:

Illegal length detected (ILD) is set in SCS 4 or C

when the device interface control logic of 000 - page delimitation to more than 4 bytes command detected an incorrect record length. 001 - 1-byte page delimitation

Skip / interrupt program control device 65 010-2-byte page delimitation

(SKIP / PCI) is used to indicate a jump during an operation - 011 - page delimitation with 3 bytes input (data transfer deleted) or an interrupt - 100 - page delimitation with 4 bytes device control command for an operation 101- page delimitation reached

9

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110 - not used at the entrance. While the CICL is filling the LCS 406 buffer, the

111-not used. DACL the void.

The memory protection key (KEY), 4 bits, To complete an entry, the CICL will complete the transfer of contains the memory protection key from the word data before the DACL does so. When there is less channel address (CAW). This area is initialized by 5 of 32 bytes of data to be transferred again, the EX bit is the OCL. We refer to the initialization of SCS in the canceled. When this is the case, BBC is counting byte OCL traffic diagrams. remaining. The CICL will stop entering data when

The 4-bit channel number identifies the channel to which BBC = ADB and EX is canceled. At this time, the buffer holds the SCS state information, in the displayed stage, (see the data (LCS 406) contains all the necessary bytes although production of the channel number). 10 that the DACL has not completed transferring all bytes to

The buffer command for unit S will now be described in more detail. The DACL will stop sending data to the data unit S. The channel buffers include the when the BBS is decreased to 0 and EX is canceled. Single subchannel buffer memory (SBS) and channel memory the DACL decreases BBS; so, when BBC is zero, all local (LCS). The SBS retains the order information and bytes have been brought to unit S.

status for inactive subchannels. The LCS is divided into three 15 For an output operation, the description which follows logically distinct zones, the channel buffer memory 1 identifies the indicators with reference to FIG. 9. The indicators (CBS I), the memory subchannel status (SSS) and the DACL and CICL memory both start at zero. The DACL channel 2 buffer (CBS II). CBS I and II contain zones collects 4 bytes of data from unit S, the command, status and data buffers for the 16 channels, in CBS following the DACL indicator and advances the indica-The SSS stores the functional states of the 1,024 sub-channels. In Figure 9, the DACL acted six times, so that available. the indicator is in the byte 24. The CICL sends data

There are 16 data buffers with the buffer born at the input / output device and advances the channel indicator (CBS) comprising memories 407 and 408 of FIG. 5, CICL. The CICL is only starting and is at the byte one for each channel. Interface channel logic available. Each transfer is a byte, so that control bit 432 and the access control logic of the next location will be byte 1. The data flag 430 controls these buffers. The DACL 430 com- DACL precedes the CICL indicator in a clockwise direction to direct the movement of data between the unit S 4 and the watch zone around the queue. While the DACL data from CBS. The CICL 432 controls the movement of fills the LCS buffer, the CICL empties it.

data between the CBS and the entry / exit devices, via the Inter- To complete an exit, the DACL will complete the transfer of the mediaries of the 411 control devices. During an entry, the 30 data before the CICL does it . When there is less CICL 432 filling the data buffers, while the 32 byte DACL 32 to be repeated for the DACL, the bit EX 430 is empty. On exit, the opposite is true, the DACL canceled. In this case, BBC is the remaining byte count, filling and the CICL emptying. The DACL will stop collecting data when the BBC is

Each buffer contains 32 locations of a multiplet; decreased to zero (and the EX bit is cleared). The CICL however, addresses are carried out on the delimitations of a word. 35 will stop moving data to the I / O device Buffers can be considered queues when ADB = BBC = 0.

circular. An address wrapper is used so that the channel number generator is a binary counter at which buffer operations are continuous. This comes down to 4 bits which is realized as part of channel number to say that when DACL or CICL addresses the last word (28), they stage F of SCS. The 4-bit channel address is propagated to continue with the zero address. 40 stages 0,1 and 2 of SCS. Since these are the only

Two indicators are used to track floors where SCS data is reviewed or modified, the par-

access to the buffer: the DACL indicator and the CICL indicator and tie of SCS channel address falls after stage 2. The computer-each of them indicates one of the 32 locations of a multiplet . tor produces the channel numbers displayed in the other floors

The DACL flag is a 5-bit flag stored in SCS.

SCS. There are 16 DACL indicators, one for each channel. 45 When powered up, this 4-bit binary counter The flag is also used by DACL to produce a start in a random state, then advances by one unit at CBS address when accessing the data buffer. each clock cycle, counting from 0 to F, and it repeats conti-

The CICL indicator is not kept in SCS. It is widely.

duit in the CICL by adding the buffer zone DACL available. The lower rank bit of the number generator switches to

4-bit target from SCS to DACL flag. All 50 each cycle. This lower rank bit serves a dual purpose, as like the DACL, the CICL uses its flag to produce this sense that it is also referred to as the "im-cycle lock of CBS addresses which are loaded into the address register of peer". When the lock is cut, the cycle is considered as local memory 467 when access to the CBS is required. being "even", while when armed, the cycle is considered

like "odd". This lock has an entry towards the multi-For an entry operation, the description which follows concerns 55 SU / LCS plexer in order to determine even / odd cycles by the indicators mentioned in figure 8. The two indicators compared to the priority CICL or OCL / DACL. The clock input starts at zero. The CICL collects data, a multi (not shown) to each of the stages 710 is conventional.

complete at the same time, stores them in CBS with the CICL indicator and The first part of the channel control logic advances the indicator, by a count of bytes. In the figure (CCL) 403 is constituted by the state circuits 428 which responds-8, the CICL has loaded the bytes 0 to 23 and indicates replace-eo tooth on stages SCS15 and SCS0 of the channel state memory, Next, that of byte 24. The DACL has access to the data. The stage SCS15 receives an entry from the stage SCS14, an entry born in CBS using the flag DACL, sends the data from the register of order lock 450 of FIG. 3 on line 712 born at unit S and updates the DACL indicator. In FIG. 8, and an entry on line 542 derived from the desk unit 12 of the DACL indicator is found at the byte 0. During the first, FIG. 1.

transfer, the DACL will transfer 4 bytes, 0 to 3, so 6s The information in SCS15, during any clock period that the DACL indicator will be found at mutliplet 4 after a given, offers an input to the state calculator 703 where the calculation transfers. The CICL flag precedes the DACL flag in the configuration according to the clockwise flying wire entries around the queue while on lines 708 restores the configuration of the channel units and

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10

stores the results in SCSO. In addition, the precomputer will wait for the completion of this procedure. When the state logic 703 offers via a register 702, an input 719 receives a signal on the input wiring 498 indicating towards the immediate priority logic 714, namely the state of the procedure. started has been completed, a decision has been made

channel associated with the content of SCS15. At the same time, the killing unit as to what the next procedure is, if there is any control multiplexing 704 receives the 4-bit channel address 5a. When all the procedures specified by logic 719 on the input wiring 426 from the EAR (not shown) of have been executed, the procedure logic 719 indicates a unit I of FIG. 1. The control multiplexer 704 receives condition with a signal to the result logic 725. This further an operation code and a last interrupt information thereafter and when the associated channel information on the wiring 426, sent by the register 702 to the logic of in the organization register 721 is also shifted in the immediate procedure OCL 714. In addition to the input received at io the SCS2 stage, causes a modification in the setting for starting from unit I by l Through wiring 426, the multi-channel status from "operation in progress" to "command plexer selection 704 returns initial information".

command to control unit I via wiring In Figure 5, the OCL 429 uses the OCL result register 716 to set condition codes and to indicate that the (OCLRR) 469 and the register immediate OCL (OCLIR) 722 for operations specified by unit I are completed. Multiplexer 15 places new SCS information in SCS 2.

704 command receives this condition code and information The OCLIR is used when possible to carry out completed operations via inputs from the decisions of a cycle as to the setting of certain zones OCL 714 immediate priority logic and SCS logic.

OCL procedure 719. The setting of the OCLIR is determined by the integrated

The information in the SCS15 stage is transferred in an OCL 714 diate.

synchronous with each cycle in stage SCS 0 where it is locked for 1 cycle. Likewise, the stage SCS15 receives and locks The latter receives the SCS information (GTS, OLS, etc.) to the new information in each cycle from the stage starting from SCS 0 and the conditioning information of com- SCS14. request (such as input / output operation now) from

SCSO offers a 46-bit input to the procedure logic 25 of the control multiplexer 104. This immediate combined information OCL 714. The latter waits for the information to be introduced into the immediate logic OCL during the floor cycle circulating in the floors 710 flows, and that the in- where the channel is located in SCSO. Immediate logic examines mation on the channel specified by the 4 channel bits on the wiring this information and makes decisions as to which setting of 426 flows to the SCSI stage. When this channel addressed pre-locks in OCLIR. As the channel goes to SCS 1, it senses its status information in SCSI, the logic 714 deterrents of OCLIR are set. As the channel switches to SCS 2, undermines the operation to be performed. If the channel addressed such as the OCLIR locks command the introduction of the SCS zones that determined by the state circuits 428 is otherwise inactive, the specified in SCS 2, via the result logic-OCL 429 then acts to copy the contents of SCSI to the tat725.

organization register OCL 721 (OCLSR). Simultaneously, the OCL immediate procedure logic 714 causes an "instruction" The OCL immediate logic register 722 may assign "to be transferred to the OCL immediate register 722 (OCLIR). seven areas of SCS:

Register 722 brings, via one of its outputs,

OCL 725 result logic to modify state information 1) UTF

channel for the channel addressed, currently located in SCSI, 2) GTS

from "inactive" to "operation in progress". The transition from inactive to in 40 3) DTP

course occurs when information in SCSI is transferred by 4) IS

the result logic 725 at SCS2. 5) IS

With the information in SCS2 indicating that a condition 6) bitsSKEP & PCl of operation in progress exists, the organization register 721 con- 7) DACLP

holds information as to the nature of this operation, 45 The IM logic diagram below represents the states logi-joint with sufficient information to initiate the operation and output of logic 714 and is constructed using ration. During this time, the unit I waits for the return signal on conventional logic circuits:

lines 716, which will condition unit I to continue processing instructions in the instruction stream. The OCL IM logic diagram OCL 719 procedure logic with its input from 50 PCI & SKIP (jump)

organization register 721, analyzes the content of this register 0 - no change to initiate the procedures which will have access to the memory of 1 - set PCI & reset SKIP to the initial channel state (including the local channel memory 406 and the subchannel buffer 408). The channel memories are made DIP accessible to obtain and lock the state of the sub-channel 55 0-no change addressed. The subchannel is identified by the data manipulator 1-set DTP to 0 neas with its 8-bit device number entry on the wiring 426. The OCL 719 procedure logic initiates, by UTF through the register ( PRTR) 724 sequences in the 00 - no change to OCL 726 sequence device. The latter includes routines 00 01 - not used sequential logic tines to perform functions of com- 10 -set UTF to 6 command, by the Intermediate 11-set UTF control point decoder to 7 OCL 706, which boots registers 404, the data manipulator 405, and the four parts 428,429,430 and 432 of the channel control IS logic 403 to perform the required functions. 65 00- no change

When the procedure logic 719 has caused the device 01 — set sequence 726 to initiate a particular procedure, the logic set IS 2 to that of procedure 719 is then in a standby state for H-set IS 3.

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GTS

00 - no change 01-set GTS to 50 10-set GTS to 00 11 - set GTS to 66 and DACLP to 0

OLS

00 - no change

01 - set OLS to "inactive"

10 - set OLS to "transfer"

11 - set OLS to "fictitious"

In Figure 5, the OCL priority logic 715 works in conjunction with the OCL organization register (OCLSR) 721 to determine which procedure will be performed by the OCL 429. The latter is capable of performing many different control procedures. As each new channel passes through SCSO, the OCL 715 priority logic must determine whether or not a new channel is to be served by a control procedure and whether the OCL 429 is inactive or whether the procedure required for that channel has priority higher than other channels that have requested OCL 429 services.

The OCL 721 organization register operates under the control of priority logic 715. The 721 organization registers include a pair of locks for each of the initial procedures to be performed by the OCL 429. Each pair of locks is a combination master-slave of locks. Priority logic 715 queries the SCSO to determine if any of the procedures that can be performed by OCL 429 is required by the channel in SCSO. If a request for a procedure is made, the master lock corresponding to this procedure is automatically set in register 721. Only one master lock will be set at any given time. The master locks in register 721 are synchronized with each cycle (by conventional means not shown), each time that SCS is synchronized. The output of each master lock supplies its corresponding slave lock in the register 721. However, a transfer takes place from the master lock to the slave lock only when the priority logic 715 determines that a transfer should take place. OCL priority logic is conventional logic for comparing the content of master locks with that of slave locks in register 721, in order to determine whether the procedure required in master locks has a higher priority than that in slave locks. The various procedures that OCL 429 is capable of executing and which will be described below in connection with the procedure logic 719, all have a priority to be assigned beforehand. For example, higher priority procedures receive a higher numbered location lock and lower priority procedures receive a lower numbered location lock. The logic of priority 715 is therefore essentially a conventional comparator. If the master lock has a higher number than that of the slave lock, the comparator output from priority logic 715 synchronizes the slave locks in register 720, causing the higher priority procedure to be transferred to the slave locks. If the procedure identified in the slave locks already has an equal or higher priority, no output is produced by the priority logic 715 and the previous procedure remains locked in the slave lock. The content of the slave lock in register 721 specifies the following procedure to be executed by the procedure logic 719. Although the priority logic 715 has been described as a simple comparator and gate control between the master and slave locks, others more complex priority circuits can be used. For example, the basic priority comparison scheme between the contents of master and slave locks can be extended by blocking the output of the comparator under certain conditions or by forcing, in another way, the transfer of master locks to locks slaves despite the fact that the output from the comparator did not take place. The operation of the priority logic is that of a two-bit state machine. There are four states for the state machine, namely 00,01,10,11.

The states of the organization register state machine (SR) have meaning only when the slave locks of the organization register contain an OCL procedure request (SR full). The state machine SR determines whether the slave locks of the organization register should remain similar, or be reset and allow the loading of a new request from the master locks of the organization register. .

The states are defined as follows:

State 00 - Rewriting on slave locks.

When SR full is armed, this state indicates that the OCL procedure logic is busy executing an OCL procedure, but for any channel other than that found in SCS 1.

We enter this state when:

1 °) OCL is not inactive,

2) the channel number in SCS 1 is not equal to that in the OCL action register 720 or the OCL result register 469 (this comparison is carried out when the channel is in SCS 0 and locked for l 'use in the next cycle, when the channel is in SCS 1).

Action during state 00:

A comparison is made between the master and slave locks of the organization register in order to determine whether the master locks have a higher priority than that of the slave locks.

If the master locks of the organization register have a higher priority, the slave locks are synchronized. This brings about a reset of the current request and the transfer of the request in the master locks to the slave locks. The slave locks are set while the requesting channel enters SCS 2.

40 State 01 (channel number in SCSO = channel number in slave locks):

This state indicates that the OCL procedure logic is executing an OCL procedure for any channel, 45 that the slave locks of the organization register contain a request to be executed and that the channel then in SCSO is the same channel for which slave locks contain a request.

At this point, it is possible that the channel in SCSO no longer requires an OCL procedure or requires a procedure different from the previous one.

We enter this state when:

1 °) the OCL procedure logic is occupied;

2) the slave locks of the organization register contain-55 a procedural request which has not yet been accepted by the procedural logic (full organization register);

3) the channel number in SCSO is identical to that then found in the slave locks of the organization register.

60 The slave locks of the organization register will be synchronized and there are then three possible results:

1 °) the channel in SCSO no longer requires an OCL procedure. The slave lock of the organization register which is set will be reset and SR full will be canceled.

65 2) the channel in SCSO always requires a procedure but different from the previous one. The current slave lock that was set is reset and a new one is set to translate this new request. SR full remains set.

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12

3 °) the channel in SCSO always requires the same procedure as before. The slave locks in the organization register are synchronized and the slave lock that was set remains the same. SR full remains set.

State 10 (keep SR full): 5

This state indicates that the full organization register lock should remain set even if the OCL procedure logic is inactive.

Some of the OCL procedures require that SCS information be loaded into the action register 720 from SCSI io before the procedure can be executed.

Normally, when the OCL procedure logic terminates a procedure and becomes inactive, the request in the slave locks of the organization register is accepted by the procedure logic and SR full is canceled, which allows the following procedure request to '' be transferred from master locks of the organization register to slave locks.

However, when the OCL procedure logic becomes inactive and the request in the slave locks of the organization register requires SCS information, the state machine SR 20 goes to state 10. It remains there until the channel associated with the request reaches SCSI. At this time, the action register 720 is loaded from SCSI and full SR is reset. We enter this state when:

1) OCL is inactive (the procedural logic is not then busy executing a request);

2 °) the slave locks of the organization register contain a request (full SR set);

3) the OCL procedural logic did not start executing the request because the necessary SCS information was not loaded into the action register.

Action during state 10:

1 °) SR full cannot pass to the initial state.

2 °) the slave locks of the organization register cannot be modified. 35

When the channel with the request in the slave locks of the organization register enters SCSO, signals are produced to allow the action register to be loaded from SCSI during the next cycle. At this time, inactive OCL will be canceled. 40

State 11 (set SR empty):

This state indicates that the request in the slave locks of the organization register will be accepted by the OCL procedure logic during the next cycle.

Empty SR will be set, allowing any request in the 45 master locks of the organization registers to be transferred to the slave locks.

We enter this state when:

1 °) OCL is inactive.

2) the slave locks of the organization register contain a request.

3) the request in slave locks does not require SCS information from SCSI or, if this is the case, the information has already been loaded into the action register.

Action during state 11:55

1 °) SR full is brought back to the initial state.

2 °) if the master locks of the organization register contain a request, the slave locks of the organization register will be synchronized and set so as to translate this request. 60

OCL 715 priority logic typically includes a full / empty organization register lock (not shown) which refers to the organization register slave locks only. If the slave locks contain a request that has not been accepted by the OCL procedure logic, the lock is set. When the OCL procedure logic ends its current operation and becomes inactive, certain conditions allow this logic to accept the request in slave locks and the processing of this request begins. At this time, the full organization register lock is reset (and empty organization register becomes active).

Normally, when the OCL procedure logic becomes empty, the request then found in the slave locks is immediately accepted by this logic. However, some procedural requests require that SCS information be loaded into the OCL action register before this procedure can be completed (the path for SCS information is from SCSI to the action register). When this occurs, the OCL priority organization register state machine goes to state 10, which prevents the full organization register from returning to the initial state until the channel performing the request enters SCSI. When a request in the slave locks has been accepted by the OCL procedure logic, the slave locks of the organization register are logically empty (full organization register is canceled). However, the current slave lock will not be reset until a new slave lock is set.

The full organization register lock is set when all of the following conditions occur:

1 °) there is no request at this time in the slave locks.

2 °) the channel in SCSO has a request for an OCL procedure.

3 °) the channel in SCSO is not then in the action register OCL 011 the result register OCL.

The lock is returned to the initial state when any of the following conditions occur:

1) a reset to the general initial state of the system takes place.

2 °) the priority state machine = 11.

3) the priority state machine = 01 and there is no procedural request for the channel then located in SCSI.

The lock is prevented from entering the initial state when the priority state machine is equal to 10.

There are four channel numbers maintained in registers in OCL and each of them is 4 bits wide. Channel numbers are channel number for master locks of organization register (CN-SM), channel number for slave locks of organization register (CN-SS), channel number for register action (CN-AR) and the channel number for the result register (CN-R).

The channel numbers in the registers make it possible to follow which channel is at the time considered in each phase of OCL (organization register 721, action register 720 and result register 469). The registers are associated in the manner of a link system.

The CN-SM channel number is synchronized by the normal clock and is loaded with each cycle, while the remaining channel numbers are loaded with their corresponding register as described above.

The priority logic 715 of Figure 5 typically includes a channel status lock not in process (CNIP) that is not shown. This lock indicates, when it is set, that the channel in SCSO is neither processed in the action register720, nor maintained in the result register 469 for introduction into SCS2.

This lock informs the priority logic, OCL that the channel in SCSO can be placed in the slave locks of the organization register if:

1 °) the channel has a procedural request, and

2) the slave locks are available to accept a new request.

At each cycle, this state machine is adjusted or reset to translate the condition of the channel in SCSO.

Priority logic 715 also typically includes an OCL distinction lock which is set in two cases.

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1 °) when the OLS zone in SCSO is equal to chain. This allows the OCL to recognize that OLS entered SIOF from a string rather than from a SIOF instruction.

2 °) when the CICLP crosses CPPPP during the waiting chain data. This allows the OCL to place the appropriate CCW address in the CSW in the event that data transfer is terminated before the byte count reaches 0.

In FIG. 5, the OCL 719 procedure logic comprises a conventional state machine (not shown), such as a counter or a register. The OCL procedural state machine consists of five states, namely inactive, job, job 0, job 1 and output.

The state machine is controlled by conventional control and decoding logic in the OCL 719 procedure logic which is defined as follows in combination with the states.

The state machine is "inactive" when the OCL 719 procedure logic is not busy executing an OCL procedure.

When the OCL 719 priority logic detects that a procedure is requested by a channel, the request is placed in the slave locks of the OCL organization register 721 and the full SR lock is governed.

If the procedure request is "search for CAW", "press data chain" or "fictitious 1", the signal "wait for action register" (WAAR) is put into action. If the request is for any other procedure "WAAR" will be inactive.

Depending on the state of "WAAR", the OCL procedure state machine will do the following:

1 °) it will go to the “work” state during the next even cycle. If “WAAR” is inactive and SR full is active, the OCL procedure state machine will enter the working state during the next even cycle.

2 °) Or it will wait for AR full, then go to the state of "work" during the next even cycle.

This signal is used to load the channel number of the OCL 720 action register.

4 °) Set SR to vacuum.

This signal, together with the inactive state of the OCL procedure state machine 5, sets the OCL priority organization register state machine to 11. This resets the SR lock full. SR full being canceled informs the OCL 719 priority logic that the procedure request in the slave locks of the organization register has been transferred to the PRT 724 io and that the slave locks are now logically empty.

The OCL procedure state machine in the working state allows the procedure locked in the PRT register 724 to be executed.

When the execution of the procedure is finished (for example, a counter reaches a maximum count value and is reset), the OCL sequence state machine reaches the inactive state, which informs the procedural state machine that the procedure has been executed.

When the OCL sequence device goes into the inactive state, 2o the procedure work state will be reset if AR full is active. If not, the work state remains set until AR full becomes active.

As indicated previously, the procedure appearing first can be executed before the action register 25 OCL is loaded with the information of the SCS channels coming from SCSI. However, if a second procedure is to be performed, the SCS information must always be found first in the OCL action register. Therefore, the full AR signal must be present before the working state is returned to the initial state. 30 The OCL procedural machine will go from working state to working state 0 when all of the following conditions occur:

1 °) the action register is full;

2) the OCL sequence device reaches the inactive state, which signals the completion of the procedure in progress;

3 °) it is an odd cycle;

4 °) the procedure performed is one of the following:

If "SR full" and "WAAR" are both active, the OCL procedure machine will remain in the inactive state until "AR 40

full ”becomes active, then goes to“ working ”state

during the next even cycle. "WAAR" signals to the OCL procedure logic that the procedure request is a request that requires that the SCS information be loaded into the OCL action register 720 before the procedure can be executed. "

When the requesting channel enters SCSO, signals are generated to allow the action register to be loaded with the necessary SCS information during the next cycle (while the channel is in SCSI).

When the action register has been loaded, the “AR so full” signal is produced and the OCL procedure state machine goes to the “working” state during the next even cycle.

As the OCL procedural state machine goes into state

"Work", four control signals are produced.

1 °) PRT clock conditioning (PRCE). 55

This signal allows the procedure transfer register (PRT) 724 to be synchronized by the clock. The SR full signal and the procedure state machine not in the inactive state condition the procedure start signal. This, together with the clock conditioning signal PRT, & o regulates the procedure (lock in the slave locks of the organization register OCL) in the register PRT.

2 °) Starting

This signal causes a conventional sequence device (not shown) such as a counter, to exit the inactive state which allows the procedure logic to start processing the procedure which is locked in the PRT register.

3 °) SCHRA clock conditioning.

A) memorize CSW2

B) search for sub-channel status

C) send STW

D) find out the status of the device

E) search for CCW1

F) search for CCW2

G) search for IDAW

H) translate

I) search for CAW and parity bit 0 is set.

If any of the other procedures are executed, the OCL procedure state machine goes from work to work 1.

The above combination produces a "delay" signal. The latter indicates that the OCL sequence logic needs two additional cycles (after the OCL sequence device reaches the idle state). The means offered by LCS and the “OK for OCL” signal from the SU / LCS multiplexer will be necessary.

Action during "work 0" state.

Job 0 is a two-cycle delay state and no action takes place.

Reset to “work 0”.

The state of "work 0" is returned to its initial condition during the next odd machine cycle after its adjustment.

We will now consider the "job 1" state of the OCL procedure.

The "job 1" state is set by one of two methods:

1 °) during the next odd cycle after "work 0" is set, if "work 0" is started.

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2 °) during the same cycle or the "work" state is brought back to the particular procedures state among the OCL procedures, for example. initial, if "delay for OCL procedure" is inactive. pie FCCW1, FCCW2, FCAW.

Action during "work 1" state. When the signal “request entered” is applied by a device

The "job 1" state indicates that an OCL procedure was positive input / output via a communication device.

completed. If the signal “end of OCL procedure” is active, it was 5 request 411, the CICL 432 will enter a call sequence for the last procedure in a chain of procedures. selective (GTS = 30). In GTS = 32, the address of the input / output device is stored in the zero word of LCS. GTS Example - Procedure chain goes to state 33 until the input address signal drops

F CAW and the input status signal is produced. The GTS then goes to state

FCCW1 10 ready (37).

FCCW2 When OCL detects the ready state of GTS (and OCL is

Keep modes (last in the chain) inactive), the sub-channel status search procedure will be executed. This obtains the input / output address of the word zero from At the end of each procedure, the LCS process state machine and places it in the input / output address register 479.

hard OCL enters the "work 1" state. At the end of the process, the signals “WR00-07 versIOAR”, “selection LCS for duration“ keep modes ”, the signal“ end of OCL procedure ”will be write multiplet 0”, “selection LCS for writing” and “condi- also active. IO AR clock operation ”are produced by the OCL in order to

We enter the exit state when the last process to transfer the entry / exit address to the chain endure address register has been completed (end of OCL procedure) and that entry / exit479.

OCL sequence machine is in "job 1" state. 20 When the subchannel status search procedure is

The exit status cannot be set if the result register, the procedure move ESB and IOAR to OCL status buffer contains information that has not yet been sent interrupt (MEBI or MEDI) is executed. This procedure to SCS send OCLRR active). obtains the address of the input / output device from the address register

The output state is set for one cycle only. In the input / output cycle 479 and places it in word 6 of byte 3 of the following after the output state, the procedure state machine 25 LCS.

OCL goes to inactive, which allows the start-up of a new signals “DMOR movement towards DHR Cl”, “condi velle procedure. DMOR clock operation ”and“ DAR selection to multiplet

When a channel requires an OCL procedure, it is possible that 3 DMORs are produced by the OCL in order to transfer the address that more than one procedure must be executed. entry / exit in the DHR 439 register via the

For example, when "input / output operation now" 30 selection circuit 487.

and SIO are active and that GTS = 00, the procedure "search for Signal" input / output operation now ".

CAW ”(FCAW) is executed. After the CAW has been obtained, When the unit I decodes an input / output instruction (SIO, the procedures "search CCW1" (FCCW1), "search TlOetc), it reads the line" input / output operation in progress "CCW2 ”(FCCW2), and“ keep modes ”(SVMD) are executed on unit C. It also sends the channel / device address set. When "search for CAW" is finished, the logic starts from unit WAR register I on the wiring 426 to register 479 automatically starts "search CCW1". When “re- figure 4.

search CCW2 ”is finished,“ search CCW2 is automatic. The control multiplexer 704 detects the signal “operatively started. After "search for CCW2" is input / output in progress "and compares the mine address in response," keep modes "is started. When this last channel received with the channel address in SCS F (SCS 15). At start-up, the signal “end of OCL procedure” is produced. 40 that the two addresses are comparable, the communication multiplexer

This signal implies that the last procedure in a chain has been requested. 704 sends the isgnal "main entry / exit operation. nant ”at OCL.

When this last procedure is finished, the OCL machine locks the signal “main input / output operation

OCL procedure state enters "job 1" and the result is "while the channel goes to SCS 0.

combined effort procedures is placed in the register of 45 As the channel goes to SCS 1, the OCL:

OCL result and the “send OCLRR” lock is set for signa- 1 °) sets the procedure “search for CAW” (for 1st locks that the OCL result register is full. master of the organization register) if OCL is inactive and that GTS

The “procedure start” signal is produced when the ver- is equal to the operation in progress, selective call sequence 1 or rou “SR full” is set (which indicates that the locks of inactive.

organization register have a procedural request which 50 2 °) governs the “STTDC” procedure (for master locks of has not been executed) and that the OCL procedure machine registers organization) if the instruction of unit I was "memo-finds in idle state (which indicates that no procedure is riser channel ID" and that OCL is inactive and that GTS is equal to running by the logic of OCL procedure). operation in progress, selective call sequence 1 or inactive.

The “start procedure” signal allows the procedure 3 °) locks “input / output operation now” in the in the slave locks of the organization register to be trans-55 master locks of the organization register. If the instruction of fairy and locked in the register PRT. unit I does not require CAW, the procedure “search for CAW”

The “start for process sequence device” signal is however always executed.

hard ”is produced when the OCL procedure machine is When the clock synchronization for locks is

set to working state or when work 1 is active and the end of the organization register claves occurs, the signal “OCL procedure operation is active. 60 input / output now ”is locked in the locks es-

This signal regulates the OCL sequence machine states “slaves of the organization register.

main sequence 0 "and" sub-sequence 0 ". This allows the When the action register becomes inactive and is ready to act

procedure locked in the PRT register to start accepting a new request, the action register lock "operated

process the OCL procedure logic. input / output ration now ”is set.

The SU LCS 704 multiplexer contains the line “not operating. 65 The OCL controls the IS area of LCS 0. When a unit channel S”. This line is normally active and must be requires that a CSW is memorized, OCL notes the signal "set denied by OCL if the latter requires a data transfer to interrupt request". If the interruption is masked, the multi-or from the unit S. This negation is carried out by command plexer 704 sends "request interruption" to the user.

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nity I. When the latter is ready to process the interruption If CICLP minus CPPPP is greater than 0 (at the end of

(allowing CSW to be memorized), “acceptance of interruption” transfer of data) and that the OCL distinction bit is set, is sent to unit C. all the data for the current CCW has been transferred.

After detecting “interrupt acceptance”, the multi-CCW address correction is not necessary.

control plexer waits for the requesting channel to arrive 5 If CICLP minus CPPP is less than 0 or the • bit during the cycle in SCS F (SCS 15). When the OCL distinguishing address is canceled, all data for the CCW channel in RCHR is equal to SCS F, the current multiplexer has not been transferred. The CD support procedure is sent sends "interrupt now" to OCL. Interrupt executed to correct the CCW address.

now has a cycle length and will occur each time The OCL 719 procedure logic is of the sequential type that the channel number in RCHR is equal to SCS F, until conventional 10 which performs several different procedures. The logic input / output signal (IOCP) from OCL is received as 719 is defined according to a SIOF instruction. This indicating that the CSW has been stored. The last multiplexer causes the application of an input to the command multiplexer waiting for acceptance of interruption to occur, of command 704, as indicated previously. The latter so that the unit I and the control multiplexer become- transmits this input to the priority logic 715 which acts inactive. 15 so as to set the operation lock now in the ver-

As the channel enters SCSO, the priority logic rous slaves of the organization register 721. When the latter OCL locks the interrupt signal now. This lock includes the slave lock operation now set, the logi-executes the following functions: that of procedure 719 is excited in response to execute a

1 °) if OS = 4 (secondary interrupt), the procedure interrupt interrupt. At the moment when the operation operation lock now sets GTS for operation in progress (50), by 20 now is set, the channel number associated with the instruction via the immediate register OCL to prepare the se- SIOF is also stored in the action register 720 of the initial reading; as previously described.

2 °) if we have IFC, CCC or PCI, the master lock procedure The first procedure executed by the organizational register procedure logic for AIC1 is set; 719 is search word channel address (FCAW). This process

3 °) preventing a request for a master lock procedure for a duration of 25 has the function of giving access to a fixed location of the organization register for searching for device status; main memory 2 (via the memory unit

4 °) prevent the setting of a verification procedure request 4) in order to obtain the word channel address (CAW). rou master of organization register for DMY1. In the embodiment of the present invention, this word

As the channel enters SCS 1, the master channel address lock is located in the OCL priority interrupt organization register storage address 48 now the main memory. The 719 procedure logic is set. This is the same cycle where the priority master locks therefore a conventional sequential logic that generates the OCL are set. following sequential signals to search for CAW at work

When the OCL priority logic allows the request to identify 48. The procedure logic 719 transmits a procedure address in the master locks of the fixed organization register 48 as an entry in the SUAR register 464 and causes this to be transferred. to the slave locks of the organization register, address to be locked in this register 464. The logic of the slave lock of the mainte- nance procedure organization register 719 then transfers the content of the register 464, therefore is set. via circuit 435 and without modification, to unit S on wiring 353. The content of the main memory location-When the action register accepts the request for a cipal procedure is returned to the channel unit via the locks of the slave locks of the organization register, the lock 40 40age 394. The information of the latter is locked in the interrupt action register now is set. register WR 466. Procedure logic 719 provides a signal

During an input string data operation, all to lock the WR register in a conventional manner. The bytes of incident data (for the current CCW) are the following sequential function of the procedure logic 719 placed in the main memory before OCL search consists of sending out a signal to load the content of the next CCW (no prior search of CCW does not take place). 45 LCSAR 467. The purpose of loading register 467 is to

During an output chain data operation, OCL mer an address for the local channel memory 406 where the next CCW must be sought before when CICL 16 has stored the CAW which is located in the register WR 466. Being bytes of data or minus (from the current CCW) given that memory 406 has an assigned location for further transfer to the input / output device. After each of the 16 channels, the top rank area for the address

CCW has been searched beforehand, DACL search beforehand 50 in the memory 406 is obtained from the channel number, probably the data for the CCW searched beforehand. The channel number for the channel on which this mo is working. If the data transfer to the input / output device lies, the OCL is stored in the action register 720. It ends abnormally, it is possible that the CICL works has been placed automatically at the moment when the data operation lock is either for the CCW in progress or for that now has been set in the organization register 721. The sought beforehand. In order to place the correct CCW address 55 channel number is transmitted from the action register 720 in the CSW, special logic is used. Part in the higher rank area of LCSAR 467. The main logic of this logic involves the CPPPP. procedure directs the lower rank area to a location

The OCL determines that CICL has 16 bytes of data or any preassigned for the CAW, which is for example the remaining em-less thanks to the following formula: placement 4. This address is locked in the register 467.

BBC = 0 and EX = 0 and ADB> 16 = less than 16 again. 60 During the period when the address is locked in the register When this condition is satisfied, the DACLP of SCS 1 467, the sequential logic takes the contents of the register WR is transferred to the OLS area of SCS 2. We will then refer to 466 as an input for the data handler 405. The this value as the CPPPP. It will be noted that the sequential logic DACLP of the logic system 719 in FIG. 5 is the last multiplet indicator of the current CCW. requires the door transmission directly through the handle

If the data transfer to the input / output device is 65 data pulverizer 405 through the abnormally select-control circuit, the suitable CCW address (for the 488.

CSW) is calculated by preparing CICLP for CPPPP and examining it in FIG. 5, the selection command 488 is simply setting the distinction bit OCL. constituted by selection gates which control that of

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of the selection circuit 487 which is selected. In Example 4) to specify the address in memory 406 of this example, the OCL 719 procedure logic causes the command word address in main memory. This selection of the wiring 424, so that the password address manipulator has already been increased by 4 as described in data 405, with regard to the present procedure, not previously, and therefore now constitutes the word address does not mean the data. The output of selection circuit 487 appears as channel 2 command, CCW2.

rait on the wiring 425 and is locked in the register 437 of the This operation completes the procedure FCCW1, which in FIG. 3. The sequence device 706, after the locking of the trains, the locking of a new procedure in the data register in register 437, locks them in register 439 724. This new procedure is intended to search for the word which, in turn, offers them as an input to the channel memory of order of channel 2 and is designated by FCCW2.

local 406. The CAW is placed in the local channel memory 10 The procedure FCCW2 is essentially identical to the 406 at the address specified by LCSAR 467. At this point, the procedure FCCW1. The address in the main procedure memory named FCAW has been completed. CCW2 is reached from local channel memory 406 and

The procedural logic indicates that the FCAW procedure is placed in register 468 to be locked in turn is finished, which causes a new lock to be set in register 464. From the latter, it is directed to the PRT register 724 for conditioning a new procedure 15 the storage unit and the latter returns the address to which is looking for channel command word 1 (FCCW1). When the register WR 466. At this time, the sequence logic device 706 procedure logic sets the lock FCCW1 in the register increases the zone of lower rank of the register LCSAR 467 in order PRT 724, a sequential procedure FCCW1 begins and it stores the content in register 466 in memory is defined as follows. The purpose of this procedure is to search for local channel 406 at a new address location by searching for the address of the order address word location in 20 core. The content of the register WR 466 (containing CCW2) is LCS 406 and to use it to have access to CCW1 from the directed via the wiring 424 in the main memory manipulator via the storage unit 405 In the latter, the CCW2 appears on the wiring 424. The tion 4 of FIG. 1. The sequence device 706 first makes functional control 490 causes CCW2 to be directed to output a trigger signal to transmit the content to the adder 483 without modification, in order to appear on LCSAR in order to address the local channel memory 406. When wiring 492. At this time, the 11-bit area on the wiring that it is so addressed , the main memory address of 492 is entered as an input in the EX CAL 471 circuit and CCW1 is transmitted by door in the LCSFDR 468, via the BBCR circuit 470 to produce a wiring media counting area 421 The sequence device 706 generates multiplier on the wiring 458. The latter is connected to the log ler the lock signal controlling locking in the result register in order to send the initial count in the SCS to tre 468. Next, the address coming from register 468 is led 30 moment desired.

under the control of the sequence device 706 in the register The data manipulator of FIG. 4 comprises the SUAR 464 and simultaneously in the register WR 466. The command register 446 which receives and stores the order coming from the register SUAR 464 is directed without modification and by a channel command word, a flag register 477 which receives the intermediary of circuit 435 as well as wiring 353, towards and stores the flags coming from a command word of channel unit S. In the latter, there is access to CCW1 which appears 35 and the status register 476 which receives and stores the status from on the wiring 394. At the same time as the address has been directed of a channel password. These values, under the control of the by wiring 353 to the storage unit, the content of the procedure logic 719, are made available for the WR logi-register 466 to be in the data manipulator 405. The only result for an introduction into the SCS appro-sequence device zones 706, in a conventional manner, produces a request when the result logic 725 is conditioned for signal for the functional command 490. This last re- 40 sending. When the FCCW2 procedure is completed by the signal which specifies the input by door in the sitive adder of sequence 706, the necessary information has been made dis-483 of figure 4. This adder 483 is controlled from available for the result logic for loading the SCS. to add plus 4 (which is equal to four bytes) to The final procedure in procedure logic 719 is called

the address on the wiring 424 which was derived from the register WR mé “mode of conservation of mode”, during which 466. 45 certain information is placed in a location of the

The augmented address from the local channel adder 483 adder 406. For the purposes of the present invention, rait on wiring 492 and is selected by a mode preservation circuit can be ignored. When the conservation

selection 487, under the command of the mode selection command has been completed, it signals the completion of the 488. The latter selects the wiring 492 as being the procedure chain for the OCL 429. After the procedure exits on cabling 425. The address on cabling 425 is ver- if mode conservation indicates completion, the rusty logic in register 437 of figure 3 and in register 439. result 725 sends the information zones defined previously-The address is loaded into LCS 406 at the address specified by SCS 2 to signal that it is now time for the address register 467. Jointly, the result of unit S DACL 430 computer and CICL 432 computer begin appears on the wiring 394 and is memorized, under the command to transfer data and to make OCL inactive. When in sequence device 706, in register 466. At this idle time, the OCL can begin a procedure for another purpose, sequence device 706 introduces a new channel zone.

of lower rank in LCSAR (e.g. 8), which, prior procedures have been discussed by admitting jointly with the higher rank channel number field, that only one channel had priority and that OCL 429 was total-forms a new address location for the memory assigned to the processing of a channel. The local channel procedure string 406. This new channel address location is fio FCAW actually has a priority of 2. Other prio procedures - that of the actual data address which is obtained from rity 1 could cause the FCAW procedure to wait before CCW1 stored jointly in register WR 466. The to be processed by the OCL.

sequence device 706 completes the procedure FCCW1 in diri- In Figure 6, we are presented in more detail the giant content of register 466 through the manipulator of data access control logic (DACL) which makes per-data 405 in registers 437 and 439 to location 65 of the channel control logic in Figure 5. The DACL memory 406 specified by the address in register 467. moves data to and from memory channel

At this time, the sequence device 706 reintroduces the local (LCS) 406. During writing operations, the DACL de-cia zone of lower rank for the address register 467 (by place of the data of unit S 4 in figure 1 to LCS 406

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and, then read operations, the DACL moves data The effective transfer length (TL) of a transfer to ef-

from LCS 406 to the S. unit performed by the DACL is typically four multi-

The DACL is a link processor or processor that creases and is determined by a 2-bit TL code from the uses of the offset channel state (SCS). At each cycle, logic 734, which is loaded into the organization register 735. new channel state information is found in SCS 2 and the 5 Other lengths are used, for example if at the end of a DACL processing requirements are determined from transfer fewer than four bytes remain to complete this information. If the DACL performs a processing, during transfer. In this case, the actual transfer length code upon completion a new state information is returned TL represents 3.2 or 1 byte as appropriate. The logic 734 in SCS 2 by the result logic DACL 740. also takes into account other special conditions, such as

The linking system works in 3 stages, namely organizing 10 transfers, for example, approaching a delimitation of action, action and result. Priority logic 734 determines on page and produces control signals on a 3-bit line each cycle if the channel in SCS 2 is to be organized. If the DIT and a 2-bit line TP. These commands are not organization register (SR) 735 is empty and that the channel requires necessary in connection with the object of the present invention and not processed by DACL, the organization register 735 will not be defined any more. detail.

synchronized. This synchronization of the clock places part 15 of the organization register 735 accepts information from the SCS2 information, plus some new information 734 and directly from the SCS2 stage on the 23 cable wiring, in the SR. bits 746. This information includes the old 1-bit EX,

When action logic 739 is available, the old 5-bit BBC register, the channel number and other organizational information 735 will be transferred to the action register (AR) 736. not applicable to the present invention. AR register 736 offers action logic with information 20 Particular interest is in tuning the old BBC area which required to move data to and from the unit represents buffered byte count (BBC) and S. During a read operation, the 1-bit EX zone control logic which presents the extended BBC (EX) bit. The controller device interface area (CICL) 432 places the BBCs is formed by the 5 lower rank bits of the data area from an input / output device in the remaining count memory. The EX bit indicates whether any of the local channel 11 (LCS) 406 and the higher rank 25 bit DACL 739 action logic is present in the count area transfers this data to the S unit. a writing operation. The organization register 735 contains inter alia the ture, the reverse is true, the DACL places data from the unit S BBC, that is to say the 5 lower rank bits of the zone of in LCS, while the CICL removes the data and sends it to the desired count, the EX indication as to whether any bits have an input / output device. At the end of a conch operation among the 11 bits of higher rank exist in the data input or output area, the DACL 739 30 action logic of counting at 16 bits, and the indication TL of the length creates new states for the channel we are acting on. The actual information transfer to be undertaken during the present state operation is then transmitted to the result logic for a DACL operation. The information in the organization register sends to the shift channel state (SCS). 735 defines the next transfer to be executed by the DACL. The

There are two result registers in the result logic, content of action register 736 represents the transfer executed Result register 1 (RR1) 737 receives data from the 35 at this time by the DACL. When the transfer in progress makes sense for action. Result register 2 (RR2) 741 receives completed information on the next transfer in the RI data and sends it to SCS2 to be reported. Register 735 is loaded in register 736.

so the result registers act as a link system to buffer results of up to two The contents of action register 736 is sent as-

different operations. 40 following the DACL 739 action logic. The latter is a

To summarize, the complete DACL link system can combine logic that traverses a fixed sequence by having four channels at various processing points. A function of the input from the action register 736. The channel logic can be organized in the action organization register (SR) 735 uses the action state register 739-2 to store and be waiting for action. Another channel may be the sequence states of the DACL action logic. The function-in the action register (AR) 736 while the action logic 45 n sequential action logic 739 command of DACL works on this channel. Two channels can have numerous time setting signals which are output to the result in the result register 737 and the control wiring result register 748. The time setting signals on 741 waiting to be returned for signaling in SCS2 . 748 cabling is locking and transfer data The second stage SCS2 of the conventional shift channel state memory and their particular sequences will be defined cyclically receives information from the SCSI stage on the cabling so after About the operation.

742. At each cycle, the information concerning a new channel The action logic 739 includes a conventional comparator is available for the DACL. SCS2 cyclically outputs one intended to compare TL, the effective transfer length of the information to stage SCS3 on wiring 743 and to CICL rée, with the old BBC. If IL is less than or equal to BBC, the on wiring 744. effective transfer can take place with a short sequence and by

The information in stage SCS2 for each cycle is therefore the action logic 739 and the sequence register folded as input to the priority logic DACL 734, by status 739-2 cause the execution of 'a short sequence through wiring 746 to determine if the channel as described below. If TL is greater than BBC, the old one in stage SCS2 has the highest priority for an action by EX zone is examined. If EX is set (which means that the DACL in Figure 6. If this is the case, the transfer length bits of higher rank exist) at a time when TL is super-effective (IL) to be undertaken is constituted by an output on 60 laughing at the old BBC, the action logic 739 and the register of a 2-bit wiring to the organization register 735. The status sequence 739-2 specify a long sequence. The priority determination in logic 734 may, for example, take a long time to search for bits of higher rank from there being simply an indication of whether or not the DACL is channel memory and then replace the counting area res -busy at this time and, if it is not, priority is given to the aunt in the channel memory. If BBC is less than or equal to any channel which is then in SCS2 by loading 65 maximum transfer length TL (in this case 4) and EX the information in the organization register 735 with a signal is not set, the short sequence is then followed. When the clock-year. Other more complex priority reports may be that the BBC is reduced to all 0s and that the EX is not set, the obviously be implemented. primitive transfer is completed and counting is exhausted.

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In general, the outputs of the 739 action logic even cause, the initial load places an indicator or pointer in the transfer of bytes of information between the memory of a fixed location of the memory, for example the location-

channel and storage unit. In addition to performing this transfer 72 in the present system, which identifies the actual location of information bytes, the first order action logic 739 in the sequence of channel orders. When causes the remaining counting area to be decreased by the amount of the input / output start order is collected by unit I, the amount of actual transfer. According to an embodiment of an effective address register, the latter is loaded with the invention, the reduction in the counting area is obtained in the information which is communicated to the channel unit via the

Originally decreasing the BBC circulating in the state memory and medium of the cabling 426. The channel unit identifies the instruction the counting zone in the local channel memory if starting input / output in the logic state and wait for that to happen. When a carry from the higher order bits is the addressed channel information, which flows through the SCSO stages

necessary, a long sequence is used to gain access to SCS15, arrives at the SCSI location causing a higher rank bit from local channel memory notification of immediate procedure logic when the

406, to decrease the total remaining counting area, and for appropriate channel among the 16 channels reaches the location to memorize the new remaining counting area again SCSI. Assuming for the purposes of this example, that the state of in memory 406. 15 channel addressed is inactive, the OCL allows the introduction of the count

The old BBC and the old EX, prior to the bare transfer of SCSI in the organizational register 721, while the effective, appear in the action register 736. The old result logic 725 modifies the state of the channel (assuming the

BBC is out on 5-bit 460 wiring to channel 5 circuits as a typical example), which indicates by lockout-

data manipulator of figure 4. Likewise, the old EX läge in SCS2 the current operating state. During each coming from the register 736 is output on the line at 1 bit 457 towards the cycle 20, the channel information is advanced by one stage at a time data manipulator of FIG. 4. After processing by the among the stages 710 , so that after 16 cycles, each data manipulator, the new EX on the 1-bit line 418 channel information has progressed through all SCS stages 1 to

is received from the data handler and is stored in SCS15.

Result register 1 (R1R) 737. Likewise, the new BBC is For an input / output start instruction, the information received on the 5-bit wiring 427 and is stored in the channel register 25 continues to progress through the stages 710 where the R1R 737. The channel number is applied as input to the OCL circuits 429 are allocated to a particular channel, the channel 5 result register 737 from a register 749 which stores in the present example. Although circuits 429 are attracted, the value of the last channel having control of the DACL. The fogging on channel 5 for processing, the other parts of the channel logi-number in the register 749 is derived from the channel control ack register (state DACL, CICL) can be tion 736. When the number channel, the new BBC and the 30 used for processing channels other than channel 5. new EX are applied as input to register 737, they For a SIOF instruction, the unit I waits until the unit is available for a load in the channel result register and in particular the OCL have finished processing their 2 (R2R (741. The channel numbers in the two part registers of the channel function. More precisely, for an ins-result 737 and 741 are available as inputs for SIOF pull, the OCL is responsible for finding a logic word of priority 734. In this way, the channels having the channel address in the buffer channel while using the DACL can be used to decide that the v terrifying to ensure that the subchannel state memory is channels served at this time by the DACL have no priority available to process the identified addressed device. Admitting to use the latter. With the new BBC values and as long as the identified subchannel is device 25 (which identi-EX in register 741, these are available for an implicit referral of a subchannel), the procedural logic 719 see in the state memory via the logic of 40 after having access to the channel address word and thus having result DACL 740. located the address of the first channel command word, stores

Logic 740 includes a conventional comparator which re-indicators or order pointers in the buffer of

receives the SCSI channel number on the 750 wiring from the LCS channel and performs validity checks on the information

742 wiring and compare it with the channel number in the mation. In performing these functions, the OCL uses register paths R2R 741. When a comparison takes place, the new data 45 and the common memory to control the functions

EX and BBC values in register 741 are directed to tions.

through the result logic 740 to the wiring 745 where they With the access to the first channel command word, the logic of are introduced into the stage SCS2 with the information coming from procedure 719 means to the control multiplexer 704 that SCSI. The old BBC and the old EX in SCSI are rejected. the SIOF instruction of unit I of the data computer has been

The period of time required to complete the transfer to so completed as indicated on the return lines 716, which the storage unit and the introduction of the new values therefore allows the unit I to continue processing others of EX and BBC in stage SCS2 is a function of the fact that the instruction in its instruction stream.

lower ranking area (BBC) only must or may not be set With the first channel command word obtained, the logic of

updated with a short sequence or if a hold is required and procedure 719 indicates to the result logic 725 that the state of the whole of the counting zone must be updated with 55 initial selection for the associated channel 5 must be entered in a long sequence. the data transferred from SCSI to SCS2 whenever the information

The operation of the channel unit will be described with reference to channel 5 is then loaded into SCSI during its rant to a typical instruction "start input / output released normal shift cycles. When CICL 432 circuits in fast ration ”(SIOF). As initial conditions, all logic 757 detects the initial selection state of a channel nal, 16 in this example, are inactive and must be any 60, they result in a channel buffer access set to initial state by initial program load (IPL) (CBS) in order to obtain a device address and an order and or or, in another way, by a reset order. direct them to the correct physical interface and the

With the initial program loading carried out, suitable input / output commands using the input logic

tions are loaded into the main memory and the remote instruc- tors 407 of figure 3.

tions are sought and processed by unit I. As part "s Admitting that the first order consists in transferring from the initial program load, any instruction input / information from the control unit to the main memory,

output such that SIOF sets a sequence of gold in memory - the CICL manipulates the command lines and the LCS provo-

channel dres which actually constitutes a channel program. As for the transfer of data from the control devices

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entry / exit to LCS. The CICL, through control logic 757 and output wiring 780 to the appropriate channel stage SCS4 or SCS12, maintains a record of the LCS locations that contain the transferred data. When a sufficient amount of data has been collected in the LCS, the DACL recognizes the need for a transfer of the main memory by observing the state of channel 5 while it appears in the SCS2. At this point, the DACL will cause a data transfer from LCS to the main memory.

When the channel password has been obtained from unit I of FIG. 1, it is transmitted under the control of the OCL via the wiring 394 to the working register (WR) 466 in the future. 3. From this latter, it is transmitted by the data manipulator 405 to the wiring 425 without modification and it is locked in the DMOR register 437. From there, it is locked in the DHR register 439 and stored in the channel memory local 406. In this way, the 16-bit counting area is originally stored in the channel memory 406.

When the counting zone coming from the channel command word is directed from the register WR 466, it crosses the adder 483 in the data manipulator of FIG. 4 and appears without modification on the wiring 492. On the latter, the 5 bits of lower rank are extracted and loaded into the BBCR register 470. From there, the initial value of the new BBC is directed to the OCLRR register 467 in FIG. 5.

At the same time, in the manipulator of FIG. 4, the 11 bits of higher rank of the total transfer length zone are applied as input to the computer EX 471 where the bits of higher rank are combined according to an OR logic to form the new initial EX signal on line 418, which is also stored in register BBCR 470 and transferred to register OCLRR 467. From this latter, the new initial values of EX and BBC are directed by logic 725 in SCS2 when SCSI contains the appropriate channel number.

As a typical example, we will assume a total count of 36 bytes. In the 16-bit counting area, the 11 highest-ranking bits include ten higher-ranking 0s followed by a 1 and the 5 lower-ranking bits are 00100. The count appears in binary notation as 100100 preceded by ten higher-ranking 0s .

With the typical example above, the new initial BBC stored in SCS2 by the OCL is 00100. The value stored in SCS2 for the new initial EX bit is 1, since the 11 bits of higher rank are not 0.

With the new initial BBC and the new initial EX memorized in SCS2, the DAC1 is ready to start a transfer of 36 bytes of data each time the channel number 5 gets priority, for the use of the DACL. When channel 5 gets priority, the BBC and the EX for channel 5 in SCS2 are directed to the action register 736. In the latter, the BBC and the EX are then treated as the old BBC and the old EX and are examined in action logic 739. Assuming the usual case of an effective transfer length TL of four bytes, the value 100 of TL is compared with the BBC in register 736 by logic 739. Given that BBC with a value of 00100 is equal to or greater than the value of TL which is 100, the action logic 739 requests a short sequence. The latter is identified in diagram I below.

Diagram - Short sequence

Channel to Unit S Cycles Unit S to Channel Cycles

1 and 2 Find address 1 and 2 data

3 and 4 Search data 3 and 4

5 and 6 Store address 5 and 6 data

7 and 8 "not used" 7 and 8

Find data address "not used" Save data address

Save data

When performing the short sequence transfer of data from the channel memory to the storage unit, the data address in the channel memory must first be reached from the channel memory and placed in the register d storage unit address 464 of FIG. 3 during cycle 3. Each access to the channel memory requires two cycles. Then the data itself must be retrieved from the channel memory using the address in register 467 during cycle 3. The address is established by adding the channel number from the address register 739 to the DACLP zone in register 736. If the address was 100 and TL was 4, the address becomes 104. The data to which we have access are output on the wiring 421 and stored in register 468, from which they are transferred to the register 465 and outputs to the storage unit 15 via the wiring 358. Finally, the modified data address which identifies the next byte to be transferred is stored in the local channel memory 406. The address 104 (100 + TL (4) = 104) was added by the data manipulator 405. During cycle 3, the an-20 old data address in WR 466 is added to TL in CHDM 405 and loaded in DMOR 437 and DHR 439 during cycle 5 and then in LCS 406. A sequence similar is used for information transfer from the storage unit to the local channel memory 406.

During the aforementioned short sequence identified in diagram I, a transfer of four bytes takes place between the storage unit and the channel unit. Therefore, the IL value of 100 can be subtracted from the initial total count area to form the remaining count area. The TL 30 value of 100 is subtracted from the BBC value 00100 in the data multiplier and gives a result of 00000 which is the new BBC.

It will be appreciated that since the initial BBC was 100, the subtraction of 100 from IL was performed without the need for restraint from the higher rank area. Therefore, the old EX bit remains valid and is selected to become the new EX bit. Therefore, the new EX equals l.

After subtracting 100 from BBC, the new BBC is 40 00000. This new BBC is obviously memorized in the register R1R 737 and then in the register R2R 741 in FIG. 6 and it is transferred to the SCS2, which therefore momentarily completes the use of DACL through channel 5.

When the channel number in SCSI matches that of channel 45 in RR2 741, the DACL loads the new BBC, the new DACL flag (now equal to 4) and the new ADB in SCS2. ADB and DACLP are adjusted (decreased and increased, respectively) using the TL in RR2 741.

With the new EX and the new BBC memorized in its stage SCS2, the state memory continues to circulate until channel 5 reappears in SCS2 and obtains priority for the use of the DACL. Since the total transfer of 36 bytes has not taken place, channel 5 will again receive priority for some time from the logic of priority 55 logic 734 in FIG. 6. When channel 5 obtains priority , channel number 5, a new TL value of four bytes, the now old BBC (00000) and the old EX (1) are directed to the organization registers 735. If the action logic is inactive, the register SR 735 will be transferred to the action register 60 736. The old BBC (00000) and the bit EX (1) are directed to the data manipulator on the cables 460 and 457, respectively.

In the present case, the value of TL equal to 100 cannot be subtracted from the old BBC equal to 00000 without a carryover to 65 from the bits of higher rank which are known as existing, because EX is 1. Consequently , a long sequence must be followed in order to properly subtract the effective transfer length (100) from the remaining count (100,000) from the

629,320

20

which we arrived as always by chaining the 11 bits of higher rank of the counting word in LCS with the BBC zone of SCS. The long sequence is summarized in diagram II below:

Diagram II - Long sequence

Channel to Unit Cycles S Unit to Channel Cycles

I and 2 Search address 1 and 2 Search address data data

3 and 4 Search data 3 and 4 Search count 5 and 6 Search count 5 and 6 Save modified data address

7 and 8 Store address 7 and 8 Store account-

data modified tage modified

9 and 10 Save comp- 9 and 10 Save modified tage data

As in a short sequence, the address is sought in the local channel memory. It is now 104. The modified address will be 10 + TL (4) = 108 and it will be remembered in LCS.

In the long sequence of diagram II above, the two additional steps of counting search and modified count memorization are added. During the counting search step, the total compaction area, including the

II bits of higher rank, is sought in the local channel memory and directed to the register 468, from which it is transferred to the working register 466 during cycle 7.

In the data manipulator of FIG. 4, the 11 bits of higher rank coming from register 466 (1 preceded by ten 0) are chained with the bits of lower rank (which constitute the old BBC of 00000 on the wiring 460) and are applied as input to the right connection of adder 483. Jointly, the TL value of 100 is applied as input to the left connection of adder 483 and the left input is subtracted to form the result on the wiring 492. When 100 is subtracted from 100,000, the result on wiring 492 is 011100.

The new BBC is 11100 and the new EX is 0. Since in the particular example chosen, all 11 bits of higher rank are 0, the new bit EX is now set to 0. The 11 bits of higher rank of new counts are loaded in DMOR 437 and in DHR 437 during cycle 9 and in LCS. The new EX equal to 0 and the new BBC equal to 11100 are stored in the result registers 737 and 741.

When channel 5 appears again in SCSI, a comparison is made in the result logic 740 and the new EX as well as the new BBC are memorized in SCS2. Information in SCS2 continues to flow in state memory until priority logic 734 again determines that channel 5 has priority. At this time, the channel number 5, the now old BBC (lllOO) and the old EX (0) are applied as input to the action register 736. The action logic 739 determines that the old BBC ( 11100) is greater than the effective transfer length 100, so a short sequence is requested.

The short sequence is repeated as shown in diagram I above. Four bytes of data are transferred from the channel memory to the storage unit while the high-speed data manipulator subtracts 100 from the old BBC 11100 to form the new BBC equal to 11000. From this moment, the value 0 for the bit EX no longer changes, since no carry-over is necessary from the old BBC.

The operation continues with a short sequence until the new BBC has been reduced to 00000. Since EX is also different from 0 at this time, DACL and OCL

can both determine that the data transfer is complete. The CICL finishes transferring the data and then transfers the order to the OCL after receiving the status (from the control unit) .- After the status manipulation, the OCL hands over the order to the CICL and completes the sequence for put the channel inactive.

When all the data has been transferred, the OCL notes this fact and causes the result logic 725 to operate on the channel state so that the channel 5 becomes inactive. Subsequently, channel 5 is again available to transfer information from the input / output control device to the storage unit.

Although the above example was given for a single channel, namely channel 5, it is evident that while the 15 different parts of the channel control logic are working on the transfer of channel 5, they can act simultaneously on other channels. For example, while status logic 428 is busy with channel 5, OCL logic 429 can work on control information associated with some other channel 20 while, simultaneously, DACL logic 430 can process a third canal and the CICL a fourth canal. As each part of the channel control logic 403 becomes available, it accepts input from the offset channel state (SCS) and begins processing an appropriate channel.

25

Control device interface control logic 432 (CICL) is a link system control unit that moves data between local channel memory (LCS) and input / output devices.

During an input / output start instruction, the operation control logic activates the CICL by modifying the global transfer state area (GTS) of the shift channel state (SCS). The CICL responds by initiating the initial selection sequence, a work sequence, which is then a termination sequence. In the meantime, the OCL monitors the operation by examining the changes that the CICL makes to the offset channel state.

The OCL will intervene while the channel end and device end states are received from the device. When the end of channel state 40 is received, the CICL establishes a new GTS state in the shift channel state. This prevents further action in the CICL, until OCL processes the state and releases the CICL by changing the GTS to a new value. The CICL recognizes the new GTS condition and continues treatment. The handling of the device end state is similar.

Likewise, the OCL controls the operations of the CICL with regard to errors. If the CICL detects an interface command check or a channel command check, it will establish an error value in the unusual SCS termination area. The OCL will detect this error area in SCS and cause a channel status word (CSW) to be stored.

The 11 interface sequences that can be executed by the CICL 432 are defined in "IBM SYSTEM / 360 and SYS-55 TEM / 3701/0 INTERFACE CHANNEL to CONTROL UNIT ORIGINAL EQUIPEMENT MANUFACTURERA INFORMATION" (form number Ga22-6974).

To execute CICL sequences, the CICL uses local channel memory (LCS), remote interface logic 60 (RIL), and offset channel state (SCS).

LCS contains a data buffer with 32 data locations for each channel. This data is sent to the input / output interface during an output. During an entry, the data buffer is used as intermediate memory 65 for the data received from the input / output interface. The local channel memory (LCS) also contains the device commands sent to the input / output control unit under the control of the CICL. Similarly, the state received

21

629,320

from the input / output device is stored in the LCS by the CICL.

Remote interface logic provides data paths to and from local channel memory (LCS)

for the 16 channel interfaces, the CICL offering command 5 but not having data paths. The input / output interface connectors are fixed to the RIL chassis. During an entry, data (or flags) moving from these interfaces are stored in the RIL and then sent to the LCS under the command of the CICL. On exit, the circulation is reversed.

To control the flow of data between LCS and RIL, the CICL uses information from SCS and RIL. This information is loaded into an entry organization register; CICL processing is carried out from this register; 15

CICL treatment only takes one cycle; however, only one step is performed in traffic. Since it takes many steps to execute any of the 11 sequences, CICL operations take many machine cycles. 20

The CICL and the remote interface logic (RIL) work together like a computer with a link system.

The link system is started when CICL sends a synchronization pulse to the RIL sequence device. This sequence device begins to send pulses for sampling (S), edge (E), command (C) and wiring (B). The pulses direct information from the input / output interface in the RIL.

During the first four cycles of the CICL-RIL link, 30 flags at the entrance are sampled and locked in the RIL. The input flags are collected simultaneously from a pair of up / down channels with channel numbers spaced eight units apart, for example 0-8.1-9, etc.

While the input flags are being collected, if input service or input data is present, a head edge lock will be set in the RIL. The leading or leading edges in RIL are sent to the CICL and indicate to the latter that data is required by an input / output device.

The priority logic in the CICL examines the 40 front edges. If neither channel or both channels in the up / down pair have a leading edge, the CICL will give priority to the channel that has not received service for the longest period of time.

The output of the priority logic is a signal used to select either the higher numbered channel or the lower numbered channel. This selection signal is sent to the up / down selection shift register.

The up / down selection shift register contains 8 stages and only retains the fact that the channel number 50 higher or that number lower was selected by the priority circuits. At each cycle, the stored signal is shifted to the next stage of the shift register. As a selected channel travels through the link system, the up / down selection offset produces gate signals to control the CICL and RIL.

The first command from the up / down selection shift register enters the shift channel state information (SCS) into the CICL entry organization register (CICLIS). Each channel status information is in the SCS so and of the two channels that can receive service, one is in SCS2 and the other in SCS A.

At the same time, status information is loaded into CICLIS, the up / down selection shift register also directs the input flags of the selected channels and the output flag reaction information (from RIL)

in CICLIS for treatment.

Treatment in the CICL takes only one cycle (cycle P).

The processing logic determines:

1) new status information to illustrate which channel step follows for the current operation;

2) the new output flags to be transferred to the remote interface logic (RIL), and

3) the requirements for writing or searching for local channel memory (LCS).

During processing, new channel state information is produced. The information is signaled in SCS during the cycle following cycle P and this is done by a preservation device adjusted from the priority circuits.

Likewise, during processing, if it has been determined that a search is required in the LCS memory, an address is generated and loaded into the local channel memory address register (LCSAR). A storage operation could consist in storing a data state and a search operation could consist in searching for an input / output address, an order or data. -

Input status or data arrives in RIL from the input wiring lines of the input / output interface. This data (status / data) is routed through the input / output wiring buffers until control is taken by the up / down selection shift register and the RIL sequence device.

As the data passes through the RIL, it is locked in the Interface Logic Data Obtaining Register (ILGDR). A byte selector is used to rearrange bytes of data in the ILGDR if necessary before sending them to local channel memory (LCS).

Data or commands from LCS are placed in the 32-bit Interface Logic Data Placement Register (ILPDR). A byte selector at the output of the ILPDR sends a byte to the RIL. For an interface with a width of two bytes, two bytes would be selected and sent to the RIL. The up / down selection shift register and the RIL sequence device provide the trigger commands necessary to move the data through the output buffers (A and B) and output it to the interface output wiring lines enter exit.

Each time the channel number in SCS2 is 3 or E, the RIL sequence device will receive a start pulse. The sequence device will cycle through eight cycles and then receive a new start pulse. Through this process, the RIL sequence device works continuously.

When a channel is in the P cycle, an ADB operand is produced; the operand can be true or in addition. True ADB operands are intended for normal operation. The operands in addition are intended for correction operations. The operand produced is added to the ADB in CICLIS for a new production of ADB. If CICL does not transfer data to an input / output device, the newly calculated ADB is neglected and the ADB in SCS remains unchanged.

At the output ADB indicates the number of byte locations that are empty in the channel buffers (CBS).

When entering, ADB is the number of bytes in the CBS.

Each time a channel enters the process cycle (P), a decision is made as to:

look for the data in the data buffer CB A and transfer it to the output buffers RIL or, store the data from the input / output device (in ILGDR) in the CBS or,

do neither a CBS memorization, nor a CBS search.

If either a store or a search takes place, the available DACL buffer (ADB) must be updated and reported in the offset channel state (SCS).

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22

To update the ADB, the CICL calculates an area of 5 CICL entry organization (CICLIS). This subtraction, by bits called the operand ADB. The bits are numbered from 0 to addition of complement, is called a correction of

4. During an exit operation, the operand is equal to the name- ADB.

number of bytes transferred from the channel buffer An ADB correction takes place when an input /

(CBS) to the RIL output buffers. During an input operation causes the input operation or input state to drop down before input, the operand ADB is equal to the quantity of bytes received as soon as the channel CCW count has reached 0. In one and the other from the input / output device and sent to the case data area, there may be data in the RIL output buffer which

CBS. have not been transferred to the input / output device. Given

The ADB operand can be in true form or in the form that the ADB has been modified (which indicates an erroneous count),

is lying. True operands are intended for operations of which correction of ADB is necessary since ADB is used

normal input and output. The operands in addition are for the production of CSW.

used for correction operations. The ADB operand produced for correction can be-1

During an output, an ADB correction is necessary when- byte (11111), -2 bytes (11110) or -3 bytes that an input / output device descends operation as input or (11101). However, the operands —2 and —3 are only output state before the CCW channel count is 15 when using a two byte interface. In addition,

0. In this case, a negative operand is produced. This will be explained as additional operands are only produced for oper-

more in detail below. The operand ADB is added to the output anations.

this ADB in CICLIS to create a new ADB. The production of the new ADB takes place in an adder

CICLIS receives an ADB of SCS 2 or A at each cycle by 5-bit paired contained on a CL 29 microchip.

via the up / down selection shift register. This operator has no controls and performs a simple

ADB is added to the operand ADB produced by the CICL and binary resi- sum of the 5 bits of the operand ADB and the 5 bits ADB

gnalé à SCS4 ou C. However, during CICL treatment, if from CICLIS.

no data transfer is required, the newly ADB A new channel ADB is calculated during the calculated cycle will not be used and on the contrary a channel processing selection circuit (P). Likewise, during the next cycle choose the SCS 3 or SCSB ADB. 25 (CTS / DIS), the new ADB is returned to the SCS.

The selection is based on the fact that the channel that CICL treats. A selector is used to control the sending of the ADB to the ISP from SCS 2 or SCSA (SCS 10), which has been determined by SCS. As previously explained, the new ADB can speak the up / down selection shift register during the cycle coming to SCS 4 or C. In the case of no wiring transfer (B). If the CICL processed the channel in SCS 2, the ADB data CICL, the ADB of SCS 3 is selected instead of the originating from SCS 3 is directed in SCS 4. If the CICL processed the new ADB of CICL.

channel in SCSA, the ADB coming from SCSB would be directed into the LCS address register (LSCAR) can receive

SCS C. controlled by the operation control logic (OCL), the logic

We will now define the production of the operand plus data access control (DACL), the console and the software.

ADB. This operand is an amount of increase for the Adequate Channel Interface Control Device (CICL). The ADB diter and will be equal to + 1 multiplet (0001) or + 2 35 OCL and the DACL go through LCS at each machine cycle multiplets (00010) during normal operation. One operator and CICL has access to LCS at each machine cycle.

an additional command is produced during an input and an output, if The fact of making an LCS request to memorize an interface of a byte is used and that a byte of input / output address, store a state, search for data must be transferred between the data buffer and the RIL. entry / exit address or search for an entry / exit order is

An operand plus two is produced, at the time of an entry and a 40 called a control access. Command access is output only if a two-byte interface is used. performed while the global transfer state (GTS) is equal to

CICL can also produce a plus one for an interface of two anything except work reports (66-77).

bytes, as in the case of a byte count im- We will now define the production of LCSAR bits for even, when the last byte is transferred from CBS to RIL. command access.

During the process or processing cycle (while 45 bit 10 of LCSAR is chased every time CICL has channel information is in CICLIS), ADB is unavailable to LCS. Bits 1-4 of LCSAR constitute the pecté number. It is determined whether the operation is a channel entry or exit and come from the CICL entry organization register.

and also what is the width of the data transfer. A LCSAR bit 5 is chased because GTS is not equal to

from this, the new ADB value is determined. work during command access. Bit 6 of LCSAR is

If ADB coming from SCS was equal to 00111 and that the opera- 50 set if GTS is equal to 61 (search order).

tion concerns a transfer of a multiple, the ADB will be set to Bit 7 of LSCAR is chased or canceled if:

010,000. This is done as follows: 1) GTS is equal to 01 (CICL searches for an address for

1) Point A = more due to an exit / stop entry / exit operation) or

2) Point B = more because point A is less and point 2) GTS = 32 (CICL stores an address for a device-C is less (this is not a transfer of two bytes) 55 tif who submitted an input request) or

3) Point D will be more because point B is more 3) GTS = 52 (CICL searches for an entry / exit address

4) Point E will be less because point D is more for an initial selection) or

5) Point H will be more because bit 4 of ADB from 4) GTS = 60 (CICL searches for an input / output address at SCS was set (point G) compare to that sent from an input / device exit

6) Point H will be more because point I will be less, by eo or canceling bit 4 of the new ADB. 5) GTS = 61 (CICL searches for an order to send to a

If the ADB was equal to 00110,1e new ADB will be equal to input / output device).

00101. This is done as for point 1-4 above and the Bit 7 is set if GTS = 26,34,44 or 64 (CICL memo-

point H will be less because point G is more. This brings the status of the input / output device). Bit 8 of LCSAR is point I to become more. 65 canceled for all command accesses, because GTS is not

The CICL may have to subtract from the ADB. This is not equal to work.

produced by producing an ADB operand in addition. The operation - bit 9 of LCSAR is set if the operation is an additional write write is then added to the ADB in the register to LCS.

23

629,320

LCSAR bit 10 is set via byte write mark circuit 0 during all control accesses, because GTS is not equal to work.

LCSAR bit 11 is set if GTS is equal to 0,1,32,52 or 60 (see bit 7 for the description of the states). Bit 11 is set via the byte write mark circuits.

LCSAR bits 12—13 are canceled during command hits via byte write mark 2 and byte write mark circuits 3. They are i0 canceled because GTS is not equal at work.

The CICL will be in a data transfer when the global transfer state (GTS) is equal to work (states 66-77). The transfer may be an input, with movement of data input / output to the local channel memory (LCS), or be an output with movement of data from LCSAR to an input / output device. During a data transfer, the CICL performs data access to LCS as opposed to command access. It will be remembered that during command access, the GTS is different from working. 20

We will now define the production of LCSAR bits for data access.

Bit 0 LCSAR is cleared each time CICL has access to LCS.

Bits 1 to 4 constitute the channel number and come from the CICL entry organization register (CICLIS).

Bit 5 is set because GTS equals work (66—77).

LCSAR bits 6 to 8 come from the CICL indicator or pointer. The CICL indicator is produced on the CL 29 microchip by adding the available DACL buffer (ADB) to the DACL indicator.

Bit 9 of LCSAR is set if the operation is a write to LCS.

LCSAR bits 10-13 are set by the byte write mark circuits (0-3). 35

An odd numbered channel request is made during even cycles, CBS available is canceled, the generated address is locked and held for one cycle, and LCSAR is open to input during the odd channels of the CBSI cycle.

All odd channels enter the CICL processing cycle during an even machine cycle. The lower rank bit of the channel number generator determines the odd-even cycles. Refer to the channel number generator for details.

When an odd channel makes a CBS request, the available CBS lock is released. The odd channel cannot enter LCSAR until the next even machine cycle (CICL only has access to CBS for even cycles). During this time, an even channel will be in the process or processing cycle, so that it does not have to use LCSAR. The even numbered channel is blocked by canceling the available CBS lock. As a result, available CBS prevents even channels from opening at the LSCAR input while allowing input opening for an odd channel to LCSAR.

Address generation for an odd channel takes place during cycle P, is locked during the next cycle (odd cycle) and directed into the LCSAR during the next cycle (CBSI cycle).

An even numbered channel request is made during odd cycles; it is not allowed if an odd numbered channel made a request during the last cycle; it will produce an LCSAR address during the P cycle; it will open at the LCSAR entry with the address produced during the next cycle (CTS / DIS) if CBS is available.

Even number channels are in cycle P during odd machine cycles; LCSAR bit generation is performed during this cycle. The address produced is sent to LCSAR during the next cycle.

Since CICL only has access to LCS in even cycles, only one channel can have access to LCS every two cycles. An even channel request will be blocked if an odd channel request is in progress.

The even request is blocked by the available CBS lock. This route is used by all even numbered channels. As explained for the odd channel request, the available CBS lock will be blocked or canceled following an odd channel request and the LCSAR will be opened for entry from delay locks, which would contain the generated LCSAR address for odd channels.

If no odd channel request is in progress, an even channel will open a cycle after the P cycle (CTS / DIS cycle) at the LCSAR input.

6 sheets of drawings

Claims (4)

629,320 2 CLAIMS such that the first (430) and second (432,407) calculate 1. Data processing installation, comprising readers which can identify a channel which is in the process of triate-devices forming an installation memory (2,4) and at least ment. a channel unit (6) for transferring data between 5. Data processing installation as claimed input / output devices and the installation memory (2,4) on 5 cation 4, characterized in that, in said first multi-channel computer, characterized in that the channel unit (6) (430), some ( 734, .735,736) said elements are also included arranged to transfer the channel number of the fourth em- - a channel memory (406) intended to memorize the information to the address means (467) when the first calculation comprising the data to be transferred on the channels, lateür (430) acts to form a rank address superior - a channel state memory (SCS0, SCSI ... SCS15) 10 in these address means (467) and in that, in said second common to all the channels, comprising several groups (710) computer (432,407 ), some (751,754,757) of said locations of a group for each of the channels, cooperate with elements (752,753,756,776) for each group (710) retaining information for a channel also transfer the number of channel of the fourth associated location different, the state memory (SCS0, SCSI ... SCS15) to the address means (467) when the second computer (432, comprising for each group (710) first locations - 15 407) acts to form a top ranking address (BBC) for storing a count intended for in these address means. designate a remaining transfer length which specifies a name. 6. Data processing installation according to the claim for data mulitplets still to be transferred to the cation 5, characterized in that the first computer (430) is associated channel, second locations (DACL) for memo arranged to transfer the indicator from the second location to the riser an indicator intended to define a location in the address means (467) in order to form a zone of inferior memory channel rank ( 106) and third locations (ABD) laughing therein and in that the second computer (432,407) intended to store an availability number specifying them is arranged to transfer a combination of this indicator locations remaining in the channel memory ( 406), coming from the second location and the number of availabilities - a first computer (430) common to all the channels read from the third location to form a zone of in order to control the transfer of the data between the memory of lower rank in the address means (467). channel (406) and the installation memory (2,4), the first computation. 7. Data processing installation according to the reseller (430) comprising elements (734) connected to the measurement 1, characterized in that, for an output operation, state memory (SCS0, SCSI ... SCS15) to give access to in said first computer (430) some (739 ...) of said first, second and third locations for each ca- elements are arranged to control the transfer of the final data, with elements (739) intended to transfer the data 30 from the installation memory (2,4) to the memory of between the channel memory (406 ) and the installation memory (2, channel (406), the elements (740) intended to modify the number of 4) of a first of a first transfer quantity, the pre-availability in the first direction comprising elements to merge calculator (430) comprising elements (740,734—737, decrease this number, and in that in the second calcula 739-2,741,749) intended to modify the number of availability (432,407), some (757) of said elements are arranged in a first sense of the same amount equal to the first amount 35 transfer data from the channel memory (406 ) towards the transfer, input / output devices, the elements (757,780) intended for mo- —A second computer (432,407) common to all of them to calculate the number of availability in the second direction opposite to the channels, intended to control the transfer of data between the first comprising elements to increase this number of channel memory (406) and input / output devices, this availability. cond calculator (432,407) comprising elements (751, 40 8. Data processing installation according to resell-754) connected to the state memory (SCS0, SCSI ... SCS15) cation 1, characterized in that, for an input operation, the to give access to the first, second and third places - second computer (432,407) comprises elements intended for ment for each channel, with elements (407,438,439) controlling the transfer of data from the input / output devices intended to transfer the data between the channel memory to the channel memory (406), the elements (757,780) intended (406) and the input / output devices with a second quantity of 45 to modify the number of availability in the second direction opposite transfer, this second computer (432,407) comprising elements with the first comprising elements for reducing this number ( 757,780) intended to modify the number of availability of availability, and in that the first computer (430) com-in a second direction, opposite to the first, of an amount equal to takes elements (789) intended to transfer data of the second transfer amount. channel memory (406) to the installation memory (2,4), the 2. Installation for processing data according to the claim - so elements (740) intended to modify the number of availability cation 1, characterized in that the channel memory (406) co- in the first direction comprising elements for increasing operates with address means (467) responding to the first number. (430) and to the second (432,407) computers, to give access 9. Data processing installation according to the claim at the locations of this channel memory (406). cation 1, characterized in that it is arranged so that the 3. Data processing installation according to the claim 55 first transfer quantity is different from the second, cation 2, characterized in that each location group 10. Data processing installation according to the resale of the memory of state (SCS0, SCSI ... SCS15) is constituted by cation 1, characterized in that it comprises elements (467) a stage (710) of a shift register with several stages, intended to assign an access to the channel memory (406) for each stage which can act in order to memorize an informative (430) or the second (432,407,404) computer in command function for a different channel among the channels 60 tion of the magnitude of the number availability. and having elements for advancing the stages of the shift register so that the information of comp command for each channel is available for the two computers (430; 432,407) at different times. The present invention relates to a milking installation 4. Data processing installation according to the data claim, comprising apparatuses forming a me-cation 3, characterized in that the stages of the installation storage register and at least one channel unit for transfer -lage comprise a fourth location intended to store data between input / output dipocsitfs and the memory ser a channel number identifying the channel associated with these installation stages on several channels. 3 629,320 In the prior art, channels or channels have been defined architecturally as part of the data processing system serving control units associated with the input / output (I / O) devices of the system. The channels were separate and independent devices with their own set of commands allowing the input / output devices to read and write data while the rest of the system concurrently processes instructions which are not necessarily related to the devices enter exit. Each channel has its own instructions in the system memory which have been retrieved and processed under the command of a supervision program. Channels are generally of three types, namely selector, multiplet multiplexer and block multiplexer are generally associated with high speed devices, while multiplet multiplexer channels are usually associated with low speed devices. Multiple input / output devices are connected to a channel through a control unit. Byte multiplexer channels and block multiplexer channels allow interleaved data transfer from multiple devices connected to the same physical channel interface. Although the channels operate somewhat independently of the instructions executed by the data processing system, the latter maintains a supervision command on the operations of the channels and input / output. Channels are therefore information processors which have a certain independence from the other system processors (for example the instruction unit or I) and consequently increase the simultaneity of information processing by the system. Although the prior art apparatuses have worked satisfactorily, there is a need for an improved channel or channel apparatus which makes the use of modern high speed technologies more efficient. While input / output devices operate at relatively limited speeds which limit the maximum data rate in a channel, frequently due to mechanical limitations, and while electronic circuits operate at much higher speeds, these circuits should a desirable way to be shared by a multiplicity of input / output devices in order to more effectively use their high speed capabilities. In prior art channel structures, for which one channel apparatus has been assigned on a per channel basis, the circuits of one channel have not been readily shared with other channels.