CH621898A5 - Arrangement for receiver-end recovery of clocks of a plurality of digital signals interleaved in a pulse frame by means of positive-negative pulse stuffing - Google Patents

Description

The invention relates to an arrangement for the recovery on the receiving side of clocks of several digital signals interleaved in a pulse frame by means of positive-negative stuffing, each with an associated additional signal containing the stuffing information and optionally an information bit, per data signal consisting of a pulse recovery device, the digital signal, the additional signal and a clock derived from the digital signal is supplied and a digital signal restored after tamping is removed with an associated irregular clock, from a writable elastic memory that can be read out at the same time with another clock frequency, to which the restored digital signal with associated irregular clock as well as a uniform clock are fed and a clock-corrected, restored digital signal is taken from a phase comparator assigned to the elastic memory, which outputs a control signal, and from a clock device, which is controlled by the control signal in frequency generates the uniform clock.

Such an arrangement is known from the book "Transmission Systems for Communications", revised fourth edition, Dec. 1971, Bell Telephone Laboratories, Incorporated, pages 616 to 618. In this arrangement, quartz oscillators serve as clock devices.

An arrangement is also known from the communications technical reports, volume 42, 1972, "PCM-Technik", VDE-Verlag GmbH, Berlin-Charlottenburg, pages 245 to 256, which instead of the oscillator has a digital circuit for generating the uniform clock (readout clock ) used.

The digital circuit provides a clock with a frequency f 1 as long as there is no stuffing. After a tamping process, the clock frequency is increased or decreased. This is done by inserting correction steps, i.e. bit clock periods with a changed duration. This known arrangement has the disadvantage that the complex circuit for generating the readout clock is provided for each digital signal.

Finally, a device for deriving a clock pulse from a pulse having pulse gaps while maintaining the average number of pulses per unit of time is known from DT-PS 2117 344. However, this device is only suitable for a positive plug.

The object of the invention is to implement an arrangement for recovering clocks of a plurality of digital signals interleaved in a pulse frame by means of positive-negative stuffing with little circuit complexity.

Starting from an arrangement of the type described in the introduction, this object is achieved according to the invention in that a clock center is provided which generates a first clock which corresponds in frequency to the clock derived from the digital signal and which generates a second clock in frequency from deviates first clock by a negative amount, which generates a third clock, which differs in frequency from the first clock by a positive amount and which generates a switching clock, such that in one period of the switching clock n periods of the first clock, n-1 periods of the second cycle and n + 1 periods of the third cycle, where n is an integer greater than one, that a digital comparator is also provided for each digital signal, which outputs a first control voltage when a set value of the degree of filling of the elastic memory is exceeded by a first amount and which outputs a second control voltage,

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if this setpoint is undershot by a second amount, and that, finally, a gate circuit is provided per digital signal as the clock device, which, in the absence of a control signal, the first cycle, the second cycle when the first control voltage occurs and the third when the second control voltage occurs Output clock as a uniform clock, such that the switchover takes place at the beginning of a period of the switchover clock.

It is advantageous if n is a power of 2.

The degree of filling of an elastic memory means the distance between the memory cells between reading in and reading out divided by the sum of the available memory cells.

It is advantageous if a phase comparator is provided, which emits a control signal each time the setpoint of the degree of filling of the elastic memory is exceeded or undershot by an amount X 15. It is advantageous if equal amounts ± À X are selected or X = 1/2 E storage cells is selected.

It is also advantageous if the elastic memory has eight memory cells and if the period of the switching cycle 2o is greater than 1 / 6A fmax and less than 1 / 3À fmax, where À fmax is the maximum deviation of the frequency of the original digital signal from the frequency of the digital signal is in the main channel.

Finally, it is advantageous if a phase comparator 2s is provided, which compares the ordinal number of the memory cell into which reading is carried out once per memory cycle with the ordinal number of the memory cell from which it is read, from which the degree of filling of the elastic memory is obtained and which sets a first memory for a lower limit of the degree of filling and a second memory for an upper limit of the degree of filling.

The invention is explained in more detail below on the basis of exemplary embodiments.

1 shows a known arrangement for recovering the clock of a digital signal interleaved in a pulse frame by means of positive-negative stuffing.

FIG. 2 shows processes in the removal of a stuff bit from the digital signal in the arrangement according to FIG. 1.

FIG. 3 shows processes in the insertion of an additional 40 information bits into the digital signal in the arrangement according to FIG. 1.

FIG. 4 shows an arrangement according to the invention for the reception-side recovery of the clock of a digital signal interleaved with a pulse frame by means of positive-negative stuffing.

FIG. 5 shows a phase diagram of the clocks in the arrangement according to FIG. 4.

FIG. 6 shows processes when compensating for a positive tamping process in the arrangement according to FIG. 4. 50

FIG. 7 shows a known exemplary embodiment of an elastic memory for the arrangement according to FIG. 4.

FIG. 8 shows an exemplary embodiment of a phase comparator according to the invention for the arrangement according to FIGS. 4 and

FIG. 9 shows an exemplary embodiment 55 of a gate circuit according to the invention for the arrangement according to FIG. 4.

1 shows a known arrangement for the reception-side recovery of a digital signal and its clock. It contains a pulse recovery device 1 with an input 2 for a digital signal Dil of a stuffing channel with a 60 input 3 for a digital signal Dl of a main channel and with a clock signal Tl belonging to the digital signal Dl, an output 5 for a restored digital signal D12 and an output 6 for a Restored digital signal D12 associated uneven clock Tl 2, an elastic memory 65 see 7 with outputs 10 and 11 for connecting a phase comparator, with an output 12 for a clock-corrected restored digital signal D2, with a

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Input 13 for a uniform clock T2 associated with digital signal D2, with a phase comparator 14 with inputs 15 and 16 and with an output 17, and a clock device 18 in the form of a clock oscillator with a control input 19 and an output 20.

The pulse recovery device 1 is supplied with the digital signal Dl of the main channel, the associated clock signal Tl and the digital signal Dil of the stuffing channel. The pulse recovery device 1 evaluates the digital signal Dil. In the case of stuffing information “positive stuffing”, one bit is removed from the digital signal Dl. With the stuffing information “negative stuffing”, the information bit transmitted in the stuffing channel is inserted into the digital signal Dl. The pulse recovery device 1 outputs the restored digital signal Dl2 with the associated clock signal T12 to the elastic memory 7.

2 shows the processes when a stuffing bit S is removed from the digital signal Dl. In this case, the associated clock pulse of the clock Tl is suppressed, so that the stuffing bit S is not read into the elastic memory 7.

3 shows the processes involved in inserting an information bit J into the digital signal Dl. In this case, an additional clock pulse TJ is inserted into the clock signal Tl.

The pulse restoration device 1 outputs the restored digital signal D12 to the elastic memory 7 with the uneven clock T12. From this, the information is read out again with the uniform clock T2 of the clock oscillator 18. The phase comparator 14 outputs a control voltage U to the clock oscillator 18, which is proportional to the degree of filling of the elastic memory 7.

The frequency f2 of the clock oscillator 18 is regulated in such a way that the degree of filling of the elastic memory 7 is kept at its desired value Vi. When a bit is inserted, for example, the degree of filling of the elastic memory 7 increases by 1 bit above its setpoint. As a result, the frequency f2 is increased until the degree of filling of the elastic store 7 has dropped back to its target value.

The digital signal D2 read out from the elastic memory 7 is thus the restored original data signal, which was bundled with other digital signals in the transmitter of the digital multiplex device of the remote station to form a digital multiplex signal.

The clock T2 has averaged the same frequency as the clock of the original digital signal over a longer period of time. However, it is jittery due to the equalization processes. The maximum value of the jitter is 1 bit.

FIG. 4 shows an arrangement according to the invention, which differs from that according to FIG. 1 by another phase comparator 14 ′, another clock device 18 ′ and a clock center 26. The phase comparator 14 'has an output 17' for a control signal S1 and an output 17 "for a control signal S2. The clock device 18 'is a gate circuit with an input 19' for the first control signal S1, with an input 21 'for a second Control signal S2, with an input 22 for a clock T20, with an input 23 for a clock T21, with an input 24 for a clock T22, with an input 25 for a switchover clock TU and with an output 20 'for the clock T2 Clock center 26 outputs the clock T20 at output 27, clock T21 at output 28, clock T22 at output 29 and switching clock TU at output 30 for all gate circuits 18 'of the digital demultiplexing device. The phase comparator 14' can operate analogously and have threshold value circuits in front of its outputs 17 'and 17 ", at the output of which a control signal is issued when the degree of filling of the elastic memory has exceeded or fallen below a predetermined value. The phase comparator 14 'can also work digitally.

The frequencies and phases of the clock center

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Generated clocks are selected so that in a period T of the clock TU there are n periods of the clock T20, n-1 periods of the clock T21 and n + 1 periods of the clock T22, where n is an integer. This is shown in FIG. 5 . The frequency f20 of the clock T20 is chosen equal to the frequency f 1 of the clock Tl

6 shows the processes involved in compensating for a positive tamping process. If there is no stuffing, the gate circuit 18 'switches on the clock T20 as the read clock T2. The information is read in and read out into the elastic memory 7 at the frequency fl, so that its degree of filling corresponds exactly to the target value. After a positive tamping process, the degree of filling drops 1 bit below its target value. The phase comparator 14 'gives a digital control signal S1 to Gate circuit 18 '. At the next possible changeover time, the gate circuit 18 'switches on the clock T21 for a period of the changeover clock TU. During this period, n bits are read into the elastic memory 7 and n-1 bits are read from the elastic memory 7. The degree of filling has thus risen again exactly to the target value. The signal S1 assumes the value “0” as soon as the degree of filling differs from its setpoint by less than A X. After a negative stuffing process, the control signal S2 causes the switching on of the clock T22 for a period T of the switching clock TU.

The need for memory cells in elastic memories is a minimum if an equalization process is initiated after each tamping process, that is to say that the phase comparator 14 'must be designed in such a way that the amount by which the setpoint value of the filling level can be exceeded or fallen short of Vz Bit

The mean frequency of the stuffing is equal to the difference À f between the clock frequencies of the original digital signal and the main channel. If, for example, the clock frequency of the original digital signal is 1 Hz greater than the clock frequency of the main channel, then on average one stop must be made in 1 s. Since a period T of the switching cycle TU is required to compensate for a tamping process, T = ^ 1 / À f. In transmission networks, several transmission sections are often connected in series with digital multiplex devices. A single digital signal can therefore go through multiple bundling and resolving operations. The intervals between two consecutive tamping operations can vary considerably. They can be significantly above or below the average distance 1 / A f. In order for the clock recovery to work properly even under these conditions, the period T of the changeover clock TU must be selected to be less than 1 / f f and the elastic memory 7 must have a sufficient reserve of memory spaces.

An advantageous dimensioning is T1 / 6A fmax to 1 / 3A fmax in connection with an elastic memory 7, which has eight memory cells

4 shows a practical exemplary embodiment in connection with FIGS. 7, 8 and 9. For a digital multiplex device that bundles 64 kbit / s signals into one 2048 kbit / s signal. The bit rate of the main channel has a nominal value of 64 kbit / s, which can deviate by ± 0.5 • 10 "4. The bit rates of the 64 kbit / s signals can deviate by ± 1 • IO" 4 from their nominal value. The maximum difference in clock frequencies is therefore A f = 9.6 Hz. This means that in the worst case, a stuffing process is required approximately every 100 ms.

The frequency of the clock Tl is f 1 = 64 kHz. The value 211 = 2048 was chosen for n, which results in the frequency and period of the changeover clock TU at fU = 31.25 Hz, T = 32 ms and TA f = 0.31. When compensating for a tamping process, the frequency of the reading cycle increases or decreases by about 5-10-4.

The elastic memory 7 is designed with eight memory cells. This ensures that further tamping processes can be absorbed during the 32 msec compensation of a tamping process.

Fig. 7 shows a known elastic memory. It is implemented with CMOS modules, namely with the module CD 14520, which contains two four-bit counters 31 and 32, the addressable 8-bit memory 33 (CD 4099) and the data selector 34 (MC 14512).

The uneven clock T12 reaches the clock input CK of the counter 31 via the terminal 9. The outputs QA, QB, QC, the first three stages of the counter 31 address the addressable memory 33 via its address inputs A0, AI and A2. The bits of the digital signal D12 are therefore written cyclically into the memory cells Q0 to Q7 via the terminal 8 and the data input D of the addressable memory 33. The readout clock T2 at the input 13 controls the counter 32, whose outputs QA, QB and QC address the data selector 34. With each clock step of clock T2, a bit is read out of addressable memory 33 via the output of the data selector. In the normal state, the elastic store 7 is half full. A bit that is read into a memory cell is read out again after four clock steps. For example, if the addressable memory 33 writes a bit into the memory cell Q0, the data selector 34 simultaneously reads out a bit from the memory cell Q4. The elastic memory 7 is connected to the phase comparator 14 'by the outputs 35 to 40 and the input 41.

8 shows an exemplary embodiment of the phase comparator 14 ′ according to the invention, in which the addresses of the reading in and reading out are compared with one another once in each memory cycle and the result of the comparison is recorded in two memories.

The phase comparator 14 'consists of a gate circuit with gates 42, 43 and 44, a first memory with gates 48 and 49, a second memory with gates 46 and 47 and an address decoder 45, which is implemented in the module CD4028.

A comparison is carried out when the counter 32 of the elastic memory 7 has the position QA = 0, QB = 0 and QC = 1, that is to say when the memory cell Q4 of the addressable memory 33 is read out. With this position of the counter 32, the output of the gate 43 has the value “one”. The count is maintained for a period of the 64 kHz clock. In the middle of this period, a narrow clock pulse of the clock T-gate opens the gate 44 so that the input D of the address decoder 45 has the value "zero". The clock T-gate has a clock frequency of 64 kHz and a pulse width of 1 p.s.

The address decoder 45 determines the position of the counter 31 at the time of comparison. As long as the input D of the address decoder 45 has the value “zero”, one of the outputs Q0 to Q7 assumes the value “one”.

If the elastic memory 7 is half full, the output Q0 of the address decoder 45 assumes the value “one” at the time of comparison. The two memories, which consist of gates 48 and 49 or 46 and 47, are set to the value Sl = 0 and S2 = 0.

If the degree of filling deviates by more than Vi bit from its nominal value, one of the outputs Q5, Q6 or Q7 assumes the value "one" and sets the first memory with the gates 48 and 49 to the value Sl = 1.

If the degree of filling deviates upwards by more than Vi bits, one of the outputs Q1, Q2, Q3 assumes the value "one" and sets the second memory with the gates 46 and 47 to the value S2 = 1.

If the output Q4 of the addressable memory 45 assumes the value “one”, the elastic memory 7 is in its overflow position. This condition can occur when the device is switched on or in the event of faults. In this case the counter 31 is reset to the value “zero” via its R input.

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set.

9 shows an exemplary embodiment of the gate circuit 18 'according to the invention. This consists of two JK flip-flops 54 and 55, which are implemented using CD 4027 CMOS modules, a gate connection, gates 56, 57, 58 and 59 and inverters 60 to 64. The latter can be omitted if the clocks TU, T20, T21 and T22 are available inverted and - if the clock T2 can be used inverted.

The signals S1 and S2 are fed to the flip-flops 54 and 55 together with the inverted signals. The flip-flops 54 and 55 can only change their state with the falling

Change the edge of the switchover clock TU. If the signals S1 and S2 both have the value 0, then both flip-flops also have the value Q = 0. In this state, the gates 57 and 58 are blocked and the gate 56 is opened, so that the clock T20 s is switched through.

If the signal S1 assumes the value "one", the flip-flop 54 is switched to the value Q = 1 on the next falling edge. The gate 56 is thus blocked and the gate 57 is opened so that the clock T21 is switched through. If the signal S2 assumes the value “one”, the processes proceed accordingly.

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3 sheets of drawings

Claims (6)

621898 PATENT CLAIMS 1. Arrangement for the recovery on the receiving side of clocks of several digital signals interleaved in a pulse frame by means of positive-negative stuffing, each with an associated additional signal containing the stuffing information and optionally a 5 information bit, per data signal consisting of a pulse recovery device (1) which transmits the digital signal (Dil ), the additional signal (Dl) and a clock derived from the digital signal and a digital signal (D12) restored after plugging with an associated irregular clock are removed from an writable elastic memory (7) which can also be read at a different clock frequency , from which the restored digital signal with associated non-uniform clock and a uniform clock are fed and a 15 clock-corrected restored digital signal is taken from a phase comparator assigned to the elastic memory, which emits a control signal, and from a clock device (18), which generates the uniform clock controlled by the frequency of the control signal, characterized in that a clock center (26) is provided which generates a first clock (T20), which in frequency corresponds to each digital signal (Dl) derived clock (Tl), which generates a second clock (T21), the frequency of the first Clock (T20) deviates by a negative amount, which generates a third clock (T22), which deviates in frequency from the first clock (T20) by a positive amount and which generates a switching clock (TU), such that in a period (T) of the switching cycle (TU) n periods of the first cycle (T20), n -1 periods of the second cycle (T21) and n +1 periods of the third cycle (T22) occur, where n is an integer Greater than one is that a phase comparator (14 ') is also provided for each digital signal (Dl), which emits a first control voltage (S1) when a set value of the degree of filling of the elastic memory (7) is exceeded by a first amount, and 35 which emits a second control voltage (S2) when this setpoint value falls below by a second amount, and that, finally, a gate circuit is provided for each digital signal (Dl) as the clock device (18 '), which in the absence of a control signal has the first clock (T20) , when the first control voltage occurs ng (Sl) outputs the second cycle (T21) and, when the second control voltage (S2) occurs, the third cycle (T22) as a uniform cycle (T2), such that the changeover occurs at the beginning of a period (T) of the changeover cycle (TU) he follows. 45 2. Arrangement according to claim 1, characterized in. that n is a power of 2. 3. Arrangement according to claim 1, characterized in that the first and second amounts, which relate to the deviations from the target value of the degree of filling of the elastic store 50, are chosen to be of the same size. 4. Arrangement according to claim 3, characterized in that the equal amounts of 1/2 2 memory cells are selected. 5. Arrangement according to claim 1, characterized in 55 that the elastic memory (7) has eight memory cells and that the period (T) of the switching clock (TU) is greater than 1 / 6À fmax and less than 1 / 3À fmax, where À fmax is the maximum deviation of the frequency of the original digital signal from the frequency of the digital signal in the main channel. eo 6. Arrangement according to claim 1, characterized in that a phase comparator (14 ') is provided which, once per storage cycle, compares the ordinal number of the memory cell into which it is read with the ordinal number of the memory cell from which it is read, which compares the degree of filling of the elastic memory (65) from this comparison. 7) wins and which sets a first memory (48,49) at a lower limit of the degree of filling and a second memory (46,47) at an upper limit of the degree of filling.