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CH554073A - Verfahren zur herstellung einer halbleiteranordnung, gemaess dem verfahren hergestellte halbleiteranordnung und anwendung des verfahrens. - Google Patents

Verfahren zur herstellung einer halbleiteranordnung, gemaess dem verfahren hergestellte halbleiteranordnung und anwendung des verfahrens.

Info

Publication number
CH554073A
CH554073A CH1680772A CH1680772A CH554073A CH 554073 A CH554073 A CH 554073A CH 1680772 A CH1680772 A CH 1680772A CH 1680772 A CH1680772 A CH 1680772A CH 554073 A CH554073 A CH 554073A
Authority
CH
Switzerland
Prior art keywords
semi
conductor arrangement
producing
application
produced according
Prior art date
Application number
CH1680772A
Other languages
English (en)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of CH554073A publication Critical patent/CH554073A/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
CH1680772A 1971-11-20 1972-11-17 Verfahren zur herstellung einer halbleiteranordnung, gemaess dem verfahren hergestellte halbleiteranordnung und anwendung des verfahrens. CH554073A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7116013.A NL161305C (nl) 1971-11-20 1971-11-20 Werkwijze voor het vervaardigen van een halfgeleiderin- richting.

Publications (1)

Publication Number Publication Date
CH554073A true CH554073A (de) 1974-09-13

Family

ID=19814524

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1680772A CH554073A (de) 1971-11-20 1972-11-17 Verfahren zur herstellung einer halbleiteranordnung, gemaess dem verfahren hergestellte halbleiteranordnung und anwendung des verfahrens.

Country Status (11)

Country Link
US (1) US3849216A (de)
JP (1) JPS5122348B2 (de)
AU (1) AU474400B2 (de)
CA (1) CA970076A (de)
CH (1) CH554073A (de)
DE (1) DE2253702C3 (de)
ES (1) ES408758A1 (de)
FR (1) FR2160534B1 (de)
GB (1) GB1408180A (de)
IT (1) IT982456B (de)
NL (1) NL161305C (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911079A (de) * 1972-05-26 1974-01-31
JPS5550395B2 (de) * 1972-07-08 1980-12-17
JPS5087784A (de) * 1973-12-08 1975-07-15
US3931674A (en) * 1974-02-08 1976-01-13 Fairchild Camera And Instrument Corporation Self aligned CCD element including two levels of electrodes and method of manufacture therefor
US3979765A (en) * 1974-03-07 1976-09-07 Signetics Corporation Silicon gate MOS device and method
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Ｍｏｓトランジスタおよびその製造方法
JPS5222481A (en) * 1975-08-14 1977-02-19 Oki Electric Ind Co Ltd Method of manufacturing semiconductor device
JPS52124635A (en) * 1976-04-12 1977-10-19 Kishirou Igarashi Lift for carrying
JPS5342567A (en) * 1976-09-30 1978-04-18 Oki Electric Ind Co Ltd Semiconductor device and its production
US4313768A (en) * 1978-04-06 1982-02-02 Harris Corporation Method of fabricating improved radiation hardened self-aligned CMOS having Si doped Al field gate
US4402002A (en) * 1978-04-06 1983-08-30 Harris Corporation Radiation hardened-self aligned CMOS and method of fabrication
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
JPS5553462A (en) * 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
US5191396B1 (en) * 1978-10-13 1995-12-26 Int Rectifier Corp High power mosfet with low on-resistance and high breakdown voltage
JPS5548972A (en) * 1979-10-08 1980-04-08 Hitachi Ltd Insulation gate type electric field effective transistor
US4476479A (en) * 1980-03-31 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device with operating voltage coupling region
AT387474B (de) * 1980-12-23 1989-01-25 Philips Nv Verfahren zur herstellung einer halbleitervorrichtung
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4486943A (en) * 1981-12-16 1984-12-11 Inmos Corporation Zero drain overlap and self aligned contact method for MOS devices
CA1197926A (en) * 1981-12-16 1985-12-10 William D. Ryden Zero drain overlap and self-aligned contacts and contact methods for mod devices
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4826781A (en) * 1986-03-04 1989-05-02 Seiko Epson Corporation Semiconductor device and method of preparation
US4748103A (en) * 1986-03-21 1988-05-31 Advanced Power Technology Mask-surrogate semiconductor process employing dopant protective region
IT1250233B (it) * 1991-11-29 1995-04-03 St Microelectronics Srl Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.
EP0549055A3 (en) * 1991-12-23 1996-10-23 Koninkl Philips Electronics Nv Method of manufacturing a semiconductor device provided with a field effect transistor, and such a semiconductor device
US6344663B1 (en) * 1992-06-05 2002-02-05 Cree, Inc. Silicon carbide CMOS devices
JP3431647B2 (ja) 1992-10-30 2003-07-28 株式会社半導体エネルギー研究所 半導体装置とその作製方法およびメモリ装置の作製方法およびレーザードーピング処理方法
US5869371A (en) * 1995-06-07 1999-02-09 Stmicroelectronics, Inc. Structure and process for reducing the on-resistance of mos-gated power devices
US6437416B1 (en) * 1996-04-12 2002-08-20 Cree Microwave, Inc. Semiconductor structure having a planar junction termination with high breakdown voltage and low parasitic capacitance
JPH09312391A (ja) * 1996-05-22 1997-12-02 Toshiba Corp 半導体装置およびその製造方法
US20080099796A1 (en) * 2006-11-01 2008-05-01 Vora Madhukar B Device with patterned semiconductor electrode structure and method of manufacture

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1535286A (fr) * 1966-09-26 1968-08-02 Gen Micro Electronics Transistor semi-conducteur à oxyde métallique à effet de champ et son procédé de fabrication
US3544399A (en) * 1966-10-26 1970-12-01 Hughes Aircraft Co Insulated gate field-effect transistor (igfet) with semiconductor gate electrode
US3475234A (en) * 1967-03-27 1969-10-28 Bell Telephone Labor Inc Method for making mis structures
NL152707B (nl) * 1967-06-08 1977-03-15 Philips Nv Halfgeleiderinrichting bevattende een veldeffecttransistor van het type met geisoleerde poortelektrode en werkwijze ter vervaardiging daarvan.
US3616380A (en) * 1968-11-22 1971-10-26 Bell Telephone Labor Inc Barrier layer devices and methods for their manufacture
US3576478A (en) * 1969-07-22 1971-04-27 Philco Ford Corp Igfet comprising n-type silicon substrate, silicon oxide gate insulator and p-type polycrystalline silicon gate electrode
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
US3673471A (en) * 1970-10-08 1972-06-27 Fairchild Camera Instr Co Doped semiconductor electrodes for mos type devices
US3699646A (en) * 1970-12-28 1972-10-24 Intel Corp Integrated circuit structure and method for making integrated circuit structure

Also Published As

Publication number Publication date
JPS5122348B2 (de) 1976-07-09
NL161305C (nl) 1980-01-15
GB1408180A (en) 1975-10-01
FR2160534A1 (de) 1973-06-29
DE2253702A1 (de) 1973-05-24
AU474400B2 (en) 1976-07-22
NL161305B (nl) 1979-08-15
AU4887672A (en) 1974-05-16
ES408758A1 (es) 1976-04-16
DE2253702B2 (de) 1979-07-12
FR2160534B1 (de) 1976-01-30
NL7116013A (de) 1973-05-22
CA970076A (en) 1975-06-24
IT982456B (it) 1974-10-21
US3849216A (en) 1974-11-19
JPS4863680A (de) 1973-09-04
DE2253702C3 (de) 1980-03-06

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Legal Events

Date Code Title Description
PL Patent ceased