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CH512144A - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung

Info

Publication number
CH512144A
CH512144A CH997670A CH997670A CH512144A CH 512144 A CH512144 A CH 512144A CH 997670 A CH997670 A CH 997670A CH 997670 A CH997670 A CH 997670A CH 512144 A CH512144 A CH 512144A
Authority
CH
Switzerland
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
CH997670A
Other languages
English (en)
Inventor
Antonius Van Dijk Hen Josephus
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of CH512144A publication Critical patent/CH512144A/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
  • Photovoltaic Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CH997670A 1969-07-04 1970-07-01 Verfahren zur Herstellung einer Halbleiteranordnung CH512144A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6910274A NL6910274A (de) 1969-07-04 1969-07-04

Publications (1)

Publication Number Publication Date
CH512144A true CH512144A (de) 1971-08-31

Family

ID=19807388

Family Applications (1)

Application Number Title Priority Date Filing Date
CH997670A CH512144A (de) 1969-07-04 1970-07-01 Verfahren zur Herstellung einer Halbleiteranordnung

Country Status (11)

Country Link
US (1) US3640807A (de)
JP (1) JPS501985B1 (de)
AT (1) AT322633B (de)
BE (1) BE752897A (de)
CH (1) CH512144A (de)
DE (1) DE2031333C3 (de)
ES (1) ES381370A1 (de)
FR (1) FR2050507B1 (de)
GB (1) GB1316830A (de)
NL (1) NL6910274A (de)
SE (1) SE368114B (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902979A (en) * 1974-06-24 1975-09-02 Westinghouse Electric Corp Insulator substrate with a thin mono-crystalline semiconductive layer and method of fabrication
US3962052A (en) * 1975-04-14 1976-06-08 International Business Machines Corporation Process for forming apertures in silicon bodies
US4033787A (en) * 1975-10-06 1977-07-05 Honeywell Inc. Fabrication of semiconductor devices utilizing ion implantation
US4054497A (en) * 1975-10-06 1977-10-18 Honeywell Inc. Method for electrolytically etching semiconductor material
JPS6047725B2 (ja) * 1977-06-14 1985-10-23 ソニー株式会社 フエライトの加工法
US4141621A (en) * 1977-08-05 1979-02-27 Honeywell Inc. Three layer waveguide for thin film lens fabrication
US4257061A (en) * 1977-10-17 1981-03-17 John Fluke Mfg. Co., Inc. Thermally isolated monolithic semiconductor die
NO843614L (no) * 1983-09-13 1986-06-23 Marconi Co Ltd Infra-roed detektor
US4554059A (en) * 1983-11-04 1985-11-19 Harris Corporation Electrochemical dielectric isolation technique
JPS6415913A (en) * 1987-07-09 1989-01-19 Mitsubishi Monsanto Chem Epitaxial growth method of substrate for high-brightness led
EP0309782B1 (de) * 1987-09-30 1994-06-01 Siemens Aktiengesellschaft Verfahren zum Ätzen von (100) Silizium
US4995953A (en) * 1989-10-30 1991-02-26 Motorola, Inc. Method of forming a semiconductor membrane using an electrochemical etch-stop
JP3151816B2 (ja) * 1990-08-06 2001-04-03 日産自動車株式会社 エッチング方法
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US9465049B2 (en) 2012-04-13 2016-10-11 James B. Colvin Apparatus and method for electronic sample preparation
CN111895679B (zh) * 2020-09-10 2022-04-01 江西北冰洋实业有限公司 一种半导体制冷片安装机构

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153947B (nl) * 1967-02-25 1977-07-15 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen, waarbij een selectief elektrolytisch etsproces wordt toegepast en halfgeleiderinrichting verkregen met toepassing van de werkwijze.
NL6706735A (de) * 1967-05-13 1968-11-14

Also Published As

Publication number Publication date
ES381370A1 (es) 1972-12-01
SE368114B (de) 1974-06-17
FR2050507A1 (de) 1971-04-02
JPS501985B1 (de) 1975-01-22
FR2050507B1 (de) 1974-06-14
AT322633B (de) 1975-05-26
DE2031333A1 (de) 1971-01-21
DE2031333C3 (de) 1978-07-13
DE2031333B2 (de) 1977-11-17
US3640807A (en) 1972-02-08
NL6910274A (de) 1971-01-06
BE752897A (fr) 1971-01-04
GB1316830A (en) 1973-05-16

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Legal Events

Date Code Title Description
PL Patent ceased