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CH475652A - Procédé de fabrication d'un dispositif électrique - Google Patents

Procédé de fabrication d'un dispositif électrique

Info

Publication number
CH475652A
CH475652A CH1756865A CH1756865A CH475652A CH 475652 A CH475652 A CH 475652A CH 1756865 A CH1756865 A CH 1756865A CH 1756865 A CH1756865 A CH 1756865A CH 475652 A CH475652 A CH 475652A
Authority
CH
Switzerland
Prior art keywords
manufacturing process
electrical device
electrical
manufacturing
Prior art date
Application number
CH1756865A
Other languages
English (en)
Inventor
Clair Kilby Jack St
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CH475652A publication Critical patent/CH475652A/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Manufacture Of Motors, Generators (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CH1756865A 1964-12-21 1965-12-21 Procédé de fabrication d'un dispositif électrique CH475652A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42003164A 1964-12-21 1964-12-21

Publications (1)

Publication Number Publication Date
CH475652A true CH475652A (fr) 1969-07-15

Family

ID=23664787

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1756865A CH475652A (fr) 1964-12-21 1965-12-21 Procédé de fabrication d'un dispositif électrique

Country Status (10)

Country Link
JP (1) JPS5011235B1 (fr)
BE (1) BE674126A (fr)
CH (1) CH475652A (fr)
DE (1) DE1514910A1 (fr)
DK (1) DK118474B (fr)
ES (1) ES320796A1 (fr)
FR (1) FR1460406A (fr)
GB (1) GB1135059A (fr)
NL (1) NL6516643A (fr)
SE (2) SE315338B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
JPS54100349U (fr) * 1977-12-27 1979-07-14
US4703436A (en) * 1984-02-01 1987-10-27 Inova Microelectronics Corporation Wafer level integration technique

Also Published As

Publication number Publication date
FR1460406A (fr) 1966-11-25
BE674126A (fr) 1966-04-15
JPS5011235B1 (fr) 1975-04-28
DK118474B (da) 1970-08-24
GB1135059A (en) 1968-11-27
DE1514910A1 (de) 1970-11-26
ES320796A1 (es) 1966-05-16
SE346420B (fr) 1972-07-03
SE315338B (fr) 1969-09-29
NL6516643A (fr) 1966-06-22

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Legal Events

Date Code Title Description
PL Patent ceased