CH329435A - Standard digital electronic adder device - Google Patents

Description

  

  Serial digital electronic adder device The present invention relates to an electronic adder device intended to operate on numbers expressed in binary coded decimal systems.



  It is well known in the art that computers can be easily constructed to operate on numbers expressed in the binary system. However, it is very desirable to perform operations on numbers expressed in conventional decimal systems; this is why the binary-coded decimal systems which make it possible to benefit from both advantages are now used in preference to others in computers. In such systems, a decimal digit may be represented, for example, by a group of four binary digits. The value of the decimal digit is determined by noting the presence or absence of binary units in each of the four digit positions of a group.



  It has been shown previously how a circuit capable of adding pairs of binary-coded decimal numbers can be established using bistable elements combined with logical networks defined by equations which use the algebra notation of Boole.

   The circuit forming the subject of the present invention constitutes an improvement over the known circuits having the aim of adding in series decimal numbers coded in binary, the improvement residing in the substantial reduction of the equipment necessary for the realization of this function. In addition, the circuit of the present invention uses a system for solving logic networks according to simpler and more understandable devices for the personnel who maintain the equipment.

    This advantage is considerable, since the problem of checking the circuits and their operation is a problem of primary importance for complex computer systems of this type.



  Briefly, the present invention makes it possible to edit a pair of binary-coded decimals through the use of three bistable circuits which efficiently accumulate the necessary information during the four pulse periods constituting a cycle of. surgery. The bistable circuits are introduced successively, so as to function like the stages of a conventional binary counter during the first three periods of the cycle. The mode of operation allows, however, each bistable circuit to represent a progressively increasing order stage of the binary counter at each of the three successive periods of pulses.

   During the fourth period of the cycle, the circuits enable the count of the accumulated binary number to be transformed into a sum-number represented in the binary-coded decimal system used for the digits entered.



  Thus, according to the invention, there is provided a serial digital electronic adder device intended to add pairs of binary coded numbers, each coded integer taken from said numbers being expressed in the form of a sequence of four binary digits, a weighted value predetermined number being assigned to each digit according to its position in the sequence, the device comprising a source of synchronization signals continuously producing a recurring cycle of four synchronization signals, said device being characterized by a first, a second and a third bistable members arranged so as to constitute a binary digital register,

   known per se, and by a logic network intended to receive said synchronization signals and provided with input lines designed to simultaneously receive a sequence of four binary signals indicating corresponding integers taken from the coded numbers, each binary signal being synchronized with a signal for synchronizing said cycle, said network comprising a first, a second, a third and a fourth group of logic circuits, the first group of circuits responding to the first three binary signals pon dered from the corresponding integers, so as to produce output signals at the end of each of the first three periods of the synchronization signals, the output signals causing recording, by the digital binary register, in true binary form,

   of the sum of the first three weighted binary digits, the second group of logic circuits responding to an output signal from the bistable device which stores the lowest order true binary digit during the period of the third synchronization signal of so as to produce on an output line emanating from the logic network the first weighted binary output digit of the sum,

    the third group of logic circuits responding to output signals which emanate from bistable members which indicate the partial sum stored therein during the period of the fourth synchronization signal and to input signals indicating the fourth weighted binary digits,

   so as to produce the second weighted binary digit of the sum output on said output line and the fourth group of logic circuits responsive to signals indicating the partial sum stored in the binary digital register during the period of the fourth synchronization signal and to input signals indicating the weighted fourth binary digits, so as to produce output signals causing the recording by the second and third bi-stable members of the fourth and third weighted binary digits, respectively ,

   of the sum in question and causing the recording by the first bistable member of any carry resulting from the addition of the corresponding integers and responding to output signals emanating from the register during the first and second periods of the cycle subsequent synchronization signals, so as to produce the third and fourth weighted binary digits of the sum on the output line.



  More particularly, the summation circuit of the present invention consists of bistable devices, such as flip-flop circuits, and an associated control network. The two groups of signals representing the numbers to be added are introduced in series into the control network which has a cyclic action commanded by synchronizing pulses coming from another source. The group of signals at the output of the adder represents the number corresponding to the sum of the two numbers entered and is expressed in the same code used for the numbers entered.



  The flip-flop control network works according to a set of logical equations. Each of these equations defines when and how a flip-flop should change state. The output signals of the flip-flops as well as the shapes of signals at the input correspond to the terms of the equations which are combined by logical addition or multiplication operations. These operations are carried out physically by networks comprising sets of diodes and resistors which connect the lines carrying the potentials representing the terms of the equations. Synchronizing pulses are used to actually synchronize and advance the summing circuit for the purpose of making the process run.

   When, due to the activation of a synchronization pulse, the network terms are able to satisfy a control signal at a flip-flop, the logical multiplication of this control signal by the synchronization pulse Next flips the flip-flop, unless it is already in the signaled state, in which case it remains in the same state. The cyclic action of the summing circuit corresponds to the reception of four successive binary digits which define a decimal group. An auxiliary set of flip-flops is arranged so as to successively count the clock pulses and to provide potentials representative of the counting of four cycles.

      Thus, we can say that the electrical state of the logic networks and, consequently, of the flip-flops themselves, changes according to the voltage terms representing the digits at the input, the state of the flip-flops according to the command of the previous synchronizing pulse, and the stage of the cycle through which the adder progresses.



  The drawing represents, by way of example, an embodiment of the object of the invention.



  Fig. 1 is a block diagram generally illustrating the embodiment of the adder device.



  Fig. 2 represents a block diagram of the pulse counter accompanied by the logic equations which define the control signals of each of the flip-flop stages.



  Fig. 3 shows the detailed diagram of a typical flip-flop circuit, for example the flip-flop <I> FI, </I> in the pulse counter. Fig. 4 is a diagram showing the forms of signals referred to in the explanation of the operation of the flip-flop <I> FI. </I>



  Fig. 5 is a circuit diagram of the counting logic network for the pulse counter. Fig. 6 is a block diagram of the addition flip-flops showing the state of the different flip-flops during the first pulse period.



  Fig. 7 is a block diagram of the addition flip-flops showing the state of the different flip-flops during the second pulse period.



  Fig. 8 is a block diagram of the addition flip-flops showing the state of the different flip-flops during the third pulse period.



  Fig. 9 is a block diagram of the addition flip-flops showing the state of the different flip-flops during the fourth pulse period.



  Fig. 10 is a circuit diagram of logic networks generating complex propositions used a large number of times in addition circuits.



  Fig. 11 is a diagram of the gate input logic networks for the flip-flop <B> IF. </B> The fi-. 12 is a diagram of the gate input logic networks for the S2 flip-flop. Fig. 13 is a diagram of the gate input logic networks for the S3 flip-flop.



  Fig. 14 is a diagram of the logic output networks, generators of the voltage forms representative of the sum. <I> Description </I> general Referring first to fig. 1, a block diagram shows the whole of the positive adder device. Adder 10 consists of flip-flops <I> IF, S2 </I> and S3 as well as an arithmetic logic output network 11. The voltage forms on the inputs <I> His </I> and <B> <I> IF, </I> </B> represent coded decimal numbers of the times to be added in adder 10. The signal appearing at the output So represents the sum of the numbers at the input.



  A clock or sync pulse generator 12 continuously outputs square wave signals which determine the P-synch pulse periods. A pulse period is the interval between the leading edge of two successive clock pulses.

   The purpose of these periods is to determine the time allocated to a binary digit which is manifested for example by the output potential of a flip-flop. A high output potential on the connection of the right plate of eg a flip-flop expresses binary digit one, while a low potential at the same point represents binary digit zero.



  As a decimal digit is represented by a block of four binary digits, the presence or absence of a high potential on the inputs <I> His </I> or S ,, during each of the four consecutive pulse periods should be observed. Pulse counter 14, which counts the clock pulses from generator 12, defines the appearance of particular binary digits in a decimal block. This is accomplished by the outputs of the counting logic network 13 which together with the flip-flops <I> FI </I> and F2, constitutes counter 14.

   The output voltages of counter 14 represent counts <I> Pl, </I> P2, <I> P ;, </I> P4, Pl, P2, P.3, P. ,, etc., in a cyclic fashion. The count potential which is high during a given clock period, indicates which particular binary digit of a decimal block is observed at the input of additor 10.



  The following table 1 represents the binary code used to represent decimal digits.



  The synchronization pulses Pl, <I> P.>, </I> P3 and P4 for input, and P3, P- ,, <I> PI </I> and P2 for the output, define, with the digital weights associated with these pulse periods, 1, 2, 4, 2 respectively, the columns of the table.

   The decimal equivalent of the binary code at each horizontal row is thus obtained on the table by totaling the effective components of the
EMI0004.0032
  
     <I> Table <SEP> 1 </I>
 <tb> Enter <SEP> P, <SEP> P ,, <SEP> P @ <SEP>! <SEP> P,
 <tb> Pulse
 <tb> sync- <SEP> nisante <SEP> Exit <SEP> P_ <SEP> P, <SEP> P, <SEP> P,
 <tb> I
 <tb> Weight Digital <SEP> <SEP> I <SEP> 2 <SEP> 4 <SEP> 2 <SEP> I <SEP> 1
 <tb> I
 <tb> 0 <SEP> he <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0
 <tb> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1
 <tb> I
 <tb> 2 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 0
 <tb> Equivalent <SEP> 3 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1
 <tb> decimal <SEP> to <SEP> - <SEP> I- 4 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0
 <tb> entry <SEP> and <SEP> @ ._ <SEP> '_--' to <SEP> the <SEP> exit <SEP> 5.

    <SEP> II <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1
 <tb> 6 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0
 <tb> I <SEP> I
 <tb> 7 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 1
 <tb>.
 <tb> 8 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 0
 <tb> 9 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 numeric weight, indicated by binary 1 in the appropriate columns. It should be noted that the equivalents of the decimal digits 2, 3, 4, 5, 6 and 7 can be represented by two different combinations of codes. The code shown in the following Table II represents the inversion of a signal so as to obtain a complement code as desired when performing a subtraction.



  As will be seen in the description below, the value of a decimal digit at the input can be expressed in any of the two combinations without affecting the correct operation of the addition circuit. It should be understood, however, that the decimal digit at the output will always be represented by the code in table 1.

      
EMI0005.0001
  
     <I> Table <SEP> 11 </I>
 <tb> Pulse Synchronizing <SEP>. <SEP> Enter <SEP> P4 <SEP> P, <SEP> P @ <SEP> P,
 <tb> Weight Digital <SEP> <SEP> 2 <SEP> q <SEP> 2 <SEP> I <SEP> 1
 <tb> <U> I <SEP> I <SEP> I </U>
 <tb> 2 <SEP> I <SEP> 1 <SEP> @i <SEP> 0 <SEP> 0 <SEP> @ <SEP> 0
 <tb> 3 <SEP> i <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1
 <tb> Equivalent
 <tb> decimal <SEP> to <SEP> 4 <SEP> 1 <SEP> - <SEP> 0 <SEP> I <SEP> 1 <SEP> 0
 <tb> I
 <tb> entry <SEP> and <SEP> i
 <tb> I <SEP> Î <SEP> @ <SEP> I
 <tb> to <SEP> the <SEP> exit <SEP> 5 <SEP> I <SEP> 1 <SEP> [ <SEP> 0 <SEP> 1 <SEP>;

    <SEP> 1
 <tb> 6 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0
 <tb> 7 <SEP> 1 <SEP> I <SEP> 1 <SEP> i <SEP> 0 <SEP> 1 Referring again to fig. 1, we will now describe in detail how the adder 10 operates to add the decimal number 68 encoded in binary and introduced at the input S ,, and the decimal number 27, encoded in binary, simultaneously introduced at the input S ,,.



  In Table I, the decimal digit 8 is defined by a binary digit zero in the pulse position P1, while the positions P ,, P3 and P4 are defined by the binary digit one.

   Thus, in fig. 1, a relatively low potential is introduced at the input <I> His </I> during period P1, and a relatively high potential is introduced into Sa during periods P ,,, P3 and P4. The decimal digit 6, which immediately follows the decimal digit 8 at input S6 is represented in Table 1 by the binary digit zero for the period PI;

   followed by binary digit one for periods P, and P3, and finally followed by binary digit zero for period P4. Thus, a relatively low potential manifests itself in SQ during the PI period followed by a relatively high potential during the P @ periods. <I> and </I> P.3, and finally by a relatively low potential during the period P4. Similarly, we can recognize the decimal number 27 at the input S ,,

  . The input binary digits in each block are introduced in series into adder 10 in the same order as the count potentials P1, Pz, P i, P4 are fed.

   These counting potentials synchronize the additor 10 so that it gives each binary-coded input digit its weight and outputs the binary digits corresponding to the sum in sequence at the pulse periods. required. The sum signal S, is represented by the waveform corresponding to the decimal number 95.

   As shown in fig. 1, the output signal So is shifted by two periods, that is, it is two pulses behind from counter 14, in that the four binary digits of the outgoing decimal block, compared to the counts d The synchronizing pulses at the input are not assumed to be in positions P3, P4, PI and P, respectively.

   This is due to a delay of two clock pulses inherent in the establishment of the coded digits corresponding to the sum performed by the adder 10.



  The logical propositions can be considered as being represented in the circuits by the flip-flops which are electronic devices having two possible stable states, and only two. One of these two states is called true (it is sometimes represented in the tables by 1) and the other state is called false (0 in the tables).



  The true and the false state of a proposition preferably relate to terms which are physically represented in the circuits such as the direct voltage at a point for example. This tension can exist at one of two different levels. When a term is effective, the voltage is relatively high (E ,,); and when it is ineffective, the voltage is relatively low <B> (El,), </B> see fig. 3.



  Thus, by connecting the output lines, for example, to each of the tube plates of a flip-flop circuit, the output line having the relatively high voltage determines the effective state (or term) of the flip-flop. The other output line having the relatively low voltage then represents the ineffective state. In accordance with the present system, it is desirable to be able to control a propo flip-flop to its false or true state by signals applied to separate inputs.

   These input lines are coupled to the gates of each of the tubes of the flip-flop circuit; thus by applying a negative pulse to the correct input line, the flip-flop circuit can be controlled and switched to the desired state.



  The nomenclature used for the present invention uses combinations of upper case letters and numbers to designate the proposition flip-flops themselves. The outputs of the flip-flops are characterized by upper case letters corresponding to the associated num ber as a subscript. In order to differentiate the true state of a flip-flop circuit from the false state, the latter is distinguished from the previous one by the prime sign.



  On the other hand, the entries of a flip-flop are designated by the corresponding lowercase letters with the associated number in index. The entry which has the effect of putting a flip-flop in a false state is distinguished from the other by a zero index preceding the lowercase letter. <I> Pulse counter </I> Referring then to fig. 2, the flip-flops <I> FI </I> and F2 constituting the stages of the pulse counter, are illustrated diagrammatically.



  The logic equations defining the command inputs for each of the flip-flop stages are as follows: f1 = FX f, = F, 'F, CJ, = FIC "f, = F, F @ C The flip-flop outputs are connected to the inputs, so that the pulse counter can count through a cycle of four consecutive counts, ie P1, P ,, P3 and P4.



  The counter device is a parallel device in the sense that a pulse C from the synchro pulse generator 12 is applied to all the flip-flop inputs simultaneously. The gate interconnections (ga- ting) of the flip-flop outputs, however, only allow certain flip-flops to be controlled by successive pulses C, so that they can flip in a way. ordinate to indicate cycle counts.



  The combinations of flip-flop states that indicate the counter's digit content are shown in the following table. This table 111 is a binary representation of the pulse counts <I> PI to </I> P;

  .
EMI0006.0049
  
     <I> Table <SEP> 111 </I>
 <tb> Flip-flops
 <tb> F1 <SEP> i <SEP> F2
 <tb> P <B> l </B> <SEP> 0 <SEP> I <SEP> 1 <SEP> P4 '= <SEP> F, '+ F, F.,
 <tb> P_ <SEP> 1 <SEP> 1 <SEP> P, <SEP> = <SEP> F, F,
 <tb> P ,, <SEP> 0 <SEP> 0 <SEP> P, <SEP> = <SEP> F, 'F2'
 <tb> i
 <tb> P, <SEP> 1 <SEP> 0 <SEP> P, <SEP> = <SEP> F, F2 'Referring then to fig. 3, a schematic diagram is shown, showing how the flip-flop is connected <I> FI </I> to function as the first stage of the pulse counter.



  The flip-flop circuit used is well known, and it consists of two triodes V1 and V ,, the plate of each of them being connected to the gate of the other by a resistor R in parallel with a capacitor C. The plate of each triode is connected through a separate load resistor like resistor RI to a positive voltage source B -I-. The cathode of each triode is grounded.

    Each of the grids of the tubes is connected through a separate grid resistor R., to a bias source. <B> -E. </B> The flip-flop circuit is provided with control circuits associated with each of its gates and with output circuits connected to each of the plates.



  Whenever the flip-flop is considered to be in a state a <B>, </B> the neon lamp L, connected in series with a protection resistor Ro across the terminals to the left load resistor Rh, lights up; when the flip-flop is in zero state the neon light is off.



  The output lines <I> FI </I> and <i> Fi </I> flip-flop <I> FI </I> are taken on the right and left plates, respectively. In order to maintain the variation of the plate voltage between the levels El, and El, locking diodes such as the diodes 20 and 21 associated with the right output <I> FI </I> are provided on each output line.



  The flip-flops entries are controlled by gate circuits 22 and 23 associated with the tube grids <I> VI </I> and V., respectively. Each of the gate circuits 22 and 23 is coupled through a differentiation circuit 24 and a blocking diode 25 to the grid of one of the tubes, as can be seen in particular for the left grid, that of the tube. V1.



  For this particular counting stage, the output of the right plate <I> FI </I> is connected to one of the inputs of the left door 22, and the output of the left plate FI 'is connected to one of the inputs of the right door 23. The pulse C is applied simultaneously with the second input of each of gate circuits 22 and 23.



  These circuits 22 and 23 are logical networks. In such circuits, as can be noted in particular for the left gate 22, the inputs are applied to the cathodes of the diodes 27 and 28 whose anodes are connected to a common line 29 which joins the positive voltage source. B -; - through a load resistor R ;.



  Whenever the plate input of the gate circuit is at a high potential, the C pulse applied to the other input is sent to the output. This pulse is differentiated in the differentiator circuit 24 and the positive portion is blocked by the diode 25 while the negative portion passes and tilts the tube. <I> VI. </I>



  It is shown in FIG. 4, the voltage forms appearing at different points of the counter stage <I> FI </I> described above. On line 1, we can see the synchronizing periodic pulses C; on line 11, the voltage- output plate <I> FI </I> which is initially at high potential <B> (El,) </B> <I>;

   </I> on the line <I> 111, </I> the output plate voltage FÎ which is initially at a low potential <I> (El). </I> As can be seen on the line <I> IV, </I> whenever the tensions <I> FI </I> and C are simultaneously at a high potential, the term of f is supposed to pass through gate circuit 22 as a rectangular pulse similar in shape to that of pulse C.

   The pulse generator is low impedance so as to be sure that the leading edge of the pulse is not rounded but relatively square. On line V, the shape of the signal introduced at the input of the left gate is essentially the pulse resulting from the differentiation of the leading edge 1 from the rectangular pulse <B> J </B> j. j. We can therefore notice that the flip-flop <I> FI </I> changes state with the leading edge of the pulse o

  f j (pulse C). It should also be noted that, the left tube VI having ceased to conduct, the output-plate voltage FI 'increases gradually according to the time constant of the flip-flop circuit. The output Fr is now at a high potential, so that on arrival of the next pulse C, the right-hand gate circuit 23 passes the pulse C and, consequently,

   the differentiated front edge 32 of this last pulse causes the flip-flop to switch <I> FI </I> to its original state.



  It now becomes evident that the C pulses divide the time of the circuit operations into two distinct phases. During the first phase of a pulse period, when the pulse generator voltage is low, transient phenomena occur. For assured operation, these transient phenomena must be terminated before the arrival of the leading edge of the C pulse.

    During the duration of the pulse, the circuits of the logic network can be considered to be observing flip-flops and other input sources in order to determine whether a pulse should or should not pass over the gate. of a flip-flop. The pulse C must be long enough so that it can, taking into account its rise time, reach its peak amplitude before the end of the clock period. The pulse must also be produced by a low impedance generator, so that a square edge can be created on the leading edge of the pulse passing through the gate circuits.

   These conditions make it possible to create, by differentiation, a negative pulse, coinciding with the end of the clock period, which can be used to toggle the flip-flops. Reference will now be made to FIGS. 2 and 5. Instead of showing the wiring diagrams of the logic circuits, as in fig. 3, the remaining circuits have simplified block diagrams of the flip-flops. It is understood, however, that all the flip-flops are identical.

   As seen in fig. 2, only the entry and exit lines of the flip-flop are shown and these are marked according to the convention outlined above. In addition, the gate entry differentiation and blocking circuits are omitted in the overview diagrams for simplicity. Only the gates, indicating the logical product of the control input and the clock input are shown at each of the inputs, so as to emphasize the fact that the C pulses are applied simultaneously to all the flip-flop inputs. .



  The logic equations define when and how the flip-flop circuits must change state according to the actual terms of the system during each clock period of the system cycle. Writing the gate control logic equations of a flip-flop circuit amounts to indicating the terms which must simultaneously have a high potential for a given flip flop in a given state to flip. Two separate operations are used in the equations.

   The first, logical multiplication, means that all of the terms in the particular product of the equation must be relatively high potential for that product to be effective in the equation. The second, logical addition, means that at least one of the terms of the sum must be of relatively high potential for that sum to be effective in a particular equation.



  So, for example, the logical equation <B> bone, </B> = S; the S3 (P @ + S # "S3) C which is physically carried out by the network of fig. 11, can be interpreted as stating that the SI flip-flop can switch to its false state at the end of a clock pulse period during which the following four terms are at a high potential: <B> <I> Sa ', </I> </B> Sb ' <I>, </I> (P4 ' <I> + </I> S_'S; ') and C;

   the term (Pl ' <I> + </I> &'S;') itself and interpreted as having a high potential if any of the terms P ° and / or (S "S3 ') at least is at a high potential.



  The particular representation of these logical equations was chosen, because these equations can be treated according to certain well-known rules of Boolean algebra. When we have once described the means of physically realizing a typical logic product and logic sum circuit, current techniques allow logic circuits to solve the entire logic system to be established by referring directly to the equations alone. The set of logic circuits generally appears as a large interconnected network made up of these two fundamental circuits.

   By reducing the equations to physical circuits, we come to recognize the fact that certain common complex terms and certain partial products can be produced only once and used several times in other parts of the networks as necessary. This simplifies the logic equations and therefore reduces the number of elements in physical circuits, but often comes at the cost of complication.

    in the search for original logical equations Cr ne. The techniques present nevertheless allow the original system of thought to be retained in the equations, even if the equations are revised several times, as long as the revisions remain in accordance with the rules of Boolean algebra.



   <B> He </B> It should be noted that in the current art, the circuits intended to solve logic multiplications are also called gates and the circuits which solve logic additions are also called mixers or mixers. Returning to fig. 2, the conditions necessary for causing the flip-flop FI to switch, as has already been described in connection with FIG. 3, are represented by the symbolic logical equations f1 <I> = </I> 171'C <I> and </I> of, <I> = </I> 171C.



  Looking at the states of the F flip-flops, as shown in Table 111, the symbolic logical equations for the F2 flip-flop can be similarly determined. The conditions necessary to make the flip-flop F2 switch to its true state, that is to say from state 0 to state 1, are that the flip-flop <I> FI </I> either in a true state and the F2 flip-flop itself in a false state;

   this can be denoted symbolically by f2 = F @ 'FIC. Likewise, the necessary conditions for making the F2 flip-flop to a false state are that the F2 flip-flop is true as well as the flip-flop. <I> FI </I> either <I> of., = </I> F2FIC.



  The diode logic networks used to solve all the control equations for the pulse counter 14 will be shown in fig. 5.



  Networks capable of physi cally solving the equations o f I <I> = </I> FIC <I> and </I> f I <I> = </I> F, 'C associated with flip-flop <I> FI </I> are the gate circuits 22 and 23 respectively, as shown previously in FIG. 3.

   These circuits are simply represented by designating the inputs of gate 22, which is a typical two-input product gate by the terms of the equation <i> " </I> f1 and designating the inputs of gate 23 by the terms of equation f1. The outputs of these gates are respectively marked Jl and f1. Each of these product circuits is such that whenever any of the inputs is at a relatively low potential, the output is also at a relatively low potential;

   if, on the other hand, all the inputs are at a relatively high potential, the output is at a relatively high potential. In other words, the output potential is equal to the lowest input potential.



  The equation which makes it possible to produce f2 is, in fig. 2, a product of the same two terms defining off multiplied by a term adding F2 '. It will be noted in fig. 5 that, instead of providing a three-input product circuit to solve equation f2,

      the output of dual input product circuit 22 is cascaded to a second dual input product circuit 40 along with the new term F2 '. Thus the output f <i> 2 </I> of the second dual input product circuit 40 provides the solution of f2.



  The equation of2 also contains the common product defining off. This is why the output of the double-input product circuit 22 feeds one of the inputs 41 of a third double-input product circuit 42 as does the new term F.,. The output of this third product circuit 42 provides f2- The above circuits clearly illustrate how the equations that define the inputs to proposition flip-flops work,

   reveal how the outputs of the flip-flops are logically interconnected with the inputs, i.e. define when and how the flip-flops should change depending on the conditions of the other proposals of the system.



  The equations representing the impulses <I> P. ,, </I> P, 3, <I> PI </I> and P4 define the terms time necessary for terminal adder circuits. These time terms are composed, according to Table 111, of the logical products of the terms represented by the outputs of the flip-flops F. These products are obtained physically by the networks of FIG. 10.

   We can see that P2 <I> = </I> (FIF @) occurs on the line <I> 64; </I> P @ <I> = </I> FI'F2 on line 65; P ,, = (171F2) on line 66, and P4 <I> = (Fi </I> -I- FlF2) on line 67. <I> Sum circuits </I> The. addition or total circuit 10 of FIG. 1 will now be described in detail.



  The sum of the weighted inputs Sa and Sb is accumulated in the addition flip-flops, in the binary digital system, during each synchronization period;

       however, like; we can notice it by comparing the fi-. 6, 7, 8 and 9, each addition or sum flip-flop does not represent the same digit position stage of the binary system during any double pulse period of a count cycle.

       For example, the flip-flop SI represents successively stages 2, 21, 22 and 23 during the respective periods P1, P2, <I> P3 </I> and <I> P4. </I> For this reason, the overall action of the addition circuit can be better understood by first explaining the addition action by each of the four periods of a cycle.



  The general plan used to present and describe the action of the adder during each pulse period is as follows During each of the periods P1, P. ,, P3 and P4 of the addition cycle, the inputs Su and Sr, the value defined by Table I or Table II. In addition, the addition flip-flops <I> S1, S2 </I> and S3 accumulate information during each of these periods, as can be seen in the tables associated with the addition flip-flops of fig. 6, 7, 8 and 9.



  These are as follows <I> PI pulse period </I> (see fig. 6)
EMI0010.0025
  
     <I> Table <SEP> IV </I>
 <tb> Flip-flop <SEP> S1
 <tb> <U> i </U>
 <tb> Stadium <SEP> @; <SEP> 2
 <tb> I
 <tb> Content <SEP> decimal <SEP> I <SEP> 0 <SEP> 0
 <tb> i
 <tb> from <SEP> adder
 <tb> 1 <SEP> 1 <I> Pulse period </I> P_> (see fi-. 7)
EMI0010.0027
  
     <I> Table <SEP> V </I>
 <tb> Flip-flop <SEP> S1 <SEP> I, <SEP> S2
 <tb> I
 <tb> Stadium <SEP> 21 <SEP> 2
 <tb> <U> i </U>
 <tb> 0 <SEP> he <SEP> 0
 <tb> Content <SEP> decimal <SEP> 1 <SEP> - <SEP> 0 <SEP> 1
 <tb> i
 <tb> from <SEP> adder
 <tb> 2 <SEP> 1 <SEP> 0
 <tb> 3 <SEP> 1 <SEP> 1 <I> Pulse period P;

   </I> (see fig. 8)
EMI0010.0029
  
     <I> Table <SEP> UI </I>
 <tb> Flip-flop <SEP> S1 <SEP> S2 <SEP> S3
 <tb> i
 <tb> Stadium <SEP> 2 ' <SEP> 2 ' <SEP> 2 "
 <tb> 0 <SEP> Ii <SEP> 0 <SEP> 0 <SEP> 0
 <tb> 1 <SEP> I <SEP> 0 <SEP> 0 <SEP> 1
 <tb> 2 <SEP> 0 <SEP> 1 <SEP> 0
 <tb> Content
 <tb> decimal <SEP> of <SEP> 3 <SEP> 0 <SEP> 1 <SEP> 1
 <tb> adder
 <tb> 4 <SEP> 0 <SEP> 0
 <tb> I <SEP> 5 <SEP> 1 <SEP> 0 <SEP> 1
 <tb> 6 <SEP> 1 <SEP> 1 <SEP> 0
 <tb> i <SEP> --I
 <tb> 7 <SEP> 1 <SEP> 1 <SEP> 1 <I> Pulse period Pl </I> (see (fi-.

   9)
EMI0011.0001
  
     <I> Table <SEP> V11 </I>
 <tb> Flip-flop <SEP>! <SEP> S1 <SEP> S2 <SEP> S3 <SEP> Exit
 <tb> __ <SEP> <U> I </U>
 <tb> i
 <tb> Stadium <SEP> 23 <SEP> 22 <SEP> 21 <SEP> 20
 <tb> n
 <tb> 0 <SEP> \ <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0
 <tb> I
 <tb> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1
 <tb> 2 <SEP> I <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 0
 <tb> i <SEP> I- I
 <tb> 3 <SEP> o <SEP> 0 <SEP> 1 <SEP> 1
 <tb> 4 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0
 <tb> I
 <tb> 5 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1
 <tb> Content
 <tb> 6 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0
 <tb> decimal
 <tb> i
 <tb> 7 <SEP>.,

    <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 1
 <tb> from
 <tb> 8 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0
 <tb> addition 9 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1
 <tb> neur
 <tb> 10 <SEP> 1
 <tb> 0 <SEP> 1 <SEP> 0
 <tb> 11 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 1
 <tb> 12 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0
 <tb> 13 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 1
 <tb> 14
 <tb> 1 <SEP> 1 <SEP> 1 <SEP> o
 <tb> i <SEP> 15 <SEP> [@ <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 With these values assigned to the terms of the logic grid equations, the control signals are derived to toggle the flip-flops at the end of each of the pulse periods in question, so as to store them in the addition flip-flops an accumulated count, as indicated by the table associated with the following period.

   During the period <I> PI </I> for example, the logical networks of SI flip-flops <I> and S2 </I> direct the inputs S ,, and Sv to the adder, at the same time as the information contained in the flip-flop SI. At the end of period P1, control signals are thus obtained to change the state of the addition flip-flops <I> IF </I> and S2 so as to establish at this point the accumulated sum indicated by table V.

   Similarly, during the period Pz, the logical networks of the SI flip-flops <I> and S2 </I> direct the Sd and Sb inputs, as well as the information of the SI and S2 flip-flops, so as to establish the SI flip-flops, <I> S2 </I> and S3, at the end of the period P #, in a state representing the accumulated sum as defined by Table VI. <I> PI pulse period </I> We can see in fig. 6, the synoptic diagrams of SI flip-flops,

   S2 <I> and S3, </I> the logic control equations associated with each of the grid inputs during the PI period being the following st = S ,, SbCPl OS1 = S @ Sb 'CPl s2 = [Sl (S.,' Sb -I- SaSh) + Si (S @ Sb + S., 'Sb)

  ] CPl S @ 3 - [S1 (Sa Sb + S, Sb) + Sl (S ,, Sb '+ Sa'Sb)] CPl 53 = 0 Osa = S2 CPl As noted, the flip-flop <I> IF </I> represents stage 20 of a binary counter,

   while the flip-flops <I> S2 </I> and <I> S3 </I> contain information representing the fourth and third binary digits respectively of the coded decimal sum digit resulting from the previous addition cycle, and they are, therefore, represented by broken lines.

       Table IV gives the decimal content of adder, as found in the flip-flop <I> IF </I> during the period <I> Pl. </I> This content represents the presence or absence of a decimal retention of the previous addition cycle. During period Pl, as can be seen in Table I, the effective external inputs (high potentials) received at S ,, are assigned to <I> and Sb </I> a unit weight.

   The maximum accumulated deci mis count, capable of being routed during the period <I> PI </I> is therefore 3: an entry on S ,, and Sb, and a carry from the previous addition cycle. This accumulated total can be established in binary form in SI flip-flops and <I> S2 </I> at the end of period Pl, and accumulated there during period P.- Table V shows the states that must be assumed by flip-flops <I> IF </I> and S2 at the end of the period <I> PI </I> to represent the ac count accumulated during the period <I> Pl. </I>



       It should be noted that the flip-flop SI represents the stage or digital position 20 of the binary counter during the period <I> Pl. </I> However, due to the exploration of the information available during the period Pl, the flip-flop <I> IF </I> is controlled so as to store the information corresponding to stage 21 of a binary counter during the period P ,,, as indicated by table V. Looking at this table, it becomes obvious that the flip -flop <I> IF </I> should be in state one- for a partial decimal of 2 or 3.

    These conditions are: 1o) a carry or carry over from the previous addition cycle and a unit entry on <I> Su </I> or <B> IF, </B> or on both; or 2,) no carryover from the previous addition cycle and one, unit entry on S ,, and <I> Sb. </I> But, as explained previously, a carry over from the previous addition cycle is lost in the flip-flop <I> IF </I> during the period <I> Pl. </I> If a hold exists, the flip-flop <I> IF </I> will already be in state one.

   Thus the logical grid equation necessary to control the state one of the flip-flop <I> IF </I> must satisfy only the second of these conditions if - S.SbCP1 Referring again to table V, the flip-flop <I> IF </I> should switch to state zero for accumulated decimal sums of 0 or 1. These conditions are: 1, I) no carry and a unit entry on Sa or Sb or on neither; or 20) a carry over and no entries on <I> Su </I> or Sb.

   But again, as the carry was stored in the flip-flop <I> IF </I> during period Pl, if there is no carry over, the flip-flop <I> IF </I> will already be in a zero state <B>. </B> So, again, the logical equation necessary to control the zero state of the flip-flop <I> IF </I> only has to satisfy the second of these conditions:

   <B> Bones, </B> - Sa'Sb CPi The content of flip-flop S2 corresponds to the fourth binary digit of the coded decimal sum, derived from the previous addition cycle and, therefore, is not used during the action summation of the period <I> Pl. </I> However the S2 flip-flop is used in order to store the sum of the entries explored during the period <I> Pl. </I> So, as can be seen in Table V, the S2 flip-flop represents stage 2 of a binary counter and is in the zero state for accumulated decimal counts of 0 and 2 and in state one for accumulated decimal counts of 1 and 3.

   Considering in the first place the logical grid equations to cause flip-flop S2 to switch to state one at the end of period Pl, all the possible conditions which give a partial decimal sum of 1 or 3 during time <I> PI </I> must be considered. These conditions are: l o) a carry over from the previous addition cycle and no entries on Sd or <B> <I> IF, </I> </B> <I>; </I> or 2) a carry forward and a unit entry on SQ, and <I> Sb; </I> or, finally, 30) no carry over from the previous addition cycle and a unit entry on <I> Su </I> or Sb, but not both.

   The logical grid equation satisfying the above conditions is s; 3 - [sl (Sa'sb '+ SasL) <B> + </B> Si '(S @@ Sn'-f- Sa S ,,)] CP, Then studying the gate logic equation to control S2 flip-flop to zero at the end of the period Pl, we see that all the possible conditions which give a partial decimal sum of 0 or 2 must be considered.

   These conditions are <B>: </B> 1 1,) no carryover from the previous addition cycle and no entries on S, or SL; or 2, -) no carry and one unit entry on S ,, and S ,,; or, finally, 30) a carry forward and a unit entry on <I> Su </I> or SU, but not on both.

    The logical grid equation satisfying these conditions is "52 = [sl '(S. Sb' + S.sb) + Sl (S.Sû + S.'Sb)] CPl During period Pl,

      the flip-flop <I> S3 </I> accumulates the third binary digit of the coded decimal number resulting from the previous addition cycle and sees the fourth binary digit of the coded sum shifted towards it from the flip-flop <I> S2 </I> at the end of the period <I> Pl. </I> So the logical grid equations will be derived by the flip-flop <I> S3 </I> at the start of the next addition cycle.



  It can be seen from Table I that the first output potential emitted from the adder during the period of P., will indicate whether the sum decimal digit is odd or even. An output sum of 0, 2, 4, 6, 8, 10, 12, 14, 16, or 18, i.e. all even numbers will have a <B> </B> zero <B> </B> as the first exit potential. Likewise, an output sum of 1, 3, 5, 7, 9, 11, 13, 15, 17, and 19 will have one as the first output potential.

   If we notice that the weights of the Su and Sv inputs after the first pulse period are even values, i.e. 2, 4 and 2 for the periods <I> P. ,, </I> P3 <I> and P4 </I> respectively, it appears obvious that one can determine during the period P_, whether the final digit of the decimal sum has an even or odd value.

   The representative potential of the first output binary digit can thus be immediately determined from the flip-flop <I> S2 </I> during time P2. However, since the remaining output binary digits cannot be determined in order, it is necessary to delay the use of this first output binary digit for another pulse period.

       <I> Pulse period P., </I> Referring then to fig. 7, the synoptic sche mas of flip-flops <I> IF, S2 </I> and <I> S3 </I> are shown and the control logic equations associated with each of the grid inputs for the period P., are as follows <B> IF </B> = SaSbCP2 <B> Bones, </B> = S.'Sb, CP2 S2 = [Sl (Sa Sb + S., Sb) + Si (S #, sb + Sz Sb)] CP2 Ose - [Sl (Sa,

          Sb + SaSb) + Sl (S.Sû + S. "Sb)] CP # -1 S3 = S2CP2 osa = S2 'CP2 Table V provides the decimal content of these addition flip-flops during period P2. Actual inputs (high potentials) received at Sa and Sb during this time have the weight of two (Table I).

   The maximum decimal count that can be scanned during this period P2 is 7, a possible decimal value of 3, stored in the addition flip-flops together with an entry of two units on <I> His </I> and Sv. This decimal count explored during period P., is stored as a binary number in the addition flip-flops during period P3 according to Table VI.

    As is easily understood, the fact of increasing a binary number by a power of 2 does not affect the binary digits representing the lower order stages of the binary number, i.e. the fact of d 'increasing a binary number by 21 or 2 does not affect the binary digit representing the order of 20 of the binary number; and increasing a binary number by 22 or 4 does not affect the binary digit representing stage 2 or 21; etc.

   By this reasoning, the content of flip-flop S2, which represents stage 20 during period P, cannot change as a result of the inputs received during period P2 and thus, it is simply shifted to flip-flop S3 for period P2. So the logical grid equations for the flip-flop <I> S3 </I> during period P2 become and S.3 = S., CP., Osa = SI 'CRI The flip-flop S2 represents,

   as can be seen in Table VI, stage 21 or numerical position of a binary number during time P; h state one of this flip-flop S2 representing a partial decimal sum of 2, 3, 6, or 7.

   The possible conditions to give a partial decimal sum of 2, 3, 6 or 7 during the time M are: 1o) a partial decimal sum of 2 or 4, emma gasiné in the adder and no entries on Sd nor on Sb ; 20) a partial decimal sum of 2 or 3 in the adder and an entry of two units on <I> His </I> and on S6; 30) a partial decimal sum of 0 or 1 in the adder and an entry of two units on Sd or on Sb but not on both.

   By examining Table V, we can see that a partial decimal sum of 0 or 1 during the time P, will be indicated by a zero state of the flip-flop. <B> <I> IF, </I> </B> and that a partial decimal of 2 or 3 in the adder will be evidenced by a state one of the flip-flop <B> <I> IF. </I> </B> It follows that the logical grid equation which satisfies the above conditions is written s2 = [Sl (Sa Se + S., Sb) + Sl (Sa, St,

  '+ S #,' S ,,)] CP_, In Table VI, a partial decimal sum of 0, 1, 4 or S is indicated by the zero state of the flip-flop S2 during the time P,;. The possibilities for this are: 10) a partial decimal sum of 0 or 1 in the adder during time P2 (table V) and no inputs on Sd or Sb; or 2 (1) a partial decimal sum of 0 or 1 during the time P ,, and an entry of two units on Sa and on Sb;

   or, finally, 3o) a partial decimal sum of 0 or 3 in the adder during the time P2 and an entry of two units on Sd or on Sb, but not on both. As it has been indicated before, a partial decimal sum of 0 or 1 is evidenced in the adder during time P2 by a zero state of the flip-flop <I> IF </I> and a partial decimal sum of 2 or 3 is evidenced in the neur addition during time P2 by a state one of the SI flip-flop.

   So the logical grid equation to switch the flip-flop S2 to a false state at the end of time P., is os-2 = [S1 (s. Se + s., Sb) + Sl (S @ Sb '-, Sa Sb)] CP2 It appears evident from Table VI that the partial decimal sums of 4, S, 6 and 7 are indicated by a state one of the flip-flop SI during the time P;

  . The possible conditions for obtaining one of these sums are <B> l o) </B> a partial decimal sum of 2 or 3 during the time P., and an entry of two units on <I> His </I> or Sb, or both; or 2o) a partial decimal sum of 0 or 1 during the time P @ and an entry of two units on <I> His </I> and on <I> Sb. </I> As a partial decimal sum of 2 or 3 in the adder during the time P., is already highlighted by the state <one of the flip-flop <I> IF, </I> The logical grid equation only needs to be described for the last condition above,

   i.e. s1 = Sa, St, CP, Likewise, the logical grid equation for flipping the flip-flop <I> IF </I> to a zero state at the end of period P.> only needs to be considered for the condition in which a partial decimal sum of 2 or 3 exists in the adder (table V), no input not being received during time P2, therefore "s1 = Sz, 'SbCPs <I> Period </I> impulse <I> P; </I> The action of the adder will now be described for the period P;

  . Fig. & is a diagram of the adder flip-flops and the grid logic equations during this period are as follows <B> if </B> - S;, SbCPs Usl = Sa 'Se CP33 = [Sl (S ,,' Sb + S ,, Sb) + Sl '(Sa, Sb + S; i Sb)] CP;

              <ss = [Sl '(S. Sb + S.Sb) + Sl (S #, Sb' + S ,, 'S ,,)] CPï s ;; = S., CP "s3 = S2'CPs Table VI gives the decimal equivalent of the accumulated sum which is stored in binary form in the adder during the time P ;; and represents a conventional binary number system of three stages .

   The weight of the effective external inputs (high potentials) received at S ,, and Sb is four units for each during period P; as shown in the table. As can be understood, and following the previous detailed explanations, increasing a binary number by four or eight units will not affect the digits of the binary number representing stages 21 or 22.

   Therefore, the contents of the flip-flop S2 during the time P ;, representing stage 21 or numerical position of a binary number form of the contents of the adder (Table VI), is simply transferred to the flip -flop S3 (Table VII), representing the same stage of a binary number form of the contents of the adder at the end of period P ;.

   Thus the logical grid equations of the flip-flop <I> S3 </I> become s3 = S., CP3 and Osa = S2, CP3 According to Table VII, which represents the content of the adder during period Pl in the form of a binary number, it can be noted that the flip-flop S2 which represents the stage or digit 22 of a binary number, do in a state opposite to that of the flip-flop <I> IF </I> during period P3 (Table VI) for a decimal increase of 4,

   and do in the same state as the flip-flop <I> IF </I> for a decimal increment of 8. As the inputs Sa and Sb received during the period P ;, have the weight of four units, we can say that the flip-flop S2 should be during the period P4 in the state of the flip-flop <I> IF </I> during period P3, as they both represent the same stage, i.e. 223 during their respective periods, in case <I> Su </I> or S ,, would not receive any input, or in case inputs of four units were received by S ,,

      and SL during the period P;,. We can also say that the flip-flop S2 should be, during the time P4, in a state opposite to that of the flip-flop <I> IF </I> during time P, h if an input of four units was received by S, or SU, but not by both.

   The gate logic equations of flip-flop S2 during period P3 are therefore ss = [Sl (S @ 'Sb' + SII.Sb) + Sl '(S.Sb' + Sa'Sb)] CP3 os-2 - [S1 (Sa Sb + SaSb) + Sl (S ,, Sb + Sa'Sb)] CP ;;

       It will be noted from Table VII that the SI flip-flop is at the end of period P3 in a state one for decimal values from 8 to 15 inclusive and in a zero state for values from 0 to 7 inclusive. .

   Considering first the logical grid equation for flipping the flip-flop <I> IF </I> to state one <B> </B> during time P3 'the possibilities for a partial decimal sum from 8 to 15 inclusive, at the end of time P3 are: 1, I) a partial decimal sum from 4 to 7 included in the adder and an input of four units in <I> His </I> or <I> Sb </I> or in <I> His </I> and Sv, during the time P3;

   or 20) a partial decimal sum of 0 to 7 included in the adder and an input of four units on Sd and Sb during the time <I> P3. </I> The flip-flop <I> IF </I> is already in a state one (table VI) for partial decimal sums from 4 to 7 inclusive; therefore, the equation only needs to be written for the second possibility, let s1 = SaSbCP3 The possibilities for a partial decimal sum from 0 to 7 inclusive at the end of time PÏ are:

   10) a partial decimal sum of 0 to 3 in the adder during the time P3 and an entry of four units on Sd or on Si,.; or 20) a partial decimal sum of 0 to 7 in the adder and no inputs on Sa or Sv during time P3. But the SI flip-flop is already in state zero (Table VI) for partial decimal sums of 0 to 3 inclusive during time P3;

   and thus it is necessary to write the equation for the second possibility only <B> bone, </B> - S.'S ,, 'CP ;; A comparison of the gate logic equations for the addition flip-flops during the periods Ph P2 and P3 shows that they are identical, except for the equation s;

  ,    during the period <I> Pl. </I> For example, the logical grid equations allowing to bring the flip-flop S2 towards a state one, that is to say S2 - [Sl (Sa, Sb + S..sb) + Sl '(S.Sb + S. Sb)] C are the same for the three pulse periods if we do not take into account the period term itself.

   This similarity of the additor flip-flop gate logic equations is very advantageous, as it allows the same logic network specified for each addition flip-flop gate to be used for three of the four periods. Not only does this greatly facilitate the Logic specifications of the system, but also results in a reduction in the elements necessary to physically realize the equations compared to the case where a separate logic network is specified for each grid and for each period of time. 'impulse.



  It should be noted that the first output potential, that is to say the first output binary digit, indicating the even or odd character of the total decimal sum, is emitted by the adder during the period P ;;. This first output binary digit is the digit stored in the flip-flop <I> S3 </I> following binary counting. The logical equation defined for how this operation is performed will be explained in the discussion below.

       <I> Period </I> impulse <I> P4 </I> The logical grid equations for controlling the flip-flops during the period P4 are as follows <B> IF </B> = S, SbCP4 <B> OS, </B> = ss3, sa'sb, CP4 S._ = SZ S3 CP4 use - S2 [Sl (Sa.sb '+ Sa Sb) + Sa' Sb + S2'l CP4 S3 - S3 [S2 (Sa,

  + Sb + <B> IF ') </B> + SIS2'SI'Sb] CP4 "s3 = S3 [S @ S @ (S ,, Se + S ,, 'Sb) + Sl' S., Sb + S2 'S-" Sb] CP4 Il now becomes evident that, by noting the partial decimal sum stored in the counter and observing the inputs during period P4,

      all information regarding the entered coded digits becomes available and the binary coded decimal digit representing the sum can be clearly defined. The arrays for determining the value of the second, third and fourth output binary digit can be understood by referring to the encoded decimal table I.

   The second output binary digit is output directly from the logic network which establishes it during period P4. The third output binary digit, on the other hand, is stored in flip-flop S3 at the end of period P4 and is transmitted by the adder during the following period. <I> Pl. </I> Information, indicating whether the fourth binary output digit is different from the third binary digit,

   is stored in flip-flop S2 at the end of period P4. This information is then suitably used to control the flip-flop S3 at the end of the following period P1, so that it can transmit the fourth output binary digit during the following period P. =. The carryover digit, which exists for all total decimal sums from 10 to 19, is also determined by a logical network during period P4 and is stored in the flip-flop <I> IF </I> at the end of period P4.



  As the second binary digit is transmitted directly out of the adder, from the logical network which establishes it, this network will not be introduced this time, but rather we will describe the logical equation to store the third output binary digit in the S3 flip-flop. Note that although the binary coded output decimal digit is always represented by the code of Table I, the input of the adder may be represented by the code of Table I or Table II.

   As can easily be understood, by carrying out subtractions with the aid of numerical calculators, the larger number can be reversed so as to give the nine's complement and added to the number to be subtracted. As said before, Table II is obtained by inverting the signal of a number so as to obtain a nine's complement code as desired for a subtraction.



  As mentioned above, the third binary digit is read on the S3 flip-flop during the period <I> PI </I> following. According to table 1, the flip-flop <I> S3 </I> should be in state one during the following period PI for total decimal sums of 4, 5, 6, 7, 8, 9, 14, 15, 16, 17, 18 and 19. As the flip- flop S3 is in the same state whether the sum is 4, 5, 6 or 7, etc., only the even values 4, 6, 8, 14, 16 and 18 should be considered.

   During the time P4, three entry conditions must be considered 1 1,) no entries in Sz or in S ,,; 20) an entry of two units in S or S ,, but not both; or 3o) an entry of two units in S "and in S ,,.



  If we consider the first entry condition characterized by the absence of entries during the time P4, the flip-flop <I> S3 </I> had to be toggled to state one at the end of time P4 for partial decimal sums of 4, 6, 8 or 14 in the adder during the period <I> Pi. </I> But according to Table VII, the S3 flip-flop is already in state one <B> </B> for partial decimal counts of 6 and 14, so only adder content of 4 or 8 should be considered.

   From where
EMI0017.0020
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 4 <SEP> + <SEP> 0 <SEP> = <SEP> s ,, <SEP> s.s; <SEP> sl's ,, '
 <tb> 8 <SEP> @ - <SEP> 0 <SEP> = <SEP> SIS- <SEP> S. "S;, 's ,; Regarding the second entry condition characterized by a two-unit entry on S ,, or on Sb, the S3 flip-flop should switch to a state of one for partial decimal sums of 2, 4, 6, 12 or 14.

   Looking at table VII, we can observe that the partial sums of 2, 6 and 14 are eliminated, because the S3 flip-flop is already in state one for these partial sums, which leaves to study only the sums parts 4 and 12.

   From where
EMI0017.0027
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 4 <SEP> + <SEP> 2 <SEP> = <SEP> If <SEP> Szs3 <SEP> (S ,, S3 <SEP> + <SEP> S <B>.% </B> 'Sb)
 <tb> <U> 12 <SEP> + </U> <SEP> 2 <SEP> = <SEP> SlS2S3 <SEP> (Sa, Se <SEP> + <SEP> His <SEP> Su) As regards the third entry condition characterized by an entry with two units in Sd and in Sv, the flip-flop <I> S3 </I> should switch to state one for partial decimal sums of 0, 2, 4, 10, 12, or 14.

    But from Table VII, we can see that the flip-flop <I> S3 </I> is already in state one for partial sums of 2, 10 and 14, which leaves to study only the partial sums 0, 4, and 12. A further simplification can be made by studying the tables I and II.

   When at the same time Sd and SF, have inputs of two units during period P4, at least one of the input decimal digits of the adder must be 8 or 9, the other input decimal digit of the adder can be the nine's complement, as expressed by Table II representing the large number in a subtraction as seen above. This means that a partial decimal sum of at least 6 must exist.

    in the adder when SQ and Sh both have inputs of two units during period P4. This eliminates partial sums of 0 and 4 as impossible. Only the partial sum of 12 remains to be considered. In order to simplify the equations of logical networks, however, a term is sometimes introduced which represents an impossible condition to actually achieve in the system. This is allowed because, since the condition represented by the term never occurs, the added term cannot affect the results. Thus the partial sum of 4 will be included in the conditions which are examined here.

   From where
EMI0017.0051
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 <tb> <U> by </U> tie <U> she </U> <SEP> t <U> ota </U> l)
 <tb> 4 <SEP> + <SEP> 4 <SEP> = <SEP> If <SEP> S.S <B> J </B> S.S ,,
 <tb> 12 <SEP> + <SEP> 4 <SEP> = <SEP> SIS <B> -l </B> S ;; 'S; tS ,, Summarizing all the above conditions for which the flip-flop <I> S3 </I> switch to state one, the following table is obtained
EMI0018.0004
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 4 <SEP> + <SEP> 0 <SEP> = <SEP> Sl'S., SI ' <SEP> S ,, 'S ,,'
 <tb> 4 <SEP> + <SEP> 2 <SEP> = <SEP> Sl'S2S3 (S:

  @ Sl @ <SEP> + <SEP> S., ' <SEP> Sil)
 <tb> 4 <SEP> + <SEP> 4 <SEP> = <SEP> Sl'S.IS3S ,, S ,,
 <tb> 8 <SEP> + <SEP> 0 <SEP> = <SEP> SlS2'S3 <SEP> S3 <SEP> S ,, '
 <tb> 12 <SEP> + <SEP> 2 <SEP> = <SEP> S, S., S3 <SEP> (S ,, S ,; <SEP> + <SEP> S ,, ' <SEP> S ,,)
 <tb> 12 <SEP> + <SEP> 4 <SEP> = <SEP> S, S_, S; 3 <SEP> S.Sk, We deduce from this table that, for a partial decimal sum of 4 in the counter, the flip-flop S3 should be in a state that there is no entry or whether there are one or two of two units received during period P4. The logical grid equation expressing this characteristic can be written (1)

       s.3 = Sl'S - S. CP.4 Note further that, for a partial decimal of 4 or 12, the S3 flip-flop should be switched to state one, either with a single input of two units, or with two inputs of two units received. during period P4. Therefore (2) s; i = S- "S3 (S a + Sh) CP4 Which leaves only the partial decimal sum of 8 with no entries to resolve.

   Therefore: (3) s @ = SIS- S3 S., 'Sh CP4 By combining equations (1), (2) and (3), the logical grid equation to bring the S3 flip-flop to the state one at the end of period P4 is s ;, = S3 [Sl'S -, + S @ (Sa + S [) + SJS @ Sa'S ,;

          jCPl or by grouping the terms
EMI0018.0031
  
    ss <SEP> = <SEP> S3 <SEP> [S, (Sa + <SEP> Sl, + <SEP> <B> IF ') </B> <SEP> _- <SEP> SIS. <SEP> S, 'S, i <SEP>] CP4 It can be seen from table I that the flip-flop Se should be in the zero state during the next impulse <I> PI </I> for total decimal sums of 0, 1, 2, 3, 10, 11, 12 and 13. On the other hand, like the flip-flop <I> S3 </I> is in the same state for total decimal sums of 0 and 1, 2 and 3, etc., only even values 0, 2, 10 and 12 should be considered.



  If we first consider the condition for which no input is received during period P4, and examine Table VII, we can see that flip-flop S3 is already in state zero for partial sums of 0 and 12, and only the partial sums of 2 and 10 remain to be studied.

    Further examination of Table VII shows that, since these are even partial decimal sums, the partial sums of 2 and 10 are unique for the condition where flip-flop S2 is in the zero state and the flip-flop <I> S3 </I> in state one. Therefore
EMI0018.0041
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 2 <SEP> or <SEP> 10 <SEP> + <SEP> 0 <SEP> = <SEP> S, 'S.3S, " <SEP> S ,; When a two-unit input is received in S "or <B> IF, </B> but not for both, during period P4 the partial sums of 0 and 10 must be considered.

   But on the other hand, according to Table VII, for a partial sum of 0, the flip-flop S3 is already in the zero state, and only the partial sum of 10 remains to be considered.
EMI0018.0046
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 10 <SEP> + <SEP> 2 <SEP> = <SEP> SlS. ' <SEP> S.3 (S, LS ,; <SEP> + <SEP> S <B>, ' </B> S ,,) When an input of two units is received in Sd and Sb during period P4, the partial sums of 6 and 8 must be considered.

   But according to Table VI, a partial sum of 8 is represented by the zero state of the flip-flop <I> S3, </I> only the partial sum of 6 therefore remains to be considered. However, as noted above, the partial sum stored in the adder at the end of period P3 must be greater than or equal to 6 for an input of two units to Sa and Sb during period P4. By examining Table VII, it becomes evident that for all even values greater than 6, the flip-flop <I> IF </I> is never in zero state.

   The condition for which a two-unit input is received at S, and Sv during period P4 can therefore be written
EMI0019.0007
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 6 <SEP> + <SEP> 4 <SEP> = <SEP> Sl'S35aSF, If we combine the expressions above, the logical grid equation to bring the flip-flop <I> S3 </I> to a zero state at the end of period P4 becomes Ss [Sls. "(Sasl" + S;

  L'S ,,) + Sl'Salsf, + 5 $ '5.6 Sl,'] CP4 The fourth output binary digit of the total decimal is also read on the flip-flop <I> S3, </I> but during the period P, following. It can be seen from Table I that the only cases where the third and fourth binary digits of the even decimal sums differ from each other, correspond to decimal sums of 4, 6, 14 and 16 (the sum 14 and 16 are represented in the table by 4 and 6 respectively, with a carry-over figure as explained above).



  It can therefore be read that the flip-flop S3 must pass from state one to state zero at the end of period PZ for these decimal sums. The process used is to cause flip-flop S2 to roll back to zero at the end of period P4 when the total decimal sum is 4, 6, 14 or 16.

   The flip-flop <I> S3 </I> is then switched to the zero state at the end of the period PZ of the next addition cycle provided that the flip-flop S2 is in the zero state during this period <I> Pl. </I> By analogous reasoning and a further examination of Table I, the S2 flip-flop must be brought to state one at the end of period P4 for total decimal sums of 8 or 18, so as to ensure that the S3 flip-flop is not switched to zero at the end of the period <I> Pl. </I> Note that,

   for decimal sums of 0, 2, 10 or 12, it is irrelevant whether the flip-flop S2 is switched to state one or state zero. Taking into account the above information, the logical grid equation one for the flip-flop S2 during the period P4 will first be determined. The conditions under which the S2 flip-flop must be brought to state one are
EMI0019.0041
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)

  
 <tb> 8 <SEP> + <SEP> 0 <SEP> = <SEP> <B> SIS2 </B> <SEP> S, <SEP> S.'S ,;
 <tb> 6 <SEP> + <SEP> 2 <SEP> = <SEP> Sl'S @ S; j (S, S ,, '+ <SEP> Sa'S ,,)
 <tb> 14 <SEP> + <SEP> 4 <SEP> = <SEP> SIS21S3SaSb By eliminating the last two conditions above, because the S2 flip-flop is already one for partial sums of 6 and 14, and adding the total decimal sums of 0, 2, 10 or 12, because it is irrelevant for these sums that the flip-flop is switched to state one, we obtain the following table
EMI0019.0047
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)

  
 <tb> 0 <SEP> + <SEP> 0 <SEP> = <SEP> If <SEP> S2 ' <SEP> S3 <SEP> Sa'Sb
 <tb> 0 <SEP> + <SEP> 2 <SEP> = <SEP> Sl'S, <SEP> S.j <SEP> (Sa'Sb + <SEP> S, 1S ,, ')
 <tb> 8 <SEP> + <SEP> 0 <SEP> = <SEP> SiSS3 <SEP> S., 'S
 <tb> 8 <SEP> + <SEP> 2 <SEP> = <SEP> SlS <B> J </B> S3 <SEP> (SaS ,; <SEP> + <SEP> S; i <SEP> Sb)
 <tb> 8 <SEP> + <SEP> 4 <SEP> = <SEP> S15 <SEP> S3 <SEP> His <SEP> Sb An examination of the above conditions indicates that, for a partial decimal sum of 0 or 8, the S2 flip-flop is toggled to state one regardless of the inputs (the condition of a sum partial of 0 with two inputs to two units does not need to be considered because, as explained above,

   a partial sum of less than 6 is impossible under these conditions during period P4). From Table VII, it is evident that the partial sums of 0 and 8 are only characterized by the fact that the flip-flops S2 and S3 are both in state zero. Therefore, the logic grid equation one for flip-flop S2 at the end of period P_, becomes s. = SSCP4 The logic zero gate equation for the S2 flip-flop at the end of period P4 will now be determined.

   As indicated previously, the S2 flip-flop must be brought to zero for total decimal sums of 4, 6, 14 or 16. These conditions can be explained as follows
EMI0020.0011
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> 4 <SEP> + <SEP> 0 <SEP> = <SEP> SI'S:, S. <SEP> S ;, ' <SEP> S ,;
 <tb> 2 <SEP> + <SEP> 2 <SEP> = <SEP> If <SEP> S., 'S @ (S ,, S ,; <SEP> + <SEP> S ,, 'S, <B>) </B>
 <tb> 6 <SEP> + <SEP> 0 <SEP> = <SEP> S, 'S2S; 3S. <SEP> S ,;
 <tb> 4 <SEP> + <SEP> 2 <SEP> = <SEP> If <SEP> <B> S # </B> S3 <SEP> (S "S ,, '+ <SEP> S ,, 'S ,,)
 <tb> 14 <SEP> + <SEP> 0 <SEP> = <SEP> SIS2S2S.I <SEP> S ,;
 <tb> 12 <SEP> + <SEP> 2 <SEP> = <SEP> SIS.S ;; <SEP> (S @ S ,;

    <SEP> + <SEP> S;, 'S ,,)
 <tb> 10 <SEP> + <SEP> 4 <SEP> = <SEP> S1S -_, 'S # S "S ,,
 <tb> 14 <SEP> + <SEP> 2 <SEP> = <SEP> SIS, SJS ,, S ,; <SEP> + <SEP> S ,, 'S ,,)
 <tb> 12 <SEP> + <SEP> 4 <SEP> = <SEP> S, S @ 'S. 3% S @ Looking at this table, it becomes obvious that for partial decimal sums of 4 or 12, the S2 flip-flop will be brought to zero regardless of the weight of entries. This results from the fact that a partial sum of less than 6 cannot exist during period P4 with two-unit inputs in S, and in Sl ,, and also from the fact that, for a total decimal sum of 12, it is it does not matter whether the SZ flip-flop is switched to state zero.

    From Table VII, it is evident that the partial sums of 4 and 12 are only characterized by state one of flip-flop S2 and state zero of flip-flop S3. Consequently, the grid equation satisfying these conditions becomes (4) "s @ = S, SI CP_, Note from the above that, in the absence of input on S, z or S ,, during period P4, the flip-flop <I> S2 </I> is brought to zero for partial sums of 4, 6 and 14.

    From Table VII, we can see that state one of flip-flop S2 represents partial decimal sums of 4, 6, 12 and 14. As it is irrelevant for a total decimal sum of 12 that the flip-flop S2 is in one state or another, as discussed above, the logical grid equation satisfying this condition is
EMI0020.0029
  
    (5) <SEP> "s.

    <SEP> = <SEP> S-IS, 1 <SEP> S ,, 'CP_, If we compare the conditions in the table above for partial decimal sums of 12 or 14, we can see that the S2 flip-flop will be brought to zero for an entry of two units in SQ or <B> IF, </B> during period P4. From Table VI, we can see that the partial decimal sums of 12 and 14 are only characterized by the state one of the flip-flops <I> IF </I> and S2.

   Therefore, these conditions are satisfied by equation (6) @ s @ = S, S @ (S, S ,; = - S "S ,,) CP, Partial sums of 2 or 10 can be eliminated, because the flip-flop S2 is already in the zero state for these conditions.

      If we combine equations (4), (5) and (6) above to bring flip-flop S2 to a zero state at the end of period P4, the final equation becomes "s. = S. '[S, (S;, S ,,' + S;, 'Sh,); - S "Sh + S. ,,' jCP_, The logical equation of grid one for the flip-flop <I> IF </I> at the end of period P4 can then be considered.

   As previously indicated, the carryover, which exists for all decimal sums from 10 to 19 inclusive, will be stored in the flip-flop <I> IF </I> during the pulse <i> Pr </I> following. If we consider only even numbers, according to Table VII, the maximum even partial decimal sum during period P.t is 14.

   If we consider all the possibilities for a carryover (when the total decimal sum is between 10 to 18 included), we end up with the following: 10) a partial decimal sum 10 to 14 inclusive, and no very in <I> His </I> or in <B> <I> Sb </I> </B>; 20) a partial sum of 8 to 14 inclusive, and an entry of two units on Sa or on <B> Sb </B> but not on both; or 3) a partial sum of 6 to 14 inclusive and an entry of two units in Sd and SL. An examination of Table VII indicates that, for partial sums equal to or greater than 8, the SI flip-flop is already in state one;

    therefore, there is no need to write any logical grid equations for the first two possibilities above, only the third possibility remaining to be considered. But as we have shown above, each time that S, z and S ,, will simultaneously receive an input of two units during the period P4, the partial sum will necessarily be equal to or greater than 6, so the third condition is satisfied whenever there is an entry of two units in <I> His </I> and in <I> IF,

   </I> during period P4. So the logical grid equation to flip the flip-flop <I> IF </I> to state one becomes <B> IF </B> = S "S ,, CP4 The logical grid equation for flipping the flip-flop <I> IF </I> to state zero at the end of period P4 will now be considered.

   The possible conditions for giving a total decimal sum less than 10, that is to say when it is desired to have no carry over, are: V #) no entries and a partial decimal sum less than 10; 211) an entry of two units on Sa or on S ,, but not on both, and a partial decimal sum less than 8; or 3) a two-unit entry on S @ and on Sf, and a partial decimal sum less than 6.

   But from Table VII, we can see that the IF flip-flop is already in the zero state for partial decimal sums less than 8, which avoids taking into account the two conditions above. There is nothing more to consider than the condition corresponding to a partial sum of 8 and no entries during period P4. Therefore osl = S2 S2 S #,

  Sb "CP4 During the following period Ph the third output binary digit is read on the flip-flop S3 while, during the period P ,, the fourth output potential is read on the flip-flop S3.

   As explained in detail previously, the flip-flop S3 is brought from state one to state zero at the end of the period <I> PI </I> when the total decimal sum is such that the third and fourth binary digits are different from each other (table I), but it is never necessary to verify the passage of the state zero to state one at the end of the period <I> PI. </I> We have also explained in detail the logical equations to tip the flip-flop S2 at the end of the previous period P4,

   so as to allow the fourth output binary digit to be stored in flip-flop S3 at the end of the period <I> PI. </I> The grid equations controlling the S3 flip-flop at the end of the period <I> PI </I> are therefore s3 = 0 and 0SS = S2 CPi The flip-flop S2 becomes a binary counter stage again after the period <I> PI </I> during which the third output binary digit comes from the adder;

   and similarly, the flip-flop <I> S3 </I> becomes a counter stage again after period P., during which the fourth output binary digit comes from the adder. <I> Exit from </I> The adder We will now describe the logical equations defining the output of the adder in accordance with the coded decimal representation of Table I.

   As noted above, the corresponding weighted binary digits in the output of the adder are delayed by two periods relative to the input. As has been shown in fig. 1, the first output binary digit is output from the adder during period P3. Thus the output decimal group is highlighted during periods P3, P4, <I> PI </I> and P., respectively for components 1, 2, 4 and 2.



  Because of the particular way in which the output representing the sum is used in the calculation, it is often desirable to obtain a signal representing the logical inverse of the true signal. This is necessary so that the output signal can be fed into an amplifier before it is applied to a memory such as a rotating magnetic drum, for example. The amplifier device inverts the signal applied to it, thus giving the desired signal at its output. It is for this reason that we represent here the symbolic equation of the logical inverse of the encoded binary output signal; but we must realize that this choice is arbitrary because, if desired, the sum signal can be obtained directly.

           As explained above, the first, third and fourth output potentials, or binary digits, are read on the flip-flop S3 during the respective periods P3. <i> Pl </I> and P ,,. As it is the logical inverse of the sum that we want, it is the observation of the zero exit of the flip-flop <I> S3 </I> which determines the nature of the output logic equations.

   Therefore, the logical equation which represents the first, third and fourth components or binary digits of the output group, observed during the respective periods P1 and P, is So '= S4 P4. During period P4, the second output potential, or binary digit, is output by the adder. From Table I, a low potential will correspond to total decimal sums of 0, 1, 4, 5, 10, 11, 14 and 15.

   But since the first output potential determines whether the decimal sum is even or odd, only even decimal sums should be considered, i.e. 0, 4, 10 and 14. By tabulating the possible conditions for these decimal sums, we get the following
EMI0022.0021
  
    Sum <SEP> Enter
 <tb> decimal <SEP> (Weight <SEP> Equation Logical <SEP>
 partial <tb> <SEP> total)
 <tb> <B> 0 <SEP> + <SEP> 0 </B> <SEP> - <SEP> <B> S, 'S. =' S3'S;, 'S ,, </B>
 <tb> 4 <SEP> + <SEP> 0 <SEP> = <SEP> Sl'S.S.; 'S;,' S ,, '
 <tb> 2 <SEP> + <SEP> 2 <SEP> = <SEP> St'S "S3 (S <B> # ' </B> S ,, '+ <SEP> S ,, 'S ,,)
 <tb> 10 <SEP> + <SEP> 0 <SEP> = <SEP> Sj.S., 'S; S "' St, '
 <tb> 8 <SEP> + <SEP> 2 <SEP> = <SEP> SjS @ 'S; 3 <SEP> (S ,, S ,;

    <SEP> -T <SEP> S "'S ,,)
 <tb> 6 <SEP> + <SEP> 4 <SEP> = <SEP> S, ' <SEP> S = S3S "Sh
 <tb> 14 <SEP> + <SEP> 0 <SEP> = <SEP> SISIS3Sa ' <SEP> Sh '
 <tb> 12 <SEP> + <SEP> 2 <SEP> = <SEP> <B> Sis </B> -S3 '(S;, S ,,' + <SEP> S;, 'S ,,)
 <tb> 10 <SEP> + <SEP> 4 <SEP> = <SEP> SjS @ 'SjS;, St, From this table it is evident that the second output component is at low potential whenever there are no inputs during period P4 and that we find in the adder a partial decimal sum of 0, 4, 10 or 14.

   The logical equation representing these conditions is <B> S., = </B> S, "S ,; (Si S; 3 + SlS3) P4. Note further that, for a partial decimal sum of 8 or 12 in the counter, and an entry of two units during period P4, the second output potential is zero.

   An examination of Table VII indicates that partial decimal sums of 8 and 12 are only characterized by state one of the flip-flop. <I> IF </I> and the zero state of the flip-flop <I> S3. </I> So, the logical equation representing these conditions is S ", = SisYS:

  , Sh + Si "Sh) P4. As observed previously, the partial decimal sum must be greater than or equal to 6 for two entries of two units during the period P4. A partial decimal sum less than or equal to 6 (table VII) is characterized by the zero state of the SI flip-flop.

   Therefore, the equation satisfying this condition is S4 = St'S ,, ShP4. The conditions characterized by partial sums of 2 with an input of two units and of 10 with two inputs of two units are irreducible and must be written in their integrity, hence So '- [Si'S. "S2 (Sasb' + S #, 'Sb) + <B> IF </B> S2'S3S.Sb] P4 If we group all of the above expressions into a single equation for the four components of the output group,

   the final equation becomes
EMI0023.0009
  
     <B> S ,, '= </B> <SEP> S:; 'P4 <SEP> + <SEP> [Sash (If <SEP> + <SEP> <B> sis - ,, S. ,,) </B>
 <tb> + <SEP> <B> (Sa, sl, '+ <SEP> Sit <SEP> 'S ,,) <SEP> (Sls3 '+, Sl'S-a <SEP> S # :) </B>
 <tb> 1- <SEP> Sa'Sh (Sl'Ss <SEP> + <SEP> <B> sis.,)] <SEP> P-1. </B> Like the first part of the expression above, either S ,, # * <I> = </I> S3 <I> P4, </I> includes all cases except period P4, all subsequent expressions including S3 and P4 at the same time can be simplified by removing the restrictive term P4, since all periods are included.

   The simplified expression becomes S "= S.; 'P4 + SlSs (SISh + Sa'Sh) + Si'S .; S, / S h + [(S1' + S, S:, 'S;,) S" 5 ,, + Sl'S, 'S;, (S;, SI,' + S;, 'S1,) + S, S;

  3Sa'S1, '1P_1 Before presenting the physical circuits intended to give rise to the logical equations required by the gate inputs of the flip-flops of the counter S, the derivation of a simple equation for the gate input of each flip-flop is desirable: instead of having four control equations for each of the pulses P1, P ,, P, 3 and P4, only one equation can be written for each grid, for all four time periods.

   The present method particularly leads to this simplification as illustrated above, due to the similarity of the grid equations for the pulses P1, P, and P.3.



  If we combine the logical flip-flop grid equations <I> IF </I> during the four pulse periods, the combined grid equation becomes si = SaSbC Osi = (p4 '+ S2 S2 p4) Sa'Sh <B> C </B> However, in the expression "sl above, the expression P4 can be eliminated,

   because the conditions
EMI0023.0049
  
    tions <SEP> for <SEP> which ones <SEP> the <SEP> flip-flops <SEP> S2 <SEP> and <SEP> S3
 <tb> are <SEP> in <SEP> state <SEP> <SEP> zero <SEP> <SEP> are <SEP> included <SEP> in
 <tb> the <SEP> periods <SEP> P4 <SEP> and <SEP> have <SEP> not <SEP> need <SEP> to be <SEP> limited <SEP> to <SEP> the <SEP> period <SEP> P4.

    <SEP> The <SEP> equations <SEP> finals
 <tb> combined <SEP> of <SEP> grid <SEP> for <SEP> on <SEP> flip-flop <SEP> IF <SEP> from come
 <tb> If <SEP> = <SEP> SaSbC
 <tb> osi <SEP> = <SEP> (P4 <SEP> + S2 <SEP> S3 ') Sa'Sb " <SEP> C
 <tb> From <SEP> same, <SEP> the <SEP> equations <SEP> general Logical <SEP>
 <tb> from <SEP> grid <SEP> for <SEP> on <SEP> flip-flop <SEP> S2 <SEP> become
 <tb> s2 <SEP> = <SEP> @ <SEP> [Sl (S <B>. " </B> Sb <SEP> + <SEP> <B> S., Sb) </B> <SEP> + <SEP> <B> Sl '(S.Sb </B> <SEP> + <SEP> <B> S.'sb)] P4 </B>
 <tb> + <SEP> <B> S2 <SEP> S3 </B> <SEP> P4 @ C
 <tb> @ [Sl '(Sa'Sb <SEP> + <SEP> Sasb) <SEP> + <SEP> Sl (SaSb '+ <SEP> Sa'Sb)] P4 '
 <tb> + <SEP> S2 [If (S ,, Sl, '+ <SEP> S <B> a ' </B> Sb) <SEP>;

  - <SEP> S ,, ' <SEP> Se <SEP> -i- <SEP> S31P4 @ C As the flip-flop condition S2 is not included in any of the above expressions for periods P4 ', it is a condition that is not required for the expression for the period P4 but which, nevertheless, can be included.

   For example, the inclusion of the expression S, in the portion of the first equation covered by the. period Pi, essentially means that, if all the other expressed conditions exist during the period Pi, the flip-flop S2 will go to state one if it is in state zero, but that if all the others required conditions exist during period P4 ', the flip-flop <I> S2 </I> will not be brought to state one if it is already in state one. If we rewrite the equation in this way, it does not affect the actual results and we have done it here only to simplify the physical circuits of the logical grid networks.

    The general grid equations of flip-flop S2 can therefore be written as follows
EMI0023.0058
  
     <B> S2 </B> <SEP> - <SEP> <B> S2'l [Sl (Sa. <SEP> Sb '+ <SEP> Sasb) </B> <SEP> -! - <SEP> <B> If '(SaSh # </B>
 <tb> + <SEP> Sa, 'Sb)] P4 <SEP> + <SEP> S; 'P4ÎC
 <tb> 0S2 <SEP> = <SEP> S2 @ Sl '(S,' Sb <SEP> + <SEP> S;

  , Sb) P4 <SEP> + <SEP> [Sl (S ,, St, '
 <tb> + <SEP> SR <SEP> Sb) <SEP> + <SEP> (Sa'Sb '+. S3 <SEP>) 1P4} C
EMI0023.0059
  
    The <SEP> equations <SEP> of <SEP> flip-flop <SEP> S3 <SEP> can <SEP> be
 <tb> grouped <SEP> for <SEP> get <SEP> this <SEP> who <SEP> follows
 <tb> Ss <SEP> - <SEP> iS2 (P2 + <SEP> P3) <SEP> + <SEP> S3 '[S2 (Sa + <SEP> Sh + <SEP> If ')
 <tb> + <SEP> Sls2 <SEP> Sa'Sb <SEP> 1P4} C
 <tb> <B> OS-3 </B> <SEP> _ <SEP> @ S2'P4 <SEP> + <SEP> <B> S3 [SIS "(S ,, Sb '+ </B> <SEP> S, <SEP> S ,,)
 <tb> '+ <SEP> sl's, sb + <SEP> s2S @ 1Sb'1P4 @ C By reasoning in the same way as above, in the simplification of the equations of the flip-flop S2,

   the equations of the flip-flop S3 can be rewritten as follows s3 = S3 '{S2 (P # 2 + P3) + [S -' (Sa + Sh + SI ') -! - SIS.'S # "Sh' ] P4,} C "s 3 = S, iS #> P4 '+ [SIS .-' (S, Sh;

  - Sa'St,) + Sl, S, SI, + S., 'S,' S ,, '] P4 J C And a further simplification, applying the reasoning used to derive the flip-flop grid equations <I> IF </I> gives the expressions s; s = S, @ Ss (P #, + P3) + [S2 (S;

  i + St, + S1) + SIS; S; "Se] P_I} C # 1s? - S .- [S # / P4 / + SIS ._, 1 '(SaSh + Sa.'SI,) + S-" S; t' S ,; -f- SI'S;

  1SbP4] C While trying to obtain the physical circuits to give rise to the logical equations necessary for the gate inputs of the flip-flops of the counter S, we notice that certain combinations of terms are found repeated in several equations. If one establishes each of these combinations only once, only one derived proportion is available which can be introduced where it is needed along with other terms to solve the different equations. The logical networks intended to give rise to these combinations of terms are shown in fi-. 10.



  It has been shown and described above, in conjunction with FIG. 5, the way in which the networks are arranged to physically realize the logic products.



  The network for accomplishing the logic addition 5> will now be described in connection with the fia. 10. This network, illustrated by block 45, consists of a pair of input diodes 46 and 47, the cathodes of which are common and ra led to earth through a common resistor R ,,. The input terms to the network are introduced on the anodes of the diodes. The input conductor 50 represents the product <I> His </I> S ,, 'obtained from the output of the first product network 51, and the input conductor 52 represents the product S ,, Sb obtained from the output of the second product network 53 .

   When at least one of the input conductors of the addition logic network 45 is at a relatively high potential, the output line 54 sees its potential also rise, thus indicating the logic sum (Sd <I> Yes, ' </I> + S2Sv). Thus we can say in general that, in an addition logic network, whatever the number of inputs, the output potential is equal to the highest input potential.



  It should be understood that the inputs Sa <I> and </I> Sv are fed here through inverters 55 and 56 respectively, so as to obtain their logical inverses S, 'and S ,,' which are necessary as terms of the equations. The actual source of S, and Sv could however be obtained from the false outputs of flip-flops S2 and Si, respectively for example, if such a source were used for the incoming coded digits.



  The diode arrays provided to resolve the remaining combinations are composed of similar logic product and logic add circuits. In each case, the output line is represented by the symbolic function it represents.



  We show, on the fi '-. <B> He., </B> 12 and <B> 13, </B> logical networks to physically solve the control equations of the SI, S2 and S3 flip-flops. It will be noted that the inputs of the networks which are defined by symbolic functions represent the complex terms already obtained by the network of FIG. 10. The output of the logic network is obtained in each case by a final logical product circuit which comprises, among other possible common terms, a clock pulse.



  There is shown in FIG. 14 the logic circuit generating the logic negative of the output signal-sum S "'. If we introduce the output of the logic network S" in an inverter 68, which can be an amplifier for example, the desired signal S, can be obtained.



  This time the output is not combined with a clock pulse as it was for each of the gate equations, because the output is not used to control a flip-flop. This output signal can be introduced, for example, into a memory or be observed using an oscillograph, depending on the way in which the adder circuit adapts to the device of the computer.



   <I> Operation </I> Referring again to fig. 1, the operation of adder circuit 10 will now be described in detail when it receives the coded figures shown therein.



  The content of the adder is initially zero, that is to say that the flip-flops S1, S2 and S3 are all in the zero state >>. On receipt of the input-unit (high potential) on SG during the period <I> PI </I> of the first cycle,

   the circuits are actuated so as to cause the S2 flip-flop to reverse to state one and to allow the SI flip-flop to remain in the zero state at the end of the period <I> Pi. </I> The addition flip-flops evaluated during this time (table V) contain the partial decimal sum of 1. During period P "of the first cycle, two inputs of two units are present on S, l and Sb.

   This has the effect, at the end of the period P. ,, of controlling the flip-flop S3 to state one <B>, </B> the S2 flip-flop towards zero and the flip-flop <B> IF </B> to state one. The addition flip-flops, evaluated at this time (Table VI) thus register a partial decimal sum of 5.



  During period P3, the first output pulse of unit weight is read. At the same time, inputs of four units are present in <I> Su </I> and in Sv <I>; </I> This has the effect of controlling S3 flip-flop to state zero, S2 flip-flop to state one and SI flip-flop to state one as well.

   As can be seen in Table VII, these states of the flip-flops i.e. zero, one and one for the flip-flops S3, S2 and SI respectively, represent a partial decimal sum of 12 in the adder evaluated during the pe period P4.



  During period P, 4, coded digit components of weight equal to two units are received again. As can be seen in fig. <I> 1, </I> Sd is the only one received at this time. Note that the entries during period P4 are never recorded as accounts in the adder. At this time, since all components of the arriving digits have been observed, all remaining components of the outgoing digit can be determined.



  Thus, by noting the observed total count, the following operations are carried out during the period P4: 10) The existence of the second component of the output, of weight 2, is determined and provided; 20) the existence of the third component of the exit, of weight 4, is determined and stored in the flip-flop <I> S3 </I> at the end of this time; 3o) the information determining the nature of the fourth output pulse, of weight 2, is stored in the flip-flop S2;

   and 40) the decimal carry for total decimal sums from 10 to 19 inclusive, of the first addition cycle is saved at the end of this time in the flip-flop <B> IF. </B>



  In the example in question, during period P4, the content of adder 12 (Table VII), plus the input-unit read during period P3, with the observed input Sd of weight 2, gives a decimal sum total of 15. This means that a coded binary number (Table I) equivalent to decimal 5 must be supplied and that a decimal carry must be added to the following digits on arrival.



  As can be seen from Table I, the second component of the outgoing coded digit representing 5 is absent. Consequently, following the logic output network already described, a low potential is delivered by the adder during period P4. The third component of weight 4 is present in the output. The flip-flop S3 therefore switches to a>. Finally, the fourth output potential, also of weight 2, is found to be absent. Since, as explained previously, the fourth exit potential is also read on the flip-flop <I> S3, </I> this must be brought from one to zero at the end of the period <I> PI </I> following.

    This information is stored at this time in the flip-flop. <I> S2 </I>; therefore, the flip-flop S2 is controlled to the zero state at the end of the period P4. During the PI period of the next cycle of operation, the third output component, of weight 4, is read on the flip-flop <I> S3. </I> At the end of the period Ph the flip-flop S3 is commanded to state zero <B> </B> due to the zero-> y state of the S2 flip-flop.

   The fourth output component, which in this case corresponds to a low potential, is delivered by the flip-flop S3 during the following pulse P2. The flip-flops S1 and S2, having fulfilled their function of storage units of the previous cycle, are again used, as counters, at the end of the period P1. The flip-flop S3, having provided the fourth output component during the period P2, is used as a counter,

   in association with flip-flops <I> IF </I> and <I> S2 </I> at the end of period P2. This completes a cycle of the adding circuit, illustrating how the first binary coded decimal input digit 8 received at Sd, added to the first binary coded decimal input digit 7 received at Sb, provides the first output digit. decimal encoded in binary S.

    The following binary coded decimal input digits 6 and 2 received in SQ and Sv respectively, together with the decimal carry resulting from the previous addition cycle, allow the adder to deliver the second output digit decimal 9 encoded in binary.

 

Claims (1)

CLAIM Serial digital electronic adder device intended to add curves of binary coded numbers, each coded whole number taken from said numbers being expressed in the form of a sequence of four binary digits, a predefined weighted value being assigned to each digit depending on its position in the sequence, the device comprising a source of synchronization signals continuously producing a recurrent cycle of four synchronization signals, said device being characterized by a first, a second and a third bistable element <I> (SI, S2, S3) </I> arranged so as to constitute a binary digital register, and by a logic network (11) intended to receive said synchronization signals <I> (PI, P2, P3 </I> and P4) and provided with input lines <I> (Sa, Sb) </I> designed to simultaneously receive a sequence of four binary signals indicating corresponding integers (8 and 7) taken from the coded numbers, each binary signal being synchronized with a signal for synchronizing said cycle, said network comprising a first, a second, a third and a fourth group of logic circuits, the first group of circuits ( included in fig. 11, 12 and 13) responding to the first three weighted binary signals of the corresponding integers, so as to produce output signals (S1,, S1, oS2, S @; , @, S # _) <I> a </I> the end of each of the first three periods of the synchronization signals <I> (Pl, P2, P3), </I> the output signals causing the recording ment, by the binary digital register, in true binary form, of the sum of the first three weighted binary digits, the second group of logic circuits (included in fig. 14) responding to an output signal from the bistable device (S3) which stores the lowest order true binary digit during the period of the third synchronization signal (P3) so as to produce on an output line (So) emanating from the logic network (11) the first weighted binary output digit of the sum, the third group of logic circuits (included in fig. 14) responding to output signals emanating from the bistable <B> <I> (SI, </ I> </B> <I> S2, S3) </I> which indicate the partial sum stored therein during the period of the fourth synchronization signal (P4) and to input signals indicating the fourth digits binary pon derives, so as to produce the second weighted binary output digit of the sum on said output line (S,) and the fourth group of logic circuits (included in Figs. 11, 12, 13 and 14) responsive to signals indicating the partial sum stored in the digital binary register during the period of the fourth synchronization signal (P4) and to input signals indicating the weighted fourth binary digits, so in producing output signals causing the recording by the second and the third bistable device <I> (S2, S3) </I> of the fourth and third weighted binary digits, respectively, of the sum in question and causing the 'recording by the first bistable organ <I> (SI) </I> any carry resulting from the addition of the corresponding integers and responding to output signals from the register during the first and second <I> (Pl, P2) </I> period of the cycle synchronization signals, so as to produce the third and fourth weighted binary digits of the sum on the output line <I> (S.). </I> SUB-CLAIM Serial digital electronic adder conforming to the claim, characterized in that the first group of logic circuits (included in fig. 11, 12 and 13) and the three bistable members <I> (SI, S2, S3) </I> are interconnected such that the output signals produced by the first group of logic circuits at the end of the first period of the synchronization signals <I> (PI) </I> in response to the signals indicating the first weighted binary digits cause the recording, by the first bistable organ <I> (SI), </I> of a true binary number of order 21 and the recording by the second bistable organ (S2) a true binary digit of order 2 ", the output signals produced by the first group of logic circuits at the end of the second period of the synchronization signals, in response to signals indicating the second binary digit pon deré, causing the recording, by the third bistable organ <I> (S3), </I> of a true binary digit of the sum, of order 20 and l 'recording, by the second bistable member (S2), of a binary digit of order 21 and recording by the first bistable member (SI), of a binary digit of order 22 and the output signals produced by the first group of logic circuits at the end of the third period of the synchronization signals, in <B> - </B> response to signals indicating the third weighted binary digit, causing the recording, by the third bistable member <I> (S3), </I> of a true binary digit of order 21, the recording, by the second bistable organ (S2), of a true binary digit of order 22 and the recording, by the first bistable organ (SI), of a true binary digit of order 23 , the device being further characterized in that the second and the third bistable member (S2, S3) are mounted as a transfer register at the end of the fourth synchronization period, the third and fourth weighted binary digits res of the sum , stored respectively in the third and the second member, being applied to the fourth group of logic circuits (included in fig. 11, 12, 13 and 14), from the third device <I> (S3), </I> during the first and second synchronization periods <I> (Pl, P2) </I> of the following cycle.