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CA984523A - Process for the formation of self-aligned silicon and aluminum gates - Google Patents

Process for the formation of self-aligned silicon and aluminum gates

Info

Publication number
CA984523A
CA984523A CA171,132A CA171132A CA984523A CA 984523 A CA984523 A CA 984523A CA 171132 A CA171132 A CA 171132A CA 984523 A CA984523 A CA 984523A
Authority
CA
Canada
Prior art keywords
self
formation
aligned silicon
aluminum gates
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA171,132A
Other languages
English (en)
Other versions
CA171132S (en
Inventor
Dominic P. Spampinato
Robert H. Dennard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA984523A publication Critical patent/CA984523A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0198Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
CA171,132A 1972-06-30 1973-05-08 Process for the formation of self-aligned silicon and aluminum gates Expired CA984523A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00267879A US3834959A (en) 1972-06-30 1972-06-30 Process for the formation of selfaligned silicon and aluminum gates

Publications (1)

Publication Number Publication Date
CA984523A true CA984523A (en) 1976-02-24

Family

ID=23020517

Family Applications (1)

Application Number Title Priority Date Filing Date
CA171,132A Expired CA984523A (en) 1972-06-30 1973-05-08 Process for the formation of self-aligned silicon and aluminum gates

Country Status (7)

Country Link
US (1) US3834959A (ja)
JP (1) JPS543599B2 (ja)
CA (1) CA984523A (ja)
DE (1) DE2331393C2 (ja)
FR (1) FR2191274A1 (ja)
GB (1) GB1418231A (ja)
IT (1) IT987430B (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147226A (en) * 1975-06-13 1976-12-17 Nec Corp Semiconductor memory device
US4075045A (en) * 1976-02-09 1978-02-21 International Business Machines Corporation Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
US4827448A (en) * 1976-09-13 1989-05-02 Texas Instruments Incorporated Random access memory cell with implanted capacitor region
US4182636A (en) * 1978-06-30 1980-01-08 International Business Machines Corporation Method of fabricating self-aligned contact vias
US4238275A (en) * 1978-12-29 1980-12-09 International Business Machines Corporation Pyrocatechol-amine-water solution for the determination of defects
JPS5660052A (en) * 1980-10-20 1981-05-23 Toshiba Corp Semiconductor memory device
JPH0630355B2 (ja) * 1983-05-16 1994-04-20 ソニー株式会社 半導体装置
JPH0618263B2 (ja) * 1984-02-23 1994-03-09 日本電気株式会社 電荷転送素子
JP2642523B2 (ja) * 1991-03-19 1997-08-20 株式会社東芝 電荷結合素子を持つ半導体集積回路装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2050320A1 (de) * 1970-10-13 1972-04-20 Siemens Ag Halbleiteranordnung

Also Published As

Publication number Publication date
GB1418231A (en) 1975-12-17
DE2331393C2 (de) 1984-08-09
FR2191274A1 (ja) 1974-02-01
DE2331393A1 (de) 1974-01-17
US3834959A (en) 1974-09-10
JPS543599B2 (ja) 1979-02-24
JPS4964382A (ja) 1974-06-21
IT987430B (it) 1975-02-20

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