CA2383750A1 - Virtual addressing buffer circuit - Google Patents
Virtual addressing buffer circuit Download PDFInfo
- Publication number
- CA2383750A1 CA2383750A1 CA002383750A CA2383750A CA2383750A1 CA 2383750 A1 CA2383750 A1 CA 2383750A1 CA 002383750 A CA002383750 A CA 002383750A CA 2383750 A CA2383750 A CA 2383750A CA 2383750 A1 CA2383750 A1 CA 2383750A1
- Authority
- CA
- Canada
- Prior art keywords
- address
- virtual addressing
- output
- addressing buffer
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A virtual addressing buffer circuit has improved address mapping and control flexibility for improved physical resource management and a unique opportunity for forward-compatible system design. The virtual addressing buffer formats the output address utilizing a format register as a combination of the new address bits and the original input address bits. The ability to format the output address enables the user to replace certain address bits without requiring that the entire address be replaced. The virtual addressing buffer controls the output of several command signals to external circuits to indicate how the system should respond to the address output from the virtual addressing server. The command signals are controlled by a command register and are output from the virtual addressing buffer only when an address match has been verified. The virtual addressing buffer circuit filters out certain bits of an input address as indicated by a filter register before it verifies that the input address matches a stored address.
The bit pattern in the filtering register is not fixed, so any bit location in the input address can be filtered out before the address is verified. Once an address match has been detected, the virtual addressing buffer replaces the entire input address with a new formatted address.
The bit pattern in the filtering register is not fixed, so any bit location in the input address can be filtered out before the address is verified. Once an address match has been detected, the virtual addressing buffer replaces the entire input address with a new formatted address.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/132,643 US5526503A (en) | 1993-10-06 | 1993-10-06 | Virtual addressing buffer circuit |
| US08/132643 | 1993-10-06 | ||
| CA002168335A CA2168335C (en) | 1993-10-06 | 1994-10-04 | Virtual addressing buffer circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002168335A Division CA2168335C (en) | 1993-10-06 | 1994-10-04 | Virtual addressing buffer circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2383750A1 true CA2383750A1 (en) | 1995-04-13 |
| CA2383750C CA2383750C (en) | 2003-07-01 |
Family
ID=25678318
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002383750A Expired - Fee Related CA2383750C (en) | 1993-10-06 | 1994-10-04 | Virtual addressing buffer circuit |
| CA002383747A Expired - Fee Related CA2383747C (en) | 1993-10-06 | 1994-10-04 | Virtual addressing buffer circuit |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002383747A Expired - Fee Related CA2383747C (en) | 1993-10-06 | 1994-10-04 | Virtual addressing buffer circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (2) | CA2383750C (en) |
-
1994
- 1994-10-04 CA CA002383750A patent/CA2383750C/en not_active Expired - Fee Related
- 1994-10-04 CA CA002383747A patent/CA2383747C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2383747A1 (en) | 1995-04-13 |
| CA2383750C (en) | 2003-07-01 |
| CA2383747C (en) | 2004-09-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20131004 |