CA2234855C - Highly stable frequency synthesizer loop with feedforward - Google Patents

Abstract

A frequency synthesizer loop (200) includes a first voltage controlled oscillato r (201) and a first divider circuit (202) for dividing a frequency of an output signal generated by the first voltage controlled oscillat or (201) by a factor of N. The synthesizer loop (200) further includes a phase/frequency detector circuit (203), a loop filter circuit (204), a summing circuit (206), a feedforward amplifier (205), a second voltage controlled oscillator (207), and a second divider circuit (208), wherein the second divider circuit (208) divides a second output signal generated by the second voltage controlled oscillator (207) by a factor o f M, and a microprocessor (210) varies the value of M to keep the first voltage in the middle of a range of the second voltage controlled oscillator (207).

Description

WO 9'7/20398 PC~T~JJS96~18214 EIGHLY STA~LE 1F R}3 Qu~c~ S~F.~7,T~ LOOP WL1~ FEEDFORWARD

~1~.T T~ OF ~ TION
The present invention relates generally to the field of voltage controlled os~ tr-r design and more p~r~ rly to a highly stable frequency synthP-~i7pr loop for such oscill~tor~
providing a highly stable tuning window and a high mo~ tion bandwidth using phase locked techniques. The present invention further relates to a highly stable srth~si7P,r loop for use in s:~tollit~ and land-based microwave ~iv~ tuners and clock l~CO~ r circuits.
R~(~K~RouNn OF TR~ T~VRI~TION
A typical block ~ ~m for one t~pe of known ~tf~.lli~ QPSK l~cei~ 101 is shown in Figure 1. The ;..~....;.~, QPSK carrier is in the 95~1450 MHZ range of L~u~n~ir-s The tuner employs a syntheci7PJ1 local oseill~tQr (LO) 102 and mixer 103 t~ select the desired channel and ~n~lu~ a first int~rm~ te fi~uc,lcy ~IF) of 810 MHZ. The signal ce~ d at 810 MHZ is filtered by filter 104 and mi~ced with an 880 MHZ LO 105 in mi~cer 106 to produce the final I~ of 70 MHZ. The final EF signal is filtered by filter 107 and ~en demodulated with a qn~dr~tllre demodulator ~shown as 108, 109, 110, 111, and 112). The demodulated in-phase, I, and quadrature, Q, signals are used by the carrier recovery phase detector circuit 113 to de~ ine the phase error be~ween the 70 MHZ LO and the inCQIninp 70 MHZ IF signal. The phase error is ~ ed by the loop filter 114 and sent to the control input of the 880 MHZ voltage controlled os~ tor (vco) 105. The fee~b~ck signal pushes the system toward a locked con-lition where the phase error is zero. The carner recovery phase detector 113 can be a standard 4-phase Costas Loop type detector.
The system shown in Figure 1 suf~ers from the following problem. The 880 MHZ
VCO 105 has conflicting constraints on its design. In applif~tion~ where the bandwidth occupied by the carrier is only a fraction of that of a $~tP-llit~- transponder, it is dP~ hle to ~m~t ~e tun~ng range of the VCO 105. Timiting the tuning range helps prevent problems with the Costas ~oop false locldng on the correct carrier or locking on the wrong carrier. The tuning range needs to be large enough, however, to cc "l~lsa~ for drifts in the i~lco~ g carrier frequency. For ~y~mple, a low noise block down converter (not shown) used to convert the i.~ ..n~ s~gnal to an L-Band frequency may exhi~~t a drift of several MHZ with To operate err~ ly, the 880 MHZ VCO lOS ~n Figure 1 l~ui~S a tuning range of i:2.5 M~;. If this S MHZ tuning window ~s to remain c.~ at 880 MHZ with only a S00 k~ dri~t, then a V(~O with a stability of about 0.05% or around S00 parts per million ~ppm) is required. This level of stability is ~iM~ if not ;"~ .t)1e, to achieve over the ~ui tem~t~-re range with a v~ ;lol-tuned LC oscill~tor~
Offier Ap~ AI;.~n~ of VCOs have similar ~ui~ ;. For eY~mpl~, Figure 4 shows a known configuration of a phase locked loop clock recove~y circuit. The phase of ~e g data is co~ d to the phase of a voltage controlled crystal os~ t -r (VCXO, 404) WO 97/20398 PC~JS96~8214 with a specially ~ie~ign~l clock recovery phase detector, 402. The de-tect~ phase di~ eilce is sent to the clock recovery loop filtOE, 403, which i~.l~"~ 5 the phase dirr~ ce. The output of the loop f;lter is then used tO adJust the frequency OI the VCXO, 404 to cause it to match the phase and frequency of the incoming data. This system has limited app~ tin~ because it is only capable of recovering a clock over a narrow range of bit rates. If a different bit rate is desired, a VCXO m~t~h~d to the new rate must be used.
Other known configurations for phase locked loops include those described in U.S.
Pa~ent No. 4,743,867 d~o~s~rihing cc~ pe~ n ci~uilly for dual port phase-locked loops; U.S.
Patent No. 4,755,774 describing a two-port synthP-~i7~r mocl~ ti-m system employing an improved reference phase modulator; and U.S. Patent No. 5,109,531 describing a ~ b~n~
c~ivel with pilot lock. However, none of these phase locked loop OELL) circuits address the stability problem as described above with reference to Figures 1 and 4.
IMARY OP l'~ ~;, rNVF,~ION
T,he highly stable frequency :iy~ e~ r loop according to the present invention ~JV~ leS the stability problem ~ ~ l~' ;f-"'f'd by the known voltage controlled os~ tor (VCO) techniques and is utilized to sPhili7p- the output of a VCO. The f,~que.~i,y synthp~i7~r loop accor&g to the present invention allows for a tightly controlled tuning range and a wide i. ..,J. ,1,.~ ldw;~ . The ~u~;y ~ loop acco~ g to the present invention has app!i~ u~c in co~ ;t-~ nc ~ r~ such as ~t~11itç and land-based micluw~v~
tuners and clock recovery circuits.
The L~u~l~;y sy~ p~c;~r loop accoldLIg to the present invention achieves high stability by phase 1n~ ing a VCO to a highly stable voltage controlled crystal os~ tor. The total tuning range is controlled nu...~ lly by 1imiting the divider values in the L~u~ y WO 97no398 PCT/US96/18214 synthP.~i7P.r PLL. A high mo~ til~n bandwidth for the synth~-~i7f~l1 output of the VCO is achieved by the use of feedrolwa~d.
One frequency syntht~-~i7P.~ loop according to the present invention inc1udes a first voltage controlled osr-ill~tor for receiving a first voltage; a first divider circuit coupled to an output of the first voltage controlled osc-ill~tor for dividing the frequency of a first output signal g~u~ by the first voltage controlled oscill~tor by a factor of N; a phase/frequency detector circuit having a first input coupled to an output of the first divider circuit; a loop filter circuit coupled to an output of the phase/r.c.~uellcy detector circuit; a Ç~lr~lw~ mr1ifi~q.r for receiving and alllpli~ying the first voltage; a s--mming circuit having a first input coupled to an output of the loop filter circuit and a second input coupled to the output of the feelÇolw~d ~mrlifi~.r; a second voltage controlled oscill~tor having an input coupled to an output of the s....~ g circuit, wherein the second voltage controlled oscill~tor gt ~e~ s a second output signal in l~s~onse to a second voltage ~,e~ d by the ~ g circuit; and a second divider circuit having an input coupled to an output of the second voltage controlled o.sr.ill~t r, wherein the second divider circuit divides a rl~u~::n~;y of the second output signal t~ by the second voltage controlled ~sc~ tt)r by a factor of M and has an output col3I~lecl to a second input of the phaselL~u~,lcr d~lor circuit.
The srthp~i7p-r loop acconlin~, to the present "l~ltion may fu~er include a microplvc~or for varying the value M in ~ ~, to the first vol~ge, such ~at ~e ll~i~opl~r varies the value of M to keep the first voltage in the middle of a range of ~e first voltage controlled osr~ tor~
A l~ ,r accor~ g to the present invention incl~ldP~ a first local osç~ tor for ge~ g a first output signal; a first mixer circuit for mi~cing a l~ived signal with the first WO 97/20398 PCT~US96/1~J214 output signal to produce a first il-t~ . frequency signal; a first filter for filtP,ring the first int~.rm~AiAt~. L~uellcy signal; a second mixer circuit for mixing an output of the first filter r with an output from a first voltage cont~olled ost~ t~)r to produce a second i.~t~.. ~A;A~
frequency signal; a second filter for filterin~ the second in~ iA1~ frequency signal; a .m~ll1At~r circuit for de-m~lllAting the second int~.rm~iAt~. frequency signal; a carrier phase recovery circuit coupled to the demodulator circuit for deler,l,~u,lg phase e,rror b~;lw~n the output of a second local osc,illAtor and the second intern t~AiAte frequency signal; a first loop filter for gerl~.r~ting a first voltage r~prrsellt;i-g the integrated phase error dele~ l~ by the carrier phase ~ecovel~ circuit; a second voltage controlled os~il1Ator for receiving the first voltage and gçn~.. A~ g a second output signal in les~ se to the first voltage; a first divider circuit coupled to an output of the first voltage cont,rolled oscillAtQr for dividing a frequency of a second output signal gellk~A~A by the second voltage controlled os~ tnr ~y a factor of N; a phaselfi~uellcy cl~lcclor circuit having a first input coupled to an output of the first divider circuit; a second loop filter circuit coupled to an output of the phase/rl~u~,ncy de~t~r circuit; a re~lÇulwa~d ~mplifi~,~ for receiving and ~,.~)liryi"g the first voltage; a ;,~ g circuit having a first input col~rW to an output of the second loop filter cirwlit and a second input ~ ,,1~ to the output of the ree~lîulw;l~.l Amplifi~.r; the first voltage controlled oscill~tor having an input co"p~ to an output of the ~ -;..g circuit, the first voltage c Qntrnll~
o~ill~t ~r g~ner?/ting a second output signal in r~rQn~ to a second voltage gr~ d by ~e .~.. ;.~, circuit; and a second divider circuit h~ving an input cu~ d to an output of ~e first voltage controlled osc;llAtor, the second divider circuit dividing ~e Ç ~ucn~ of the second output signal g~ F..Y~I~ by the first voltage controlled os~-illA~r by a factor of M and having an output coupled to a second input of ~e phaselL~uency detector circuit.

A clock recovery circuit acco,dhlg to the present invention in~ludes a first ph~se detector for receiving a data input; a loop filter coupled to an output of said first phase ~eSP~tQr producing a first voltage; a first voltage controlled crystal oscill~tor coupled to an output of said loop f~ter for providing a variable frequency reference; and a synthP-~i7~Pr loop. The synthe~i7~r loop include~ a first divider circuit for dividing the output frequency of the first voltage controlled crystal oscm~t< r by a factor of N, a second voltage controlled os~ tl~r~
a second divider circuit coupled to the first voltage controlled oscillator for dividing the output frequency of the second voltage controlled os~ tor by a factor of M, a phase/frequency detector circuit for co~ g the phase of outputs from the first and second divider circuits, thereby d~ a phase error, a loop filter for i~ g the phase error; and a ~....r..;.lg circuit which has as its first input the output of the loop filter. The clock recovery circuit further in~hldes a feed~,w~ud ~mrlifit~r which has as its input the first voltage, wl~el'~ihl the output of the feelrulwtud ~mplifi~r is conn~t~d to the second input of the ~....-..~;..g circuit.
The output of the ~ circuit produces a second voltage which provides an input to the second voltage controlled os~ torl thereby reductng the phase error in the srth~i7Pr loop.
The clock recovery circuit further in~ de,s a ~ird divider circuit coupled to the second voltage controlled osr~ t~r for dividing the output Çl~uency of the second voltage controlled os~ r by a f~ctor of A, ~ the output of the ~ird divider is co~ ' to a second input of the first phase ~let~ctor~ The r~c ~d clock signal is present at the output of the ~ird divider circuit. The clock recovery circuit may also include a mi.;.uplocc~sor for varying the divider values M, N and A.
The r~) ~ gûing and other ~lul~s, S~)ect~:~ and advantages of the present invention will become more a~ from the following det~il~l description when read in conJunction with WO 97/20398 PCT/IJS9~18214 the acco~ )anying drawings.
P~RTFF nP'~C~TPllON OF T~, nRAW~(~S
Figure 1 provides a block Ai~gr~m of a known PLL circuit.
Figure 2 prcvides a block .l;i.~ . of an embodiment of the synth~o~si7~-r loop according to the present invention.
Figure 3 provides a block rli~gr~m of a receaver in which the s~ llP.~ loop accoldil~g to the present invention is ~Itili7~
Figure 4 provides a block t~i~gt~m of a known phase locked loop clock recovery circuit.
Figure 5 provides a block diagram of a phase locked loop clock recovery circuit aocording to the present invention.
nRTArr~F~n nF~;:CRTPTION
The frequency syntht-~i7P.r loop circuit according to the present invention will be des~i~ed with reference to an 880 MHZ center frequency os~ tnr~ The voltage controlled os ~ilhtf r (VC~O) has a tuning range of ~2.5 MHZ with a L ~ue~ stability on the order of 50 parts per million ~ppm). However, the ~I~UGIICY synthP~i7Pr loop circuit acco~lh g to the present invention is not limited to this appli~tion and may be used in l U~llGlUUS types of circuits.
Wlth ~ ~ to Figure 2, one embo~limt~nt of the synth.o-~i7~r loop 2()0 accol lu~g to the present invention in~ dP~ a voltage controlled crystal osr-~ tor (VCXO) 201, a divider circuit 202; a phase/L~uGIlcy- ~let~tor 203; and a loop filter 204. VCXO 201 is a variable frequency voltage con~olled crystal ûscill~tQr that provides a co~ lly variable (i.e., not fixed or stepped) L~uency reference output. As a result, the m~ tion bandwidth of the synthP~i7f~r controlled VCO iS ~t~n-l~ down to DC (0 H~).
VCXO 201 receives an input Vc,~. V,~ ~ sen~s the i..~ t~ phase dirr~.~ce b~Lw~l the received signal and the output from a local osc~ tor, for eY~mrlP-, oscill~tQr 310 in Figure 3. The output of VCXO 201 is input into N-divider circuit 202. The output from N-divider circuit 202 is coupled to a first input of phasetfrequency detector circuit 203. The output of phase/fre~quency det~ctor circuit 203 is input into loop filter 204. The output from the loop filter 204 is coupled to a first input of a ~u~ g circuit 206. A ree~lrul~d ~mI~lifi~.r 205 is coupled across the voltage controlled crystal oscill~t~r 201, the phasetfrequency det~tc?r 202 and the loop filter 203. Vc.,,~ is input into the feedr,~
amplifier 205, and the output of feelr~,.vv~ mp!i~1~.r 205 is provided to a second input of summing circuit 206. Sl-mming circuit 206 adds the outputs from the loop filter 204 and provides the Summe~ output to the input of a voltage controlled os~ tl~r (VCO) 207, such as the 880 MHZ VCO shown in Figure 2. The output from the s~ g circuit 206 to the VCO 207 provides a control signal Vc for adjusting the output of the VCO 207. The output ~ ,0 from the VCO 207 is provided to an M-divider circuit 208 which divides the frequency by a factor of M and provides the divided fi~_lcy to a second input of phase/rl~uency de~r 203. The phase/rl~ue~l~;y dele.;~or 203 co.npa.cs the inputs from divider circuit 208 and divider circuit 202, and the loop filter 204 ;~ r.~ ~ the cQn~ o~ results into a v ,oltage signal. A mic~ or 210 receives the Vc~ input via an analog-t~digital converter 211 and controls the value M of the divider circuit 208.
The operation of the sy~ p~ loop 200 of ~igure 2 will now be described. The synth.o-~i7~,r loop causes ~e frequency of the VCO 207 to be equal to M/N times the Lc~u~l ~
of the VCXO 201. The VCXO 201 has a tightly controlled nominal frequency and a small WO 97/20398 PCT/US96~18214 tuning range. In co~ the VCO 207 has a more loosely controlled nominal frequency and a relatively large tuning range. By using a synthp-~i7pr loop, the n->min~l frequency of the VCO 207 is tightly controlled. It is set by the ~cur~y of the VCXO 201. By ~lsing the VCXO 201 as the reference to the synthç~i7P-r, the ou~ut frequency may be co~t-nllously varied by varying the VCXO frequency. In many app~ tiorl~ such as the carrier recovery loop of ~igure 3 and ~e clock recovery loop of Figure S; the frequency response from tuning voltage, Vc,~r in Figure 2 and Vc~ in Figure 5, to the VCO frequency must extend from DC
(O Hz) to a frequency higher than t-h-e synthP-~i7P~r loop bandwidth. The use of ~eelrolw~d ac~o~lu~g to the present invention extends the high frequency tuning response. The use of the VCXO 201 as a reference (variable frequency reference) according to the present invention provides ~e nP~c~ r DC and low frequency response.
Thus, a ;,~ . with a variable frequency reference and feelr,l~;~d is employed to achieve a modulation bandwidth whose low frequency r~yollse eYtPr~ls to DC and whose high rlc~luel cy resyonse is not limited by the synthPsi7p~r loop bandwidth.
The system of Figure 2 achieves a wide tuning range wi~ the variable reference L~uel~ synthP~i7Pr. Wiffi M and N in Figure 2 held coll:,~L, the VCO frequency, c~V~,O, has a very small tuning range. In order to extend the tuning range, the tuning voltage, V~, iS ~ iti7~ and mo~ ul~d with a lllic;lupro~s,oL 210. If V~"r ~s close to its limits, the n~i~lulJlu~l 210 will re-adjust M and N to cause V0~ to move closer to its no~nin~l value.
This lC-lL~il~ that the tuning range of the VCXO 201 be greater than (N*~VCo)/(M*(M+ ~)).
This re~ on~hir~ is ~ for ~he VCXO to have s~-ffio~ient range to overlap each step of M. The tuning range may be tightly controlled by limiting the pe~ ihle ranges for M and N.

Otherwise stated, in the synthe-si7P.r loop circuit of Figure 2, a divided down version of the VCO 207 is phase lock~d to a highly stable reference (VCXO 2013 to produce a variable high ~equency os~ ht~r with good frequency stability. This produces an oscil1~tor having a set of discrete output frequencies to which it can tune. The use of a VCXO 201 as the ~ ce oscill~t -r enables the VCO 207 to ~enP.r~t~ a continuously varia'ole output frequency ~ In order to achieve a wide tuning range, the control voltage V,~,r is ~ iti7~d by analog-t~digital converter 211 and lllonil~led by microprocessor 210 which adjusts the VCO divider value M to keep V,~" in the middle of its range. The tuning range is then limited by progr~mming the microprocessor 210 to limit the range of values for M. By choosing a frequency step size for the synthP-~i7Pr loop that is smaller than the pulling range of the VCXO
201, there will not be any gaps in the tuning range of the system.
In order to insure that the caIrier recovery phase locked loop will not ~ ; cycle slips when the synth~-~i7P-r divider value M is changed, the ~y~llhp;~;7p~r loop bandwidth must be set much lower than the bandwidth of the carrier recovery loop. As a result, the ~y~
loop responds slowly to c~ n~s in M, and the carrier recovery loop is able ~o track out any .I; ~hl.lJ~ Y5 caused by t~e change in M. When the dynamics of the carrier ~ loop are inf~i, it is a~a~ ~t that the ~n~fer function from Vc"r to the VCO ou~put î~u~lcy~
~" 0, appe~ in ~e open loop l~onse of the carrier recovery loop. If ~e syr ll.f : r r loop 200 is ~ ,'-~Pntel without a Ç~lro,w~ path, for PY~mrle, through feedforward ~mplifi~r 205, then the transfer function ~,~,O(s)/V,~(s) will be low pass in nature and will cause in~t~hili~y in the carrier lCOOV~ loop.
The synthPCi7pr loop 200 shown in Figure 2 uses a feedrolwar~ path to allow high frequency signals from the carrier l~CO~ y loop filter to be p~sel t~d direc~dy to the 880 MHZ

VCO. By cc,~ ly choosing ~e gain of the feedfonvard path, the ~dnsrer function ~O(s)/V~,r(s) remains co~ t well past the bandwidth of the carrier recovery loop. This approach aUows the synthPci7Pr to respond slowly to changes in M while responding quickly to changes in V~.rr.
Figure 3 provides a block diag~am of a receiver 301 in~ ing the ~requency synthP-ci7P-r loop accor~ , to the present invention. The syntheci7pr loop and VCO may replace the local oscillator (LO) in the tuner of a receiver such as the q~ r~t~lre phase shift keyed (QPSK) receiver shown in Figure 1.
The ,~cei~ in Figure 3 int.l~ s a VCO circuit and a loop circuit. The VCO circuit in(~ ps a local oscil1~tc)r (LO) 302, a voltage controlled crystal osc.ill~tor 315, a first mixer circuit 303, a first filter 304, a second m~xer circuit mixer 306, a second filter 307, a demodulator circuit 308-312, a carrier recovery phase detPctor circuit 313 and a carrier recovery loop filter 314. The operation of these elemPntc is described above with reference with Figure 1.
The loop circuit in Figure 3 in~ les a voltage controlled oscil1~t~r 320, a reedÇ~
plil~P,. 321, two divider circuits 316 and 322-, a phase/frequency ~le,testc-r circuit 317, a loop filter 318, and a s~ circuit 319. The divider circuit 320, phase/rl~u~.~ ~let~,tor eircuit 317, and the loop filter 318 comrrice a phase locked loop. The loop circuit of Figure 3 also ;~ 1es a mic~ ~ssor 325 which is responsive to the output voltage of ffie voltage controlled oscill~tnr eircuit via an A/D converter 326 and cont,rols the divider circuit 322 within the phase locked loop.
The op~r~tion of the elP.m~.nt.c of the loop circuit is ~le,scriherl a~ove with reference to Figure 2. T~e ~eceiver circuit res--ltin~ from the combination of the VCO cirGuit and the loop circuit as shown in Pigure 3 has a tightly controlled tuning range and a wide tuning bandwidth desired for various receiver app1~ tionc.
The synthe.ci7P,r loop employing fee~rolwdld in Figure 2 has other applir~ti~n~ in the design of a colnml~n;~tionc receiver. If a single conversion tuner is used, the synth~o-c;7~1 LO
in the tuner may have the configuration shown in Figure 2. The synth--,ci7~,r divide ratio is chosen to tune to the desired carrier, and the demodulator tunes the VCXO to achieve phase lock.
Another important function ,~ui.ed in a digital receiver is a clock recovery circuit.
This circuit is used to regenerate a clock that is phase-locked to the demod~ t~d data. The synth~-ci7P,r loop with r~elrc,lw~d according to the present invention can be used as the clock in a multiple rate clock recovery circuit. The divide ratio is sel~t~d to provide the nominal clock frequency. The clock recovery loop filter then provides a control signal input to the syntht~ci7~.r loop.
One configuration of a clock recovery eircuit according to the present invention is sho~-vn in Figure 5. Figure 5 shows a variable bit rate cloek recovery cireuit inrhl~lin~ a clock vCl~ phase cl~r, 502 and clock reeovery loop filter. A VCXO 504 acts as a variable Ll~u~~ ,f~ce to a ~.~ loop. The ~y~lhe~;~4~ loop incllldto-s a divider circuit 505 wh~eh divides ~e L~ue~ ;y of ~e VCXO by an integer N; a divider circuit 512 which divides the frequency of a VCO 510 by an integer M; a phase/r~ u~l~ey ~let~ctor 506 ~at COlllp~5 the phase of the output of the two dividers 505 and 512; and a ~yl"~C;,rr loop filte~ that inLc~ les the phase error and eontrols the VCO 510 to foree the phase error to zero. The synthP,~ r loop forees the VCO 510 frequency to be equal to M/N times ~e VCXO 504 frequency. The values M and N are p~ ---ed via a mi~;lopl ~cesso. (not shown). The -output of the VCO 510 is also sent to a divider circuit 511 which divides the VCO S10 Lc;qu~;y by an integer A which is also p"~g.~ ble by the microprocessor. The frequency of the recovered clock is then (~N)/A times the VCXO frequency. This allows the mi(;~o~l..cessol to ~elrorln coarse adj~lstm~Pnt of the clock frequency by setting M, N, and A
via inputs 520, 521 and 522. The microprocessor may adjust these values based on user inputs, I.r~lall" stored data table, or other inr~,l,llalion sources. Final fine tuning of the clock frequency is achieved by the clock reeovery loop which adjusts ~e exact frequency of the VCXO 504.
The fee Ir~w~ud ~mrlifie.r 509 is used to ll~ l a high mo(~ ti~n bandwidth for the ~y~ . loop even when a relatively low synthe~i7pr loop bandwidth is used. To ilblstr~tP.
the si~lifit~n~ of the addition of the feedfo~w~d path, the following values are ~um~d for the circuit of Figure 5:
VCO tuning range: 16 MHZ to 32 MHZ
VCXO tuning range: ~/-2 I~Iz ce~ d around 16 MHZ
Possible A values: 1, 2, 4, 8, 16, 32 Bit Rate S00 l~Hz to 32 MHZ
To allow any bit rate within the .~es-ifiP~ range to be SPl~t-P~, the value of N must be gre~ter ~an 16 MHZ12 l~Iz. I~is provides the synthp-~i7~r loop with a reference frcquell ;y of 2kHz or less. As a ~esult, the synthp-~i7p~r loop bandwldth must be 1PSS than ~>r .~ e1y 100 Hz.
With the reed~lw~.l ~mplifi~.r in place, the rP~ e from Vc~ to ~c~ is flat with respect to frequency. This allows the clock recovery loop bandwidth to be chosen in-~epen-l~,ntly and Op~ );~ for best a~ui~i~n and ~in~ rOllll~lCe. In contr~t, if the Ç~elr~.lw~ path iS omit~l, the dock recovery loop bandwidth will neecl to be lower by another factor of 10, WO 97/20398 PCT/US96/lX214 or appro~cim~tely lO Hz, because the transfer function from Vc,~ to <~c~ would be lowpass in nature with a bandwidth of around lOO Hz. This low value of clock recovery loop bandwidth may cause the loop not to acquire lock.
Thus, the clock recovery circuit of the present invention as shown in Figure S employs a syn~ht~-ci7er with progr~mm~hle dividers for coarse adju~tment.~ and a variable frequency reference for fine adju~ of the clock. The clock recovery circuit according to the present invention also uses reedro~ Ld to allow independent ad3ustm~ont of the synth~ i7~r loop bandwidth and the clock lccove~ y loop bandwidth. Furthermore, like the carrier recovery circuits shown in Figures 2 and 3, the clock recovery circuit of Pigure S combines the use of a S~ h~ with a variable frequency reference with r~edr~l~d to increase the mo~ *o~
bandwidth.
While the present invention has been particularly described with reference to the ~er~l~d embot1im~-n~, it should be readily a~ ellt to those of o~ a y skill in the art that ~h~n~.~ and ~ lir~ n~ in form and details may be made without departing from the spirit and scol?e of the in~ n. It is int~.nrl~ that the appended claims include such çh~ s and moAific~ti~

Claims (12)

We claim:

1. A highly stable frequency synthesizer loop, comprising:
a first voltage controlled oscillator for receiving a first voltage;
a first divider circuit coupled to an output of said first voltage controlled oscillator for dividing a frequency of a first output signal generated by said first voltage controlled oscillator by a factor of N;
a phase/frequency detector circuit having a first input coupled to an output of said first divider circuit;
a loop filter circuit coupled to an output of said phase/frequency detector circuit;
a feedforward amplifier for receiving and amplifying said first voltage;
a summing circuit having a first input coupled to an output of said loop filter circuit and a second input coupled to an output of said feedforward amplifier;
a second voltage controlled oscillator having an input coupled to an output of said summing circuit, said second voltage controlled oscillator generating a second output signal in response to a second voltage generated by said summing circuit; and a second divider circuit having an input coupled to an output of said second voltage controlled oscillator, said second divider circuit dividing a frequency of said second output signal generated by said second voltage controlled oscillator by a factor of M and having an output coupled to a second input of said phase/frequency detector circuit.

2. A frequency synthesizer loop according to claim 1, wherein said first voltage controlled oscillator is a voltage controlled crystal oscillator which generates a continually variable frequency output.

3. A frequency synthesizer loop according to claim 1, wherein said first voltage represents a phase difference between a received signal and a signal generated by a local oscillator.

4. A frequency synthesizer loop according to claim 1, further comprising a microprocessor for varying the value M in response to said first voltage, said microprocessor varying the value of M to keep said first voltage in the middle of a range of said second voltage controlled oscillator.

5. A tuner circuit comprising:
a voltage controlled oscillator circuit, said voltage controlled oscillator circuit comprising a first voltage controlled oscillator and a second local oscillator; and a loop circuit, responsive to an output of said voltage controlled oscillator circuit and including a third voltage controlled oscillator, said loop circuit comprising a feedforward amplifier for feeding forward the output voltage of the voltage controlled oscillator circuit toward the third voltage controlled oscillator, and a processor , responsive to the output voltage of the voltage controlled oscillator circuit, for controlling a divider circuit of a phase lock loop for controlling the third voltage controlled oscillator.

6. A tuner circuit according to claim 5, wherein said first voltage controlled oscillator is a voltage controlled crystal oscillator which generates a continually variable frequency output.

7. A tuner circuit according to claim 5, wherein said phase lock loop further comprises a phase/frequency detector circuit coupled to an output of said divider circuit and a loop filter circuit having an input coupled to an output of said phase/frequency detector circuit.

8. A tuner for use in a communication system receiver, comprising:
a first local oscillator for generating a first output signal;
a first mixer circuit for mixing a received signal with said first output signal to produce a first intermediate, frequency signal;
a first filter for filtering said first intermediate frequency signal;
a second mixer circuit for mixing said filtered first intermediate frequency signal with a second output signal from a first voltage controlled oscillator to produce a second intermediate, frequency signal;
a second filter to filter said second intermediate frequency signal;
a demodulator circuit for demodulating said second intermediate frequency signal;
a carrier phase recovery circuit coupled to said demodulator circuit for determining a phase error between a second local oscillator and said second intermediate frequency signal;
a first loop filter for generating a first voltage representing said phase error determined by said carrier phase recovery circuit;
a second voltage controlled oscillator for receiving said first voltage and generating a second output signal in response to said first voltage;
a first divider circuit coupled to an output of said first voltage controlled oscillator for dividing a frequency of a second output signal generated by said second voltage controlled oscillator by a factor of N;
a phase/frequency detector circuit having a first input coupled to an output of said first divider circuit;
a second loop filter circuit coupled to an output of said phase/frequency detector circuit;
a feedforward amplifier for receiving and amplifying said first voltage;
a summing circuit having a first input coupled to an output of said second loop filter circuit and a second input coupled to an output of said feedforward amplifier;
said first voltage controlled oscillator having an input coupled to an output of said summing circuit, said first voltage controlled oscillator generating said second output signal in response to a second voltage generated by said summing circuit; and a second divider circuit having an input coupled to an output of said first voltage controlled oscillator said second divider circuit dividing a frequency of said second output signal generated by said first voltage controlled oscillator by a factor of M and having an output coupled to a second input of said phase/frequency detector circuit.

9. A tuner according to claim 8, wherein said first voltage controlled oscillator is a voltage controlled crystal oscillator which generates a continually variable frequency output.

10. A tuner according to claim 8, further comprising a microprocessor for varying the value M in response to said first voltage, said microprocessor varying the value of M to keep said first voltage in the middle of a range of said second voltage controlled oscillator.

11. A clock recovery circuit for receiving a data input and outputting a recovered clock signal, comprising:
a first phase detector for receiving a data input;
a first loop filter coupled to an output of said first phase detector for producing a first voltage;

a first voltage controlled crystal oscillator coupled to an output of said loop filter for providing a variable frequency reference;
a synthesizer loop, said synthesizer loop comprising a first divider circuit for dividing the output frequency of said first voltage controlled crystal oscillator by a factor of N, a second voltage controlled oscillator, a second divider circuit coupled to said voltage controlled oscillator for dividing an output frequency of said second voltage controlled oscillator by a factor of M, a phase/frequency detector circuit for comparing the phase of outputs from said first and second divider circuits, thereby determining a phase error, a second loop filter for integrating the phase error and outputting a corresponding control signal to said second voltage controlled oscillator, thereby reducing said phase error, and a summing circuit having as a first input the output of said second loop filter;
a feedforward amplifier having an input coupled to said output of said first loop filter for receiving said first voltage and an output coupled to a second input of said summing circuit, said summing circuit summing said control signal from said second loop filter and said output from said feedforward amplifier and providing a summed control signal to said second voltage controlled oscillator; and a third divider circuit for dividing an output of said second voltage controlled oscillator by a factor of A, an output from said third divider circuit coupled to a second input of said first phase detector circuit.

12. A clock recovery circuit according to claim 11, further comprising a microprocessor for varying the divider values M, N and A based on information stored in said microprocessor.