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CA2202316A1 - Electronic device assembly - Google Patents

Electronic device assembly

Info

Publication number
CA2202316A1
CA2202316A1 CA002202316A CA2202316A CA2202316A1 CA 2202316 A1 CA2202316 A1 CA 2202316A1 CA 002202316 A CA002202316 A CA 002202316A CA 2202316 A CA2202316 A CA 2202316A CA 2202316 A1 CA2202316 A1 CA 2202316A1
Authority
CA
Canada
Prior art keywords
input
holes
substrate
insulating substrate
output pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002202316A
Other languages
French (fr)
Inventor
Takayuki Suyama
Tadayoshi Miyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2202316A1 publication Critical patent/CA2202316A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1092—Plug-in assemblages of components, e.g. IC sockets with built-in components, e.g. intelligent sockets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10704—Pin grid array [PGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

In an electronic device assembly, a tape carrier package carries an LSI (Large Scale Integrated Circuit) thereon and has through holes arranged bidimensionally in a film and electrically connected to the LSI by a wiring pattern. An insulating substrate has input/output pins thereon. The input/output pins are connected to pads provided on a mounting substrate, extending throughout and contacting the through holes of the tape carrier package. As a result, the LSI
and mounting substrate are electrically connected by the input/output pins. The taper carrier package can be fabricated as inexpensively as the state-of-the-art TBGA
which is lower in cost than a similar wiring using a ceramic laminate substrate. Because the dielectric constant and other factors of the material constituting an insulating substrate do not have to be taken into account, there can be used the most inexpensive material.

Description

ELECTRONIC DEVICE ASSEMBLY

BACKGROUND OF THE INVENTION
The present invention relates to an electronic device assembly and, more particularly, to an electronic device assembly for implementing a pin grid array (PGA), ball grid 5 array (BGA) or multichip module playing the role of an ultra multipin chip carrier which allows an LSI (Large Scale Integrated Circuit) to be mounted thereon.
PGA packages and BGA packages are predominant over the other packages as multipin semiconductor packages, i.e., 1 0 electronic device assemblies. A PGA package has metallic pins arranged bidimensionally on one side of a laminate substrate. The PGA package allows a multipin package to be confined in a smaller area than a quad flat package (QFP) having leads extending out in four directions. The laminate 1 5 substrate of the PGA package is mainly formed of ceramics or glass epoxy. Today, however, it is pointed out that the number of pins available with the PGA package has reached its limit. Specifically, it has been customary to connect an LSI and an insulating laminate substrate by wire bonding.
2 0 While the minimum pitch practicable with wire bonding is 100 ~m, the pad pitch of an L~I is as small as 60 llm to 80 ,um, as generally accepted at the present stage of development. In this sense, the PGA package relying on wire bonding seems to have reached its limit.
S In light of the above, a tape carrier chip subjected to inner lead bonding using a tape carrier system or tape automated bonding (TAB) system may be built in a PGA
package base having a number of pins extending out from its bottom, as taught in, e.g., Japanese Patent Laid-Open 1 0 Publication No. 63-175452. Alternatively, there may be used a carrier tape having pins for outside connection, the t a p e carrier system for incorporating a semiconductor pellet, and resin sealing using transfer molding, as disclosed in, e.g., Japanese Patent Laid-Open Publication No. 1-215031. With 1 5 these electronic device assemblies, it is possible to apply the tape carrier system smaller in bonding pitch than wire bonding to the connecting portions, and therefore to solve the problem stated above.
The BGA package reduces the distance between the 2 0 insulating substrate and the mounting substrate and thereby improves the electric characteristic, compared to the PGA
package. However, the BGA package, like the PGA package, increases the number of wirings and therefore the cost. One of solutions to this problem may be a tape ball grid array 2 5 (TBGA) package proposed in "Electronics Mounting Technologies", Vol. 11, No. 5, May, l99S. In the TBGA package, the wirings of a TAB tape are arranged in a grid array, and solder bumps are provided on the tips of the wirings. This kind of scheme implements a BGA package with a tape. The S TBGA package is expected to implement a low cost, multipin BGA configuration because it reduces the cost more than a BGA package using a ceramic substrate, and because wirings on a polyimide are feasible for fine patterning (40 ,um line an d 40 ,um space).
1 0 The electronic device assembly applying the tape carrier system to the connecting portions needs wirings on a laminate substrate, like the assembly using wire bonding.
The cost of the substrate increases with an increase in t h e number of pins and an increase in wiring density.
1 S Particularly, to produce a laminate substrate with dense wirings, a ceramic substrate, build-up print substrate or similar expensive substrate must be used. Therefore, a multipin configuration is not achievable without increasing the cost to a noticeable degree.
2 0 The number of pins presently available with the TBGA
package is 100 to 600, so that each manufacturer deals w i t h the flatness of the tape in a particular way. However, when the number of pins increases to the order of 1,000, it will be difficult to maintain the flatness of the tape (flexible film), 2 5 particularly when the tape has a broad area. This, coupled with an increase in cost, results in the need for a sophisticated mounting method while increasing the overall cost of the assembly.
Most of the state-of-the-art multichip modules are of 5 the PGA type including an expensive ceramic laminate substrate having input/output pins on one side opposite to the side for mounting a chip. This kind of configuration i s expensive and is used little for the cost performance reason.
Technology relating to the present invention is also 1 0 taught in U.S. Patent No. 4,987,100.

SUMMARY OF THE INVENl'ION
It is therefore an object of the present invention to provide an electronic device assembly allowing even an LSI
1 5 with an ultra multipin configuration to be mounted at low cost.
It is another object of the present invention to provide an electronic device assembly capable of improving productivity despite the ultra multipin configuration of an LSI
2 0 while preserving the present level of operability.
It is a further object of the present invention to provide an electronic device assembly constituting a multichip module which can be readily assembled at low cost.
An electronic device assembly of the present invention 2 5 has at least one tape carrier package carrying an IC and having through holes arranged bidimensionally in a film and electrically connected to the IC by a wiring pattern, and an insulating substrate having input/output pins. The input/output pins are connected to pads provided on a 5 mounting substrate, extending throughout and contacting the through holes. As a result, the IC and mounting substrate are electrically connected.

BRIEF DESCRIPTION OF THE DRAWINGS
1 0 The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings in which:
FIG. 1 is an exploded perspective view of an electronic 15 device assembly embodying the present invention;
FIG. 2 is a section along line A-A of FIG. l;
FIG. 3 is a fragmentary enlarged section showing a positional relation particular to the embodiment of FIG. l;
FIG. 4 is an exploded perspective view showing an 2 0 alternative embodiment of the present invention; and FIG. 5 is a fragmentary enlarged section showing a positional relation particular to the alternative embodiment.

DESCRIPI ION OF THE PREFERRED EMBODIMENTS
Referring to FIGS. 1 and 2 of the drawings, an electronic device assembly embodying the present invention is shown.
As shown, the assembly includes a tape carrier package loaded with an LSI 2. An insulating substrate 3 is provided with input/output pins 4. A radiator 5 is mounted on the central part of the top of the insulating substrate 3.
The tape carrier package 1 has an insulating portion implemented by, e.g., a 50 ,um thick polyimide film. The 1 0 polyimide film may be replaced with any other suitable flexible insulating material. The polyimide film is formed with, e.g., 800 through holes having a diameter of 200 ,um in a square grid pattern. A device hole is formed in the center of the film and dimensioned slightly larger than the LSI 2 in 1 5 order to receive the LSI 2. Inner leads for the connection of the LSI 2 is provided in the device hole. A 40 ~um wide copper wiring pattern is formed on the film in order to electrically connect the through holes and the inner leads of the device hole.
2 0 The LSI 2 is an LSI chip having 808 pins or terminals and has the terminals connected to the inner leads of the ab ove polyimide film. After the bonding of the inner leads, a resin layer is formed on the LSI 2 by bonding in order to protect the chip and connecting portions. The taper carrier package 1 can 2 5 be fabricated as inexpensively as the state-of-the-art TBGA

which is lower in cost than a similar wiring using a ceram i c laminate substrate.
The subserate 3 does not have any wiring and does not transfer any signal, so that the dielectric constant and other 5 factors of the material do not have to be taken into account a t the design stage. In the illustrative embodiment, the substrate 3 is formed of glass epoxy which is the most inexpensive material.
The radiator 5 mounted on the substrate radiates heat 1 0 generated by the LSI 2 during operation. The radiator 5 should preferably have a coefficient of thermal expansion 1 i t t 1 e different from that of the LSI 2. This is an important consideration particularly when the LSI chip has a multipin large-size configuration. In the illustrative embodiment, the 1 5 radiator 5 is formed of a copper/tungsten (Cu/W) alloy although use may be made of CuMo or alumina plate. Through holes are formed in the peripheral portion of the substrate 3.
As shown in FIG. 3, the through holes, labeled 7, each simply holds one end of the respective input/output pin 4 and does 2 0 not need electrical connection.
The input/output pins 4 connect the through holes of the tape carrier package 1 and a mounting substrate, and a r e usually formed of metal. In the embodiment, use is made of Kobar pins having a length of 1 mm and a diameter of 200 ~m 2 5 and plated with gold. The substrate 3 and tape carrier package 1 are combined in a PGA configuration, as shown in FIG. 3 in a section.
FIG. 3 shows the positional relation between the input/output pins 4 (only one is shown) and the tape carrier 5 package 1 in detail. In FIG. 3, the same structural elements as those shown in FIGS. 1 and 2 are designated by the same reference numerals. As shown, one end of the pin 4 is fixedly received in the through hole of the insulating substrate 3.
The pin 4 is aligned with and passed through a through hole 8 1 0 formed in the take carrier package 1, as illustrated.
In the illustrative embodiment, the input/output pins 4 and through holes both have a diameter of 200 ~m. However, the pins 4 may advantageously have a slightly larger diameter than the through holes, considering mechanical strength at 1 5 the time of contact. For example, each pin 4 may have a diameter of 220 ,um to 250 ,um for the diameter of 200 llm of each through hole. If the replacement of the tape carrier package 1 is not expected in the future, then the pin 4 and the through hole 8 of the tape carrier package 1 may be soldered 2 0 (hot soldering) or adhered to each other.
In the assembly shown in FIG. 3, the tip of each input/output pin 4 is affixed by solder 10 to a pad 9 provided on a mounting substrate 6. In this condition, the LSI 2 and mounting substrate 6 are electrically connected together b y 2 5 the pin 4. A ground surface 11 is formed on the rear of the tape carrier package 1. In this manner, the embodiment realizes a package having a larger number of pins than the conventional package without resorting to expensive parts, including a laminate substrate, or advanced technologies.
Referring to FIG. 4, an alternative embodiment of t h e present invention will be described. In FIG. 4, the same structural elements as those shown in FIG. 1 are designated by the same reference numerals, and a detailed description thereof will not be made in order to avoid redundancy. As 1 0 shown, this embodiment has three tape carrier packages 1-1, 1-2 and 1-3 stacked on the rear of the insulating substrate 3.
LSIs 2-1, 2-2 and 2-3 each having a particular function are respectively mounted on the tape carrier packages 1-1, 1-2 and 1-3, constituting tape carriers. The LSIs 2-1 through 2-3 1 5 are different from each other with respect to the relation t o the input/output pins 4 and the wiring. However, the pins 4 extend throughout the aligned through holes of the LSIs 2 - 1 through 2-3, electrically connecting the LSIs 2-1 through 2-3 to a mounting substrate, not shown. At this instant, the pins 2 0 4 for connecting the LSIs 2-1 through 2-3, the pins 4 for connecting a certain LSI to the mounting substrate, the pins 4 for connecting all the LSIs to the mounting substrate and so forth can be set up by a wiring method.
FIG. 5 shows the positional relation between the 2 5 input/output pins 4, the insulating substrate 3, and the tape carrier packages 1-1 through 1-3 in detail. As shown, input/output pins 4-1, 4-2 and 4-3 (corresponding to the pins 4 shown in FIG. 4) each has its one end fixedly received in the corresponding through hole of the insulating substrate 3. The 5 pins 4-1 through 4-3 extend throughout the through holes of the tape carrier packages 1-1 through 1-3. The other ends of the pins 4-1, 4-2 and 4-3 are respectively electrically connected to pads 9-1, 9-2 and 9-3 provided on the mounting substrate 6. The mounting substrate 6 is implemented as a 10 laminate wiring board having wiring layers 1 2 thereinside.
The pad 9-1 is connected to a via hole 13.
Assume that the LSIs 2-1 through 2-3 shown in FIGS. 4 and 5 are RAMs (Random Access Memories). Then, a memory module is achievable if it is designed such that only t h e 15 selector pins of the RAMs are connectable individually and if the other pins are commonly connectable.
On the other hand, assume that the LSI 2-1 is a microprocessor while the LSIs 2-2 and 2-3 are RAMs. Then, a multichip module with a cache is achievable if the tape 2 0 carrier packages 1-2 and 1-3, except for their selector pins, are commonly connectable to the address pins and data pins o f the LSI 2-1 and if the selector pins of the packages 1-2 and 1-3 are connectable individually.
As stated above, this embodiment allows a multichip 2 5 module to be produced more easily than a conventional module having chips arranged side by side on a ceramic substrate.
Further, because the embodiment does not need a laminate substrate, it is low cost. In addition, LSIs can be tested at the time of tape carrier packaging, preventing defective chips from being mounted.
In summary, it will be seen that the present invention is capable of constructing an ultra multipin package easily at low cost. Specifically, a tape carrier package can be fabricated as inexpensively as the state-of-the-art TBGA
1 0 which is lower in cost than a similar wiring using a ceramic laminate substrate. Because the dielectric constant and other factors of the material constituting an insulating substrate do not have to be taken into account, there can be used the most inexpensive material. In addition, input/output pins 1 5 provided on the insulating substrate electrically connect the tape carrier package and a mounting substrate, extending throughout through holes formed in the package. This kind of electrical connection is identical with the connection of a PGA.
2 0 Further, the present invention readily implements a multichip module having a plurality of tape carrier packages each carrying an LSI having a particular function, and allowing the input/output pins to simply extend throughout their aligned holes. Moreover, the multichip module is low 2 5 cost because it does not need a laminate substrate.

Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. For example, the present invention is applicable even to through-5 hole mounting, socket mounting and other conventionalmounting schemes.

Claims (4)

1. An electronic device assembly comprising:
at least one tape carrier package carrying an IC and having through holes arranged bidimensionally in a film and electrically connected to said IC by a wiring pattern; and an insulating substrate having input/output pins;
wherein said input/output pins are connected to pads provided on a mounting substrate, extending throughout and contacting said through holes, whereby said IC and said mounting substrate are electrically connected.
2. An assembly as claimed in claim 1, wherein said insulating substrate comprises a radiator mounted on a center of a top of said insulating substrate, a plurality of through holes formed in a peripheral portion of said insulating substrate, and said input/output pins each being fixedly received in one of said plurality of through holes at one end.
3. An assembly as claimed in claim 1, wherein a plurality of tape carrier packages each carries a respective IC
having a particular function and allows said input/output pins to extend throughout the through holes aligned with the through holes of the other tape carrier packages, constituting a multichip module.
4. An assembly as claimed in claim 3, wherein said insulating substrate comprises a radiator mounted on a center of a top of said insulating substrate, a plurality of through holes formed in a peripheral portion of said insulating substrate, and said input/output pins each being fixedly received in one of said plurality of through holes at one end.
CA002202316A 1996-04-15 1997-04-10 Electronic device assembly Abandoned CA2202316A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8-92197 1996-04-15
JP8092197A JPH09283652A (en) 1996-04-15 1996-04-15 Electronic device assembly

Publications (1)

Publication Number Publication Date
CA2202316A1 true CA2202316A1 (en) 1997-10-15

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JP (1) JPH09283652A (en)
CA (1) CA2202316A1 (en)
FR (1) FR2747510A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58112348A (en) * 1981-12-25 1983-07-04 Fujitsu Ltd semiconductor equipment
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
JPH0563138A (en) * 1991-04-18 1993-03-12 Hitachi Ltd Semiconductor integrated circuit device
DE69330630T2 (en) * 1992-05-15 2002-06-13 Irvine Sensors Corp., Costa Mesa NON-CONDUCTIVE EDGE LAYER FOR INTEGRATED STACK OF IC CHIPS
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process

Also Published As

Publication number Publication date
FR2747510A1 (en) 1997-10-17
JPH09283652A (en) 1997-10-31

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