CA2144740C - A thin multichip module - Google Patents
A thin multichip module Download PDFInfo
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- CA2144740C CA2144740C CA002144740A CA2144740A CA2144740C CA 2144740 C CA2144740 C CA 2144740C CA 002144740 A CA002144740 A CA 002144740A CA 2144740 A CA2144740 A CA 2144740A CA 2144740 C CA2144740 C CA 2144740C
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- module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
An improved semiconductor module comprising a molded frame and a composite semiconductor substrate subassembly received in a cavity in the molded frame (10). The composite semiconductor substrate subassembly comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the composite semiconductor substrate subassembly includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components (58). In some of the embodiments disclosed herein, the composite semiconductor substrate subassembly, comprising a cover plate with the composite substrate attached thereto, is attached to the molded frame by a rectangular ring formed from an anisotropic, electrically conductive adhesive material (52).
The composite substrate employed in the present invention offers the advantage of allowing the components to be pre-assembled, tested and repaired prior to final attachment into the molded frame.
The composite substrate employed in the present invention offers the advantage of allowing the components to be pre-assembled, tested and repaired prior to final attachment into the molded frame.
Description
.,.
1~~~~~740 2 Field of Invention 3 The present invention relates generally to means for encapsulating microelectronic devices. More specifically, the present invention. provides an improved module for significantly increasing the packaging density of microelectronic components.
6 Background 7 The electronics industry has a continuing goal of increasing component packaging 8 density in an effort to obtain increased functionality and consequent performance in 9 smaller volumetric size. The principal roadblocks in meeting this goal have been the lack io of industry standards for form factors and a flexible design which can be adapted to 11 differing device types. Another significant impediment to increased packaging density 12 has been the lack of a efficient means for dissipation of thermal energy generated by the 13 devices.
14 One of the largest microelectronic device module markets is that related to dynamic random access memories (DRAM's). Since its introduction in 1983, the Single 16 In-Line Memory Module or SIMM, disclosed generally in U.S. Patent No's.
1~~~~~740 2 Field of Invention 3 The present invention relates generally to means for encapsulating microelectronic devices. More specifically, the present invention. provides an improved module for significantly increasing the packaging density of microelectronic components.
6 Background 7 The electronics industry has a continuing goal of increasing component packaging 8 density in an effort to obtain increased functionality and consequent performance in 9 smaller volumetric size. The principal roadblocks in meeting this goal have been the lack io of industry standards for form factors and a flexible design which can be adapted to 11 differing device types. Another significant impediment to increased packaging density 12 has been the lack of a efficient means for dissipation of thermal energy generated by the 13 devices.
14 One of the largest microelectronic device module markets is that related to dynamic random access memories (DRAM's). Since its introduction in 1983, the Single 16 In-Line Memory Module or SIMM, disclosed generally in U.S. Patent No's.
4,656,605 and t7 4,727,513, has grown to become the preferred module configuration for the DRAM
18 semiconductor market. Among the advantages offered by the SIMM are the following:
19 (1) its significant packaging density increase achieved over prior chip mounting 2o configurations, (2) the convenience for modular replacement or upgrade, and (3) 21 availability of multiple, low-cost manufacturing sources.
WO 94/07264 : . PCT/US93/08576 1 A continuing industry trend towards increasing performance and smaller size, 2 however, foreshadows the need for an even more compact module than the present SIMM ' 3 is able to provide. The quest for ever faster data processing and more compact, light , weight, portable electronic products necessitates newer semiconductor packaging schemes that enable aggregate assemblages of bare silicon devices to be interconnected together 6 and mechanically protected inside a thin, lightweight module. Because of the handling 7 difficulty and expense associated with repairing or replacing bare silicon chip devices, 8 there is a need for an improved multichip module which meets the need for increased 9 packaging density while maintaining minimum expense. This present invention, described 1o in greater detail below, seeks to satisfy this need within the electronic industry.
11 Though semiconductor memory devices occupy the vast majority of the module 12 market today, there is also a growing requirement to modularize other semiconductor 13 components including, but not limited to, microprocessor, application specific integrated 14 circuits, telecommunication and other device types. Accordingly, the present invention provides an upgrade path for a greater number of interconnect pins/pads and improves the 16 thermal dissipation characteristics over present day microelectronic device modules.
17 Summary of the Invention 18 The improved semiconductor module of the present invention is broadly comprised 19 of a molded frame and a composite semiconductor substrate subassembly received in a 2o cavity in said frame: The composite semiconductor substrate subassembly comprises a WO 94/07264 2 1 ~ 4 7 4 0 1 plurality of semiconductor devices which are connected to electrical contacts on an edge 2 of the molded frame by a variety of configurations described herein.
3 In one embodiment of the invention, the composite semiconductor substrate sub-assembly includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The 6 composite substrate provides a mounting surface for the placement of semiconductor 7 devices and their associated passive components. In some of the embodiments disclosed 8 herein, the composite semiconductor substrate sub-assembly, comprising a cover plate 9 with the composite substrate attached thereto, is attached to the molded frame by a to rectangular ring formed from an anisotropic, electrically conductive adhesive material.
11 The composite substrate employed in the present invention offers the advantage of 12 allowing the components to be pre-assembled, tested and repaired prior to final attachment 13 into the molded frame.
14 Brief Description IS of the Drawings 16 FIG. 1 is a exploded view of the major components of a first embodiment of the thin 17 multichip module of the present invention.
Is FIGS. 2A-2B are cross-sectional views taken along lines 2A-2A of FIG. I
showing details 19 relating to electrical contacts of the molded frame of the present invention.
20 FIG. 3 is a detailed view of the electrical contacts of the molded frame of the present 21 invention.
WO 94/07264 ~ PGT/US93/08576 1 FIGS. 4A-4D show details relating to individual contact elements employed in the multi-2 chip module of the present invention.
3 FIGS. SA-SC show details relating to alternate embodiments of individual contact elements employed in the mufti-chip module of the present invention.
FIGS. 6A-6C show details relating to further alternate embodiments of individual contact 6 elements employed in the mufti-chip module of the present invention.
7 FIGS. 7A-7B show alternate embodiments of edge mount clips for electrical contacts on 8 the molded frame of the present invention 9 FIGS. 8A-8B illustrate an alternate embodiment of the present invention comprising an overmolded composite semiconductor substrate assembly.
11 FIG. 9 is a exploded view of the major components of an alternate embodiment of the 12 thin multichip module of the present invention.
13 FIGS. l0A-lOB illustrate thermal dissipation features of the composite semiconductor 14 substrate of the present invention.
FIG. 11 illustrates thermal dissipation features of the cover plate of the composite 16 semiconductor substrate of the present invention.
17 FIG. 12 illustrates an implementation of stacked memory chips for use in the composite 18 semiconductor substrate assembly of the present invention.
19 FIG. 13 is a exploded view of the major components of an alternate embodiment of the thin multichip module of the present invention comprising multiple composite 21 semiconductor substrate assemblies.
WO 94/07264 ' PCT/US93/08576 1 Detailed Description of 2 the Preferred Embodiment 3 A preferred embodiment of the multichip module 10 of the present invention can be understood by referring to FIG. 1, which is an exploded view of the major components 5 of the module. A molded frame assembly 12 comprises an internal cavity 14 which 6 extends over a substantial portion of the length and width of the module to provide a 7 nesting area for the electronic components in the finished module assembly.
The molded 8 frame 12 can be manufactured from an injection molded, thermoplastic material such as 9 a liquid crystal polymer (LPC) or "Ryton~'". Both of these materials allow consistent and repeatable control over the dimensions of the molded frame 12. However, it should be i 1 obvious to one versed in the art, that several other materials may be substitute without 12 departing from the scope or spirit of this invention. For example, the molded frame 12 13 may also be constructed from single or multiple laminate layers of epoxy glass materials 14 (similar in composition to conventional PCB products) which have been shaped by stamping, pressing or machining processes to produce features similar in function to those 16 described above. Alternatively, the molded frame 12 may be formed from one of several 17 ceramic based materials processed though a firing kiln or hydraulic press by techniques 18 well known within the industry.
19 Referring to FIG. 1 it can be seen that the molded frame 12 comprises first and second major parallel planes, illustrated by reference numerals 16 and 18, respectively, 21 that are separated by a specified edge thickness illustrated by reference numeral 20. An 22 array of contact pads 22 along one edge of the frame 12 provides electrical connection WO 94/07264 PCT/><JS93/08576 1 between the semiconductor devices contained within the interior of the module and an 2 appropriate mating socket. In the embodiment illustrated in FIG. 1, the frame 12 is 3 provided with two optional end holes 24 and a corner notch 26. These features are used 4 for proper mating of the module to presently available SIMM sockets supplied by several connector manufacturers.
6 The internal cavity 14 may extend either partially or completely through the edge 7 thickness 20, depending upon the spacing requirements of the components contained in 8 the module. Although it is possible to construct the frame to have a single internal cavity, 9 it is possible to also create first and second internal cavities by forming a thin, integrally to molded floor 28 positioned along the centerline of the module thickness.
Two possible 11 embodiments of the molded floor 28 are illustrated in FIGS. 2A and 2B. In FIG. 2A, 12 which is taken along section lines 2A-2A of FIG. 1, the floor 28 is shown molded flush 13 to the second major plane 18. In the embodiment illustrated in FIG. 2B, however, the 14 floor 28 is shown along the centerline of the module thickness to form first and second internal cavities in the interior of the module.
16 A stepped ledge 30 is formed around the circumference of the cavity 14 or cavities 17 to provide a receiving area for the mating composite semiconductor substrate assembly 18 32 described in greater detail below. In the preferred embodiment, the ledge 30 is 19 recessed below either the first major plane 16 or the second major plane 18 such that after 2o the cover plate subassembly 32 is positioned and sealed in place, the outer surfaces of 21 the subassembly 32. and the molded frame 12 are substantially flush to ot~e another.
,~ z144'~4~s , i Alternatively, the ledges may be simple extensions of major plane 16 and/or major plane a 2 18, as illustrated in FIG. 2B, placing the composite semiconductor substrate assembly 32 . 3 further away from the center line of the module thickness, thus allowing more spacing for internal components. In this embodiment, the cover plate sub-assembly 32 would project a short distance above major plane 16 and/or major plane 18.
6 The array of contact pads 22 on the edge of the molded frame 12 provide 7 electrical connection from the external surface edge of the module to an interior stepped 8 ledge 30 of the module cavity 14 or cavities. Arrayed across the interior stepped ledge 9 30 is a multiplicity of smaller termination pads 34, each electrically paired with an 1o associated external contact pad 22. In one embodiment of the invention, each of the 11 contact pads 22 and termination pads 34 are formed by a selective plating process that 12 deposits a conductive metal pattern extending from the edge of the molded frame 12, 13 across the surface of the frame, and down a vertical wall or inclined plane 36, as shown 14 in FIG. 2A and 3, to the surface of the ledge 30 lying a short distance below the first t5 major plane 16 and/or the second major plane 18. Similarly positioned pairs of contact 16 pads 22 and termination pads 34 on the opposite planes of the molded frame 12 can be 17 electrically connected by a shunt 21 across the lower edge of the frame 12, as illustrated 18 in FIG. 2B, or left electrically isolated.
19 Post molded plating techniques that may be commonly employed to produce the 20 mufti-leveled path of electrical conduction include, but are not restricted to, electrolytic 21 or electroless plated copper, nickel, gold, or tin/lead alloys.
These and other pure metals ,,~ ;
1 and alloys may be selectively plated onto the selected portions of the molded frame 12 2 via surface treatment and masking techniques known and available within the molded .
3 PCB industry. Alternatively, various plating processes may be employed separately or combined with screen printable, metal filled inks to produce electrically conductive pads on ceramic or epoxy glass materials.
6 As the need arises for a greater number of signal and data in/out connections than 7 can be accommodated by using conventional plating processes to reduce the contact pad-s width 23 and contact-to-contact pad-pitch 25, as shown in FIG. 3, an increased signal path 9 density can be obtained by integrally molding into frame 12 an array of stamped metal 1o contacts or by inserting stamped metal contacts into receptacles pre-molded in the edge i i of the frame 12, as shown in FIG. 4D. The array of stamped metal contacts comprises 12 a plurality of thin, substantially parallel plates that are closely spaced but electrically 13 insulated from one another by encompassing mold material. These stamped metal 14 contacts have exposed edges extending from the bottom edge of the molded frame 12 across the contact pad surface plane and across the interior stepped ledge on the interior 16 of the frame. The edges of the stamped contacts are substantially flush with the 17 surrounding molded surfaces or project slightly above, except in the area corresponding 18 to the exposed edge of the composite semiconductor substrate sub-assembly 32 where the 19 stamped contact would be recessed into the molded frame to avoid undesirable electrical 2o contact and structural weakening of the molded frame.
21 The above-described electrical contact arrangement can be understood by referring 1 to FIGS. 4A-4C. FIG. 4A is an illustration of an array 36 of individual contact members 2 38. The edges of the individual contacts 38 provide electrical interconnections between 3 the interior and exterior of the frame 12 corresponding to the contact pads 22 and 4 termination pads 34 discussed above. For example, once the array 36 of contacts 38 have been molded or inserted into the edge of the frame 12, as illustrated in FIGS.
4A and 4C, 6 the edges 22' and 34' of the individual contacts 38, shown in FIGS. 4A and 4C, 7 correspond to the respective contact pads 22 and termination pads 34 discussed above in 8 connection with the prior embodiments. FIG. 4C is a cross-sectional illustration of the 9 contacts positioned inside frame 12. This figure also illustrates an additional electrical 1o contact surface resulting from the projection of an end portion 22" of a contact 38 from 11 the edge of the frame 12.
12 Additional embodiments based on the concept of integrally molded or insertable 13 individual contact members 38 as an array 36 can be seen in FIGS. 5 and 6.
Since 14 individual contact members 38 are formed by a stamping process, which does not IS necessitate additional bending or folding steps to form the contacts, simple appendages 16 may be optionally included during stamping of the contacts to customize the contacts for 17 a "through hole" leaded contact 37 or a "surface mount" leaded contact 39.
Adjusting the 18 centerline of the "through hole" lead 3T enables the distance, D, between the adjacent 19 contacts 37 to be adjusted (D') for standard or non-standard hole patterns on the main 20 circuit board as illustrated in FIGS. SB and C, when adjacent contacts in an array are 21 molded or inserted while alternately rotated 180 degrees with respect to each other. By ._ W 94/07264 ~' PCT/US93/08576 O
I molding or inserting "surface mount" leaded contacts 39 in alternating orientations as 2 illustrated in FIGS. 6B and 6C, solder pads on the main circuit board may be optimally ' 3 spaced on alternating sides of the module, and a more stable mounting base is provided with contacts 39. Additional support may be provided at both ends of the molded frame 5 12, as later described in connection with FIG. 7 B, by inserting or molding a formed metal clip or post 41 into the bottom-end of molded frame 12.
7 Use of flat surfaced contact pads 22 located at the bottom edge of the molded s frame 12 is the preferred configuration for this invention for backward compatibility with 9 present SIMM sockets. However, an alternative embodiment of the invention would 10 include formed metal clips over the edge of the molded frame to produce a "leaded"
I I version of the invention for direct solder mounting of the module to a PCB
using either 12 "through-hole" or "surface mount" soldering technology. FIG. 7A is an illustration of the 13 molded frame 12 having a plurality of leads 40 attached to the contact pads 22 for use 14 on a "through hole" soldering attachment. FIG. 7B is an illustration of plurality of leads 40' attached to the contact pads 22 for use in a "surface mount" soldering attachment. In 16 this embodiment of the invention, an end post 42 integrally molded at both extreme ends 17 on the molded frame 12 is included to assist in maintaining proper alignment of the 18 module in the main circuit board during the "surface mount" soldering process. These 19 end posts 42 would typically be molded with differing cross-sectional diameters, i.e., one larger than the other, to mate with appropriately sized holes within the main circuit board, 21 thereby enabling the modules to be correctly oriented and secured against movement ~1~47~0 1 during the soldering process.
2 Details relating to the composite semiconductor substrate sub-assembly 32 will 3 now be discussed by referring again to FIG. 1. The sub-assembly includes a composite 4 substrate 46 which comprises a thin metal cover plate 48 and thin laminate circuit 50 which is bonded to the metal cover plate 48 by a film adhesive 52. The composite 6 substrate 46 provides a rigid mounting surface for the placement of semiconductor devices 7 54 and their associated passive components 56. The composite semiconductor substrate 8 sub-assembly 32 is attached to the molded frame by a rectangular ring 58 formed from 9 an anisotropic, electrically conductive adhesive material.
1o The composite substrate employed in the present invention offers the advantage 11 of allowing the components to be pre-assembled, tested and repaired prior to final 12 attachment into the molded frame 12. In the preferred embodiment, the cover plate 48 t3 is formed from stainless steel and the thin laminate circuit 50 is a multilayered, thin 14 copperlpolyimide flexible circuit. However, materials other than those described above can be substituted for the cover plate 48 and the thin laminate circuit 50.
Alternative 16 material choices for the cover plate 48 include epoxy-glass, ceramic, aluminum, copper-17 nickel alloys and other metal and non-metal rigid structures. The metal materials listed 18 above offer advantages over other material choices, because of their thermal transfer 19 properties. Anti-static and/or electrical shielding properties are also enhanced by the use of a metal cover plate 48. Additional anti-static protection in selective locations may be 21 provided by including anti-static or electrically conductive filler materials in the mold 1 compound when forming the molded frame I2 and/or adding specialized coatings as part 2 of a post molded process. These extra measures would be warranted for static sensitive , 3 or electrically emissive semiconductor devices. In applications involving semiconductor devices switching or operating at frequencies above 50 Mhz., it may be necessary or desirable to establish an electrical ground plane potential across the cover plate 48. This 6 may be readily accomplished by direct electrical contact between one or more specific 7 ground contact pads 22 and the cover plate 48, or through ground connections established 8 directly through the thin laminate circuit 50.
9 Numerous materials may be substituted for the thin laminate circuit 50 without t0 departing from the scope or spirit of the present invention. For instance, thin epoxy-glass I I PCBs, multi-layer ceramic circuit cards, screen printed or vacuum deposited and/or plated 12 thin film chrome/copper/gold or aluminum, over polyimide or polyester film circuits may 13 each be effectively used in place of the preferred flexible circuit. In some instances, a 14 film adhesive 52 may not be required. For example, a thin laminate circuit 50 fabricated IS by sequential deposition of copper/polyimide thin films directly onto the cover plate 48 16 would not require an adhesive. This type of process is generally associated with 17 controlled or matched impedance circuits employing stripline and/or wave guide structures I8 required for high frequency applications.
19 The primary purpose of the thin laminate circuit 50 is to provide electrical 2o interconnection between individual electronic devices 54 or a group of stacked electronic 21 devices mounted on the circuit 50, and to conduct data signals and control voltages to and WO 94/07264 ~ ~ ~ ~ ~ ~ ~ . PCT/US93/08576 I from the termination pads 34 on the molded frame 12. To facilitate transfer of these 2 signals and voltages, a series of electrically conductive substrate pads 60 are arrayed 3 along one or more edges of the thin laminate circuit 50 such that when the composite semiconductor substrate sub-assembly 32 is attached to the molded frame 12, each substrate pad 60 overlays a corresponding termination pad 34 on the molded frame 12.
In an alternate embodiment of the present invention, the thin laminate circuit 7 can be attached on or integrated directly into the floor 28 of the molded frame 12. In this 8 embodiment, the cover plate 48 may include an additional thin laminate circuit. Tab leads 9 or pads arrayed along the edges) of the circuit 50 can then be directly connected or soldered to appropriately sized and placed termination pads 34 along a shorter stepped i I ledge 30 or floor 28 of the molded frame 12. Another embodiment, --principally suitable 12 for a molded frame 12 formed from multiple, stacked, layers of kiln-fired, ceramic sheets 13 imprinted with electrically conductive lines and via pads, -- can incorporate the circuit as 14 an integral part of the floor 28 of the module frame 12, such that the uppermost layer IS constituted the device and component attachment surface. In yet another embodiment of i6 the present invention, the composite semiconductor substrate sub-assembly 32 can be used 17 independently of the molded frame 12 by applying or molding a protective overcoat 70, 18 as shown in FIG. 8, comprising an epoxy or mold compound material covering the 19 semiconductor devices 54, passive components 56 and substantial surface of the thin laminate circuit S0, leaving substrate pads 60, end surfaces 50' and external surface 48' 21 of the cover plate ~ 48 exposed. The resultant composite semiconductor substrate .
WO 94/07264 ~ ~ ''~ PCT/US93/08576 1 subassembly 32 can then be mated to an appropriate socket with slots to receive the end 2 surfaces 50' or combined with a plurality of leads 40 for directly mounting to a main 3 circuit board. An optional embodiment of the module shown in FIG. 8 can combine additional semiconductor devices 54 and other components 56 to the external surface 48' S of the cover plate 48 by applying an additional thin laminate circuit 50 and applying or 6 molding a protective overcoat 70 to the surface 48' also. Thin laminate circuits 50 on 7 either surface of cover plate 48 can be either physically separate and, therefore, 8 electrically independent, or physically and electrically joined along the edges) of cover plate 48 as a single flexible circuit folded over and around said edge(s). In this example, to the module would appear symmetrical with respect to a centerline drawn end-to-end i l through cover plate 48, as shown in FIG. 8B.
12 To lower thermal resistance and, hence, enhance normal thermal conductivity 13 between the contained semiconductor devices and the exterior surface of the module, 14 several features may be optionally incorporated as part of the thin laminate circuit 50.
18 semiconductor market. Among the advantages offered by the SIMM are the following:
19 (1) its significant packaging density increase achieved over prior chip mounting 2o configurations, (2) the convenience for modular replacement or upgrade, and (3) 21 availability of multiple, low-cost manufacturing sources.
WO 94/07264 : . PCT/US93/08576 1 A continuing industry trend towards increasing performance and smaller size, 2 however, foreshadows the need for an even more compact module than the present SIMM ' 3 is able to provide. The quest for ever faster data processing and more compact, light , weight, portable electronic products necessitates newer semiconductor packaging schemes that enable aggregate assemblages of bare silicon devices to be interconnected together 6 and mechanically protected inside a thin, lightweight module. Because of the handling 7 difficulty and expense associated with repairing or replacing bare silicon chip devices, 8 there is a need for an improved multichip module which meets the need for increased 9 packaging density while maintaining minimum expense. This present invention, described 1o in greater detail below, seeks to satisfy this need within the electronic industry.
11 Though semiconductor memory devices occupy the vast majority of the module 12 market today, there is also a growing requirement to modularize other semiconductor 13 components including, but not limited to, microprocessor, application specific integrated 14 circuits, telecommunication and other device types. Accordingly, the present invention provides an upgrade path for a greater number of interconnect pins/pads and improves the 16 thermal dissipation characteristics over present day microelectronic device modules.
17 Summary of the Invention 18 The improved semiconductor module of the present invention is broadly comprised 19 of a molded frame and a composite semiconductor substrate subassembly received in a 2o cavity in said frame: The composite semiconductor substrate subassembly comprises a WO 94/07264 2 1 ~ 4 7 4 0 1 plurality of semiconductor devices which are connected to electrical contacts on an edge 2 of the molded frame by a variety of configurations described herein.
3 In one embodiment of the invention, the composite semiconductor substrate sub-assembly includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The 6 composite substrate provides a mounting surface for the placement of semiconductor 7 devices and their associated passive components. In some of the embodiments disclosed 8 herein, the composite semiconductor substrate sub-assembly, comprising a cover plate 9 with the composite substrate attached thereto, is attached to the molded frame by a to rectangular ring formed from an anisotropic, electrically conductive adhesive material.
11 The composite substrate employed in the present invention offers the advantage of 12 allowing the components to be pre-assembled, tested and repaired prior to final attachment 13 into the molded frame.
14 Brief Description IS of the Drawings 16 FIG. 1 is a exploded view of the major components of a first embodiment of the thin 17 multichip module of the present invention.
Is FIGS. 2A-2B are cross-sectional views taken along lines 2A-2A of FIG. I
showing details 19 relating to electrical contacts of the molded frame of the present invention.
20 FIG. 3 is a detailed view of the electrical contacts of the molded frame of the present 21 invention.
WO 94/07264 ~ PGT/US93/08576 1 FIGS. 4A-4D show details relating to individual contact elements employed in the multi-2 chip module of the present invention.
3 FIGS. SA-SC show details relating to alternate embodiments of individual contact elements employed in the mufti-chip module of the present invention.
FIGS. 6A-6C show details relating to further alternate embodiments of individual contact 6 elements employed in the mufti-chip module of the present invention.
7 FIGS. 7A-7B show alternate embodiments of edge mount clips for electrical contacts on 8 the molded frame of the present invention 9 FIGS. 8A-8B illustrate an alternate embodiment of the present invention comprising an overmolded composite semiconductor substrate assembly.
11 FIG. 9 is a exploded view of the major components of an alternate embodiment of the 12 thin multichip module of the present invention.
13 FIGS. l0A-lOB illustrate thermal dissipation features of the composite semiconductor 14 substrate of the present invention.
FIG. 11 illustrates thermal dissipation features of the cover plate of the composite 16 semiconductor substrate of the present invention.
17 FIG. 12 illustrates an implementation of stacked memory chips for use in the composite 18 semiconductor substrate assembly of the present invention.
19 FIG. 13 is a exploded view of the major components of an alternate embodiment of the thin multichip module of the present invention comprising multiple composite 21 semiconductor substrate assemblies.
WO 94/07264 ' PCT/US93/08576 1 Detailed Description of 2 the Preferred Embodiment 3 A preferred embodiment of the multichip module 10 of the present invention can be understood by referring to FIG. 1, which is an exploded view of the major components 5 of the module. A molded frame assembly 12 comprises an internal cavity 14 which 6 extends over a substantial portion of the length and width of the module to provide a 7 nesting area for the electronic components in the finished module assembly.
The molded 8 frame 12 can be manufactured from an injection molded, thermoplastic material such as 9 a liquid crystal polymer (LPC) or "Ryton~'". Both of these materials allow consistent and repeatable control over the dimensions of the molded frame 12. However, it should be i 1 obvious to one versed in the art, that several other materials may be substitute without 12 departing from the scope or spirit of this invention. For example, the molded frame 12 13 may also be constructed from single or multiple laminate layers of epoxy glass materials 14 (similar in composition to conventional PCB products) which have been shaped by stamping, pressing or machining processes to produce features similar in function to those 16 described above. Alternatively, the molded frame 12 may be formed from one of several 17 ceramic based materials processed though a firing kiln or hydraulic press by techniques 18 well known within the industry.
19 Referring to FIG. 1 it can be seen that the molded frame 12 comprises first and second major parallel planes, illustrated by reference numerals 16 and 18, respectively, 21 that are separated by a specified edge thickness illustrated by reference numeral 20. An 22 array of contact pads 22 along one edge of the frame 12 provides electrical connection WO 94/07264 PCT/><JS93/08576 1 between the semiconductor devices contained within the interior of the module and an 2 appropriate mating socket. In the embodiment illustrated in FIG. 1, the frame 12 is 3 provided with two optional end holes 24 and a corner notch 26. These features are used 4 for proper mating of the module to presently available SIMM sockets supplied by several connector manufacturers.
6 The internal cavity 14 may extend either partially or completely through the edge 7 thickness 20, depending upon the spacing requirements of the components contained in 8 the module. Although it is possible to construct the frame to have a single internal cavity, 9 it is possible to also create first and second internal cavities by forming a thin, integrally to molded floor 28 positioned along the centerline of the module thickness.
Two possible 11 embodiments of the molded floor 28 are illustrated in FIGS. 2A and 2B. In FIG. 2A, 12 which is taken along section lines 2A-2A of FIG. 1, the floor 28 is shown molded flush 13 to the second major plane 18. In the embodiment illustrated in FIG. 2B, however, the 14 floor 28 is shown along the centerline of the module thickness to form first and second internal cavities in the interior of the module.
16 A stepped ledge 30 is formed around the circumference of the cavity 14 or cavities 17 to provide a receiving area for the mating composite semiconductor substrate assembly 18 32 described in greater detail below. In the preferred embodiment, the ledge 30 is 19 recessed below either the first major plane 16 or the second major plane 18 such that after 2o the cover plate subassembly 32 is positioned and sealed in place, the outer surfaces of 21 the subassembly 32. and the molded frame 12 are substantially flush to ot~e another.
,~ z144'~4~s , i Alternatively, the ledges may be simple extensions of major plane 16 and/or major plane a 2 18, as illustrated in FIG. 2B, placing the composite semiconductor substrate assembly 32 . 3 further away from the center line of the module thickness, thus allowing more spacing for internal components. In this embodiment, the cover plate sub-assembly 32 would project a short distance above major plane 16 and/or major plane 18.
6 The array of contact pads 22 on the edge of the molded frame 12 provide 7 electrical connection from the external surface edge of the module to an interior stepped 8 ledge 30 of the module cavity 14 or cavities. Arrayed across the interior stepped ledge 9 30 is a multiplicity of smaller termination pads 34, each electrically paired with an 1o associated external contact pad 22. In one embodiment of the invention, each of the 11 contact pads 22 and termination pads 34 are formed by a selective plating process that 12 deposits a conductive metal pattern extending from the edge of the molded frame 12, 13 across the surface of the frame, and down a vertical wall or inclined plane 36, as shown 14 in FIG. 2A and 3, to the surface of the ledge 30 lying a short distance below the first t5 major plane 16 and/or the second major plane 18. Similarly positioned pairs of contact 16 pads 22 and termination pads 34 on the opposite planes of the molded frame 12 can be 17 electrically connected by a shunt 21 across the lower edge of the frame 12, as illustrated 18 in FIG. 2B, or left electrically isolated.
19 Post molded plating techniques that may be commonly employed to produce the 20 mufti-leveled path of electrical conduction include, but are not restricted to, electrolytic 21 or electroless plated copper, nickel, gold, or tin/lead alloys.
These and other pure metals ,,~ ;
1 and alloys may be selectively plated onto the selected portions of the molded frame 12 2 via surface treatment and masking techniques known and available within the molded .
3 PCB industry. Alternatively, various plating processes may be employed separately or combined with screen printable, metal filled inks to produce electrically conductive pads on ceramic or epoxy glass materials.
6 As the need arises for a greater number of signal and data in/out connections than 7 can be accommodated by using conventional plating processes to reduce the contact pad-s width 23 and contact-to-contact pad-pitch 25, as shown in FIG. 3, an increased signal path 9 density can be obtained by integrally molding into frame 12 an array of stamped metal 1o contacts or by inserting stamped metal contacts into receptacles pre-molded in the edge i i of the frame 12, as shown in FIG. 4D. The array of stamped metal contacts comprises 12 a plurality of thin, substantially parallel plates that are closely spaced but electrically 13 insulated from one another by encompassing mold material. These stamped metal 14 contacts have exposed edges extending from the bottom edge of the molded frame 12 across the contact pad surface plane and across the interior stepped ledge on the interior 16 of the frame. The edges of the stamped contacts are substantially flush with the 17 surrounding molded surfaces or project slightly above, except in the area corresponding 18 to the exposed edge of the composite semiconductor substrate sub-assembly 32 where the 19 stamped contact would be recessed into the molded frame to avoid undesirable electrical 2o contact and structural weakening of the molded frame.
21 The above-described electrical contact arrangement can be understood by referring 1 to FIGS. 4A-4C. FIG. 4A is an illustration of an array 36 of individual contact members 2 38. The edges of the individual contacts 38 provide electrical interconnections between 3 the interior and exterior of the frame 12 corresponding to the contact pads 22 and 4 termination pads 34 discussed above. For example, once the array 36 of contacts 38 have been molded or inserted into the edge of the frame 12, as illustrated in FIGS.
4A and 4C, 6 the edges 22' and 34' of the individual contacts 38, shown in FIGS. 4A and 4C, 7 correspond to the respective contact pads 22 and termination pads 34 discussed above in 8 connection with the prior embodiments. FIG. 4C is a cross-sectional illustration of the 9 contacts positioned inside frame 12. This figure also illustrates an additional electrical 1o contact surface resulting from the projection of an end portion 22" of a contact 38 from 11 the edge of the frame 12.
12 Additional embodiments based on the concept of integrally molded or insertable 13 individual contact members 38 as an array 36 can be seen in FIGS. 5 and 6.
Since 14 individual contact members 38 are formed by a stamping process, which does not IS necessitate additional bending or folding steps to form the contacts, simple appendages 16 may be optionally included during stamping of the contacts to customize the contacts for 17 a "through hole" leaded contact 37 or a "surface mount" leaded contact 39.
Adjusting the 18 centerline of the "through hole" lead 3T enables the distance, D, between the adjacent 19 contacts 37 to be adjusted (D') for standard or non-standard hole patterns on the main 20 circuit board as illustrated in FIGS. SB and C, when adjacent contacts in an array are 21 molded or inserted while alternately rotated 180 degrees with respect to each other. By ._ W 94/07264 ~' PCT/US93/08576 O
I molding or inserting "surface mount" leaded contacts 39 in alternating orientations as 2 illustrated in FIGS. 6B and 6C, solder pads on the main circuit board may be optimally ' 3 spaced on alternating sides of the module, and a more stable mounting base is provided with contacts 39. Additional support may be provided at both ends of the molded frame 5 12, as later described in connection with FIG. 7 B, by inserting or molding a formed metal clip or post 41 into the bottom-end of molded frame 12.
7 Use of flat surfaced contact pads 22 located at the bottom edge of the molded s frame 12 is the preferred configuration for this invention for backward compatibility with 9 present SIMM sockets. However, an alternative embodiment of the invention would 10 include formed metal clips over the edge of the molded frame to produce a "leaded"
I I version of the invention for direct solder mounting of the module to a PCB
using either 12 "through-hole" or "surface mount" soldering technology. FIG. 7A is an illustration of the 13 molded frame 12 having a plurality of leads 40 attached to the contact pads 22 for use 14 on a "through hole" soldering attachment. FIG. 7B is an illustration of plurality of leads 40' attached to the contact pads 22 for use in a "surface mount" soldering attachment. In 16 this embodiment of the invention, an end post 42 integrally molded at both extreme ends 17 on the molded frame 12 is included to assist in maintaining proper alignment of the 18 module in the main circuit board during the "surface mount" soldering process. These 19 end posts 42 would typically be molded with differing cross-sectional diameters, i.e., one larger than the other, to mate with appropriately sized holes within the main circuit board, 21 thereby enabling the modules to be correctly oriented and secured against movement ~1~47~0 1 during the soldering process.
2 Details relating to the composite semiconductor substrate sub-assembly 32 will 3 now be discussed by referring again to FIG. 1. The sub-assembly includes a composite 4 substrate 46 which comprises a thin metal cover plate 48 and thin laminate circuit 50 which is bonded to the metal cover plate 48 by a film adhesive 52. The composite 6 substrate 46 provides a rigid mounting surface for the placement of semiconductor devices 7 54 and their associated passive components 56. The composite semiconductor substrate 8 sub-assembly 32 is attached to the molded frame by a rectangular ring 58 formed from 9 an anisotropic, electrically conductive adhesive material.
1o The composite substrate employed in the present invention offers the advantage 11 of allowing the components to be pre-assembled, tested and repaired prior to final 12 attachment into the molded frame 12. In the preferred embodiment, the cover plate 48 t3 is formed from stainless steel and the thin laminate circuit 50 is a multilayered, thin 14 copperlpolyimide flexible circuit. However, materials other than those described above can be substituted for the cover plate 48 and the thin laminate circuit 50.
Alternative 16 material choices for the cover plate 48 include epoxy-glass, ceramic, aluminum, copper-17 nickel alloys and other metal and non-metal rigid structures. The metal materials listed 18 above offer advantages over other material choices, because of their thermal transfer 19 properties. Anti-static and/or electrical shielding properties are also enhanced by the use of a metal cover plate 48. Additional anti-static protection in selective locations may be 21 provided by including anti-static or electrically conductive filler materials in the mold 1 compound when forming the molded frame I2 and/or adding specialized coatings as part 2 of a post molded process. These extra measures would be warranted for static sensitive , 3 or electrically emissive semiconductor devices. In applications involving semiconductor devices switching or operating at frequencies above 50 Mhz., it may be necessary or desirable to establish an electrical ground plane potential across the cover plate 48. This 6 may be readily accomplished by direct electrical contact between one or more specific 7 ground contact pads 22 and the cover plate 48, or through ground connections established 8 directly through the thin laminate circuit 50.
9 Numerous materials may be substituted for the thin laminate circuit 50 without t0 departing from the scope or spirit of the present invention. For instance, thin epoxy-glass I I PCBs, multi-layer ceramic circuit cards, screen printed or vacuum deposited and/or plated 12 thin film chrome/copper/gold or aluminum, over polyimide or polyester film circuits may 13 each be effectively used in place of the preferred flexible circuit. In some instances, a 14 film adhesive 52 may not be required. For example, a thin laminate circuit 50 fabricated IS by sequential deposition of copper/polyimide thin films directly onto the cover plate 48 16 would not require an adhesive. This type of process is generally associated with 17 controlled or matched impedance circuits employing stripline and/or wave guide structures I8 required for high frequency applications.
19 The primary purpose of the thin laminate circuit 50 is to provide electrical 2o interconnection between individual electronic devices 54 or a group of stacked electronic 21 devices mounted on the circuit 50, and to conduct data signals and control voltages to and WO 94/07264 ~ ~ ~ ~ ~ ~ ~ . PCT/US93/08576 I from the termination pads 34 on the molded frame 12. To facilitate transfer of these 2 signals and voltages, a series of electrically conductive substrate pads 60 are arrayed 3 along one or more edges of the thin laminate circuit 50 such that when the composite semiconductor substrate sub-assembly 32 is attached to the molded frame 12, each substrate pad 60 overlays a corresponding termination pad 34 on the molded frame 12.
In an alternate embodiment of the present invention, the thin laminate circuit 7 can be attached on or integrated directly into the floor 28 of the molded frame 12. In this 8 embodiment, the cover plate 48 may include an additional thin laminate circuit. Tab leads 9 or pads arrayed along the edges) of the circuit 50 can then be directly connected or soldered to appropriately sized and placed termination pads 34 along a shorter stepped i I ledge 30 or floor 28 of the molded frame 12. Another embodiment, --principally suitable 12 for a molded frame 12 formed from multiple, stacked, layers of kiln-fired, ceramic sheets 13 imprinted with electrically conductive lines and via pads, -- can incorporate the circuit as 14 an integral part of the floor 28 of the module frame 12, such that the uppermost layer IS constituted the device and component attachment surface. In yet another embodiment of i6 the present invention, the composite semiconductor substrate sub-assembly 32 can be used 17 independently of the molded frame 12 by applying or molding a protective overcoat 70, 18 as shown in FIG. 8, comprising an epoxy or mold compound material covering the 19 semiconductor devices 54, passive components 56 and substantial surface of the thin laminate circuit S0, leaving substrate pads 60, end surfaces 50' and external surface 48' 21 of the cover plate ~ 48 exposed. The resultant composite semiconductor substrate .
WO 94/07264 ~ ~ ''~ PCT/US93/08576 1 subassembly 32 can then be mated to an appropriate socket with slots to receive the end 2 surfaces 50' or combined with a plurality of leads 40 for directly mounting to a main 3 circuit board. An optional embodiment of the module shown in FIG. 8 can combine additional semiconductor devices 54 and other components 56 to the external surface 48' S of the cover plate 48 by applying an additional thin laminate circuit 50 and applying or 6 molding a protective overcoat 70 to the surface 48' also. Thin laminate circuits 50 on 7 either surface of cover plate 48 can be either physically separate and, therefore, 8 electrically independent, or physically and electrically joined along the edges) of cover plate 48 as a single flexible circuit folded over and around said edge(s). In this example, to the module would appear symmetrical with respect to a centerline drawn end-to-end i l through cover plate 48, as shown in FIG. 8B.
12 To lower thermal resistance and, hence, enhance normal thermal conductivity 13 between the contained semiconductor devices and the exterior surface of the module, 14 several features may be optionally incorporated as part of the thin laminate circuit 50.
15 Maximum thermal conduction may be achieved by incorporating open windows 62 within 16 the thin laminate circuit 50 and if present, adhesive 52, to allow backside chip attachment 17 directly to the cover plate 48, as shown in FIG. 9. Chip attachment can be accomplished t8 using eutectic alloying materials (e.g., solder), metal filled epoxy or other thermally 19 conductive adhesives. This technique would preferably be performed on a cover plate 48 20 formed from material exhibiting the same or approximate coefficient of thermal expansion 21 as the chip devices attached thereon to promote better mechanical reliability of the WO 94/07264 ~ ~ ~ 4 7 4 0 . p~/US93/08576 I5 ' 1 attachment bondline. An alternative approach to lower thermal resistance makes use of 2 small thermal vias 64 formed as an integral part of the thin laminate circuit 50.
3 Strategically arrayed under selective chip mounting sites, as shown in FIG.
10A, these structures provided either solid conductive posts or small openings through the circuit 50 and adhesives 52, into which a thermally conductive material may be emplaced, bringing 6 intimate thermal, metal-to-silicon, contact between the cover plate 48 and semiconductor 7 device 54 at localized areas beneath semiconductor devices 54. Another enhancement 8 of thermal convection, or transfer of heat into the ambient air surrounding the module, 9 involves the incorporation into the external surface 48' of the cover plate 48, a knurled surface finish 66 or uniform array of small polygon structures 68 impressed into the i i surface, for the purpose of increasing the total external surface area of the cover plate 48, 12 as shown in FIG. 11.
t3 Electrical and mechanical mating between the composite semiconductor substrate 14 subassembly 32 and the molded frame 12 is accomplished by one of several methods.
1S In the preferred embodiment, an anisotropic, electrically conductive, adhesive film 58 -16 available from several manufacturers - is pre-positioned as either a preform or pre-17 dispensed, stenciled or transfer stamped in liquid form and dried in place on either the i8 composite semiconductor substrate subassembly 32 or molded frame 12, and subsequently 19 activated by thermal and/or pressure contact in accordance with the manufacturer's 2o instructions. Alternatively, a solderable alloy combined with a thermal setting adhesive 21 may be selectively applied around the ledge 30 and across the pads 34 and thermally t S.
WO 94/07264 ~ ~ PGT/US93/08576 i activated to effect both a mechanical and electrical interconnect. Yet another material that 2 may be substituted is commonly referred to as a'z-axis elastomeric conductor', which may 3 be fashioned from a material with adhesive properties to effect simultaneous mechanical and electrical attachment between the composite semiconductor substrate subassembly 32 and the molded frame 12.
6 Semiconductor device attachment to the thin laminate circuit 50 is achieved by one '7 of several methods commonly known and available with the industry. Tape Automated 8 Bonding (TAB) technology provides a network of tab leads 72 attached to metallurgical 9 bumps on specific device bondpads, which are elevated from the surface and which to extend beyond the perimeter of the silicon device, as shown in FIG. 9. The free ends of 11 the tab leads may be mechanically/electrically bonded to appropriately spaced and 12 metallurgically compatible bond sites on the laminate circuit 50 with the silicon devices) 13 configured in either a face-up or face-down configuration. Alternatively, the device may 14 be attached using 'Chip On Board' (COB) technology where the chip is mounted with an epoxy paste or solder alloy in a face-up orientation, and electrically connected to the 16 laminate circuit 50 with conventional wire-bonds. Yet another, and preferred technique, 17 shown in FIGS. 10 and 12, is known as Flip Chip Assembly or Direct Chip Attach 18 (DCA). In this example, suitably sized bond pads 74 on the face of the chips) are 19 directly attached to matching pads 76 on the laminated circuit 50 with one of several techniques and materials. Examples include 'Controlled Collapse Chip Connection' ("C4") 21 soldering technology developed and licensed by IBM, conductive epoxies, solder-ball I reflow, and anisotropic conductive adhesives. Typically this chip mounting methodology 2 is combined with specific chip undercoating materials to enhance mechanical reliability, 3 hermeticity and/or thermal conductivity.
A variety of semiconductor devices may be readily assembled into the module of the present invention by careful tailoring of the molded frame 12 and the composite 6 semiconductor substrate subassembly 32 Typical devices include, but are not limited to, 7 Memory chips (DRAM, AS-DRAMS, Flash-EEprom, ROM, Fast/Slow-Static RAMS, 8 Ferro-magnetic RAM, et. aI.), Microprocessor, Application Specific IC's, Gate Array 9 devices, Telecommunication IC's and others manufactured in CMOS, BiCMOS, and other to technologies compatible with TTL, ECL, FAST and other logic interface standards. Since 11 DRAM and other memory device types are generally used in large quantities in typical 12 computing applications and require a proportionately large share of the volumetric 13 mounting capacity available, it is expected that these devices will predominate in this 14 _ invention. A significant performance and density gain may be achieved by combining this IS invention with stacked memory chips 52, shown in FIG. 12, supplied by Ervine Sensors 16 Corp. of Costa Mesa, CA. These stacked chips are pre-processed through a back-lapping 17 operation to substantially reduce their individual thickness, and are subsequently bonded 18 together to form short, vertical, interconnected, 3-D stacks that may then be directly face-19 bonded (DCA or Flip Chip mounted) to the thin laminate circuit 50 as described above.
2o This technique may be warranted for computationally intensive or space limited 21 applications. In addition to the variety of semiconductor devices that may find 1 application in this invention, associated passive electronic components 56, including chip 2 capacitors, resistors, etc., may also be surface mount soldered onto the thin laminate -3 circuit. Chip de coupling capacitors are used in particular with memory devices to a function in the suppression of spurious voltage spikes when electrically connected between a net positive or negative voltage reference and electrical ground.
For most 6 applications, these passive components are expected to stand slightly above the mounted 7 height of the adjacent semiconductor devices, as shown in FIG. 8B. Since these 8 components are generally composed of a robust ceramic material, they may be 9 advantageously employed to prevent direct pressure from being applied against the fragile to semiconductor devices should the assembled module be compressed in an axis 11 perpendicular to the first major plane 16 and/or the second major plane 18 of molded 12 frame 12. Alternatively, special raised stand-off features may be integrally molded into 13 the floor 28 of the molded frame 12, surrounding the areas reserved for the semiconductor i.s devices, to prevent damage resulting from compressional forces.
In its final form, the composite semiconductor substrate sub-assembly 32 total 16 thickness, including semiconductor devices and passive components, would generally 17 range from 0.010-0.040 inches in order to fct within the present 0.050-inch standard 18 SIMM module thickness specification. However, in other applications, the total thickness 19 may be appropriately increased to provide additional space for the mounted devices and components.
21 In instances where two composite semiconductor substrate subassemblies 32 are ~~.44740 1 attached to the molded frame 12, as shown in FIG. 13, - one in the first major plane and 2 another in the second major plane, the floor 28 can be hollowed or eliminated to increase 3 the available spacing between mounted devices and components. (Substrate-to-substrate electrical interconnect is normally provided via electrical shunting of the contact pads 22 across the bottom edge 20 of the molded frame 12. However, additional interconnections 5 may be facilitated around the entire perimeter of the internal stepped ledge 30 or edge of 7 molded frame 12 opposite contacts 22 (top edge of frame), similar to contacts 22.) In 8 this embodiment, signal communication between opposite and opposing composite 9 subassemblies 32 can be established via light emitting/receiving, point-to-point data/signal communication across the narrow air gap between juxtaposed semiconductor 11 devices - accurately positioned to face one another - thereby eliminating the necessity for 12 long crossover electrical paths through the thin laminate circuits 50 and across the stepped 13 ledge 30 or edges 20. Since it is expected that semiconductor or other electronic devices 14 employing light emitting/receiving structures on their respective surfaces or edges may eventually become a practical alternative for chip-to-chip communication, this invention t6 may become the preferred multichip package for shielding these components in a 17 compact, "light safe" enclosure.
18 Yet another alternate embodiment of the present invention includes the injection 19 or dispensing of a semi-rigid compound or elastomeric material to fill all or part of the volumetric void between adjacent composite semiconductor substrate subassemblies 32 2~ and/or floor 28 to improve the overall rigidity and mechanical integrity of the finished WO 94/07264 ' PCT/US93/08576 1 assembly. This technique also improves the hermeticity or moisture resistance of the 2 module. Additional manufacturing steps to improve hermeticity at the component or 3 semiconductor device level include special chip surface coatings or undercoatings - ..
depending upon device orientation and application methodology - including, but not 5 limited to organic epoxies (ex. "Praleen"~', die undercoating adhesives, etc.), 5 vacuum/plasma deposited ceramic or diamond coatings, moisture immobilized polyimide 7 and other suitable materials known within the industry.
8 The improved multichip module of the present invention offers numerous 9 advantages over the prior art. For example, the present invention provides a significant to decrease in cross-sectional thickness and overall weight reduction for the module as a 11 whole, thereby improving the total net packing density and making the module more 12 appealing for light-weight portable applications. Since this invention is approximately 13 one-third of the thickness of a standard SOJ-type SIMM, it is feasible to mount two or t4 three times more component modules within a specified area of the circuit board as 15 compared to the prior art. The present invention provides for mechanical protection of 16 fragile bare silicon devices by enclosing these devices inside the module, leaving no 17 exposed components. The exterior surfaces, therefore, are free of all obstructions which 1s may become damaged during handling or which may inhibit the placement of printed 19 information (ex. manufacturer's name, logo, date code, pan number, patent number, bar 2o code, etc.). Modules free of externally mounted components also simplify the design of 21 shipping trays and facilitates robotic handling and placement at the final end-users 1 manufacturing line. Although backward compatible with existing SIMM sockets and 2 therefore directly replaceable with conventional SOJ-type SIMMs, this invention is also 3 capable of mating with newer sockets - presently in development - that will mount the a modules closer together.
Though semiconductor memory devices occupy the vast majority of the module 6 market today, there is also a growing requirement to modularize other semiconductor 7 components including, but not limited to, microprocessor, application specific integrated 8 circuits, telecommunication and other device types. Accordingly, the present invention 9 provides an upgrade path for a greater number of interconnect pins/pads and improves the to thermal dissipation characteristics over present day microelectronic device modules.
1 t The molded frame 12 employed in the module of the present invention offers 12 significant improvements over prior art electronic packaging systems, including those 13 associated with currently available SIMM memory modules which employ conventional 14 printed circuit board (PCB) materials. A majority of SIMM connecting sockets in usage today, require the module thickness to be tightly controlled across the edge contacts, for 16 the module-socket combination to function reliably if the module is frequently inserted 1~ and removed from the socket. Standard lamination processes used in the construction of 18 PCB's, result in large thickness variations which are difficult to control.
This variation 19 in SIMM thickness directly effects the contact pad pressure inside the socket, and has been identified as a frequent cause of intermittent electrical failures.
Current practice 21 requires rigorous inspection procedures, adding to the material costs, in order to prevent WO 94/07264 ~ rt ~ ~; PCT/US93/08576 1 the inclusion of "out-of spec" SIMM substrates into the manufacturing line.
Substituting 2 a molded frame for this critical component of the module provides for more consistent 3 dimensional control across the contact pads and eliminate the necessity for I00%
inspection.
An additional benefit gained from a molded frame is the ability to mold custom 6 features on the module housing that are presently impractical with laminate PCBs.
7 Examples of potential molded features include special locking mechanisms designed to 8 mate with appropriate structures on the socket, finger grips, keying mechanisms and hold 9 fasts.
Although the method and apparatus of the present invention has been described I1 in connection with the preferred embodiment, it is not intended to be limited to the 12 specific form set forth herein, but on the contrary, it is intended to cover such alternatives, 13 modifications, and equivalents, as can be reasonably included within the spirit and scope 14 of the invention as defined by the appended claims.
3 Strategically arrayed under selective chip mounting sites, as shown in FIG.
10A, these structures provided either solid conductive posts or small openings through the circuit 50 and adhesives 52, into which a thermally conductive material may be emplaced, bringing 6 intimate thermal, metal-to-silicon, contact between the cover plate 48 and semiconductor 7 device 54 at localized areas beneath semiconductor devices 54. Another enhancement 8 of thermal convection, or transfer of heat into the ambient air surrounding the module, 9 involves the incorporation into the external surface 48' of the cover plate 48, a knurled surface finish 66 or uniform array of small polygon structures 68 impressed into the i i surface, for the purpose of increasing the total external surface area of the cover plate 48, 12 as shown in FIG. 11.
t3 Electrical and mechanical mating between the composite semiconductor substrate 14 subassembly 32 and the molded frame 12 is accomplished by one of several methods.
1S In the preferred embodiment, an anisotropic, electrically conductive, adhesive film 58 -16 available from several manufacturers - is pre-positioned as either a preform or pre-17 dispensed, stenciled or transfer stamped in liquid form and dried in place on either the i8 composite semiconductor substrate subassembly 32 or molded frame 12, and subsequently 19 activated by thermal and/or pressure contact in accordance with the manufacturer's 2o instructions. Alternatively, a solderable alloy combined with a thermal setting adhesive 21 may be selectively applied around the ledge 30 and across the pads 34 and thermally t S.
WO 94/07264 ~ ~ PGT/US93/08576 i activated to effect both a mechanical and electrical interconnect. Yet another material that 2 may be substituted is commonly referred to as a'z-axis elastomeric conductor', which may 3 be fashioned from a material with adhesive properties to effect simultaneous mechanical and electrical attachment between the composite semiconductor substrate subassembly 32 and the molded frame 12.
6 Semiconductor device attachment to the thin laminate circuit 50 is achieved by one '7 of several methods commonly known and available with the industry. Tape Automated 8 Bonding (TAB) technology provides a network of tab leads 72 attached to metallurgical 9 bumps on specific device bondpads, which are elevated from the surface and which to extend beyond the perimeter of the silicon device, as shown in FIG. 9. The free ends of 11 the tab leads may be mechanically/electrically bonded to appropriately spaced and 12 metallurgically compatible bond sites on the laminate circuit 50 with the silicon devices) 13 configured in either a face-up or face-down configuration. Alternatively, the device may 14 be attached using 'Chip On Board' (COB) technology where the chip is mounted with an epoxy paste or solder alloy in a face-up orientation, and electrically connected to the 16 laminate circuit 50 with conventional wire-bonds. Yet another, and preferred technique, 17 shown in FIGS. 10 and 12, is known as Flip Chip Assembly or Direct Chip Attach 18 (DCA). In this example, suitably sized bond pads 74 on the face of the chips) are 19 directly attached to matching pads 76 on the laminated circuit 50 with one of several techniques and materials. Examples include 'Controlled Collapse Chip Connection' ("C4") 21 soldering technology developed and licensed by IBM, conductive epoxies, solder-ball I reflow, and anisotropic conductive adhesives. Typically this chip mounting methodology 2 is combined with specific chip undercoating materials to enhance mechanical reliability, 3 hermeticity and/or thermal conductivity.
A variety of semiconductor devices may be readily assembled into the module of the present invention by careful tailoring of the molded frame 12 and the composite 6 semiconductor substrate subassembly 32 Typical devices include, but are not limited to, 7 Memory chips (DRAM, AS-DRAMS, Flash-EEprom, ROM, Fast/Slow-Static RAMS, 8 Ferro-magnetic RAM, et. aI.), Microprocessor, Application Specific IC's, Gate Array 9 devices, Telecommunication IC's and others manufactured in CMOS, BiCMOS, and other to technologies compatible with TTL, ECL, FAST and other logic interface standards. Since 11 DRAM and other memory device types are generally used in large quantities in typical 12 computing applications and require a proportionately large share of the volumetric 13 mounting capacity available, it is expected that these devices will predominate in this 14 _ invention. A significant performance and density gain may be achieved by combining this IS invention with stacked memory chips 52, shown in FIG. 12, supplied by Ervine Sensors 16 Corp. of Costa Mesa, CA. These stacked chips are pre-processed through a back-lapping 17 operation to substantially reduce their individual thickness, and are subsequently bonded 18 together to form short, vertical, interconnected, 3-D stacks that may then be directly face-19 bonded (DCA or Flip Chip mounted) to the thin laminate circuit 50 as described above.
2o This technique may be warranted for computationally intensive or space limited 21 applications. In addition to the variety of semiconductor devices that may find 1 application in this invention, associated passive electronic components 56, including chip 2 capacitors, resistors, etc., may also be surface mount soldered onto the thin laminate -3 circuit. Chip de coupling capacitors are used in particular with memory devices to a function in the suppression of spurious voltage spikes when electrically connected between a net positive or negative voltage reference and electrical ground.
For most 6 applications, these passive components are expected to stand slightly above the mounted 7 height of the adjacent semiconductor devices, as shown in FIG. 8B. Since these 8 components are generally composed of a robust ceramic material, they may be 9 advantageously employed to prevent direct pressure from being applied against the fragile to semiconductor devices should the assembled module be compressed in an axis 11 perpendicular to the first major plane 16 and/or the second major plane 18 of molded 12 frame 12. Alternatively, special raised stand-off features may be integrally molded into 13 the floor 28 of the molded frame 12, surrounding the areas reserved for the semiconductor i.s devices, to prevent damage resulting from compressional forces.
In its final form, the composite semiconductor substrate sub-assembly 32 total 16 thickness, including semiconductor devices and passive components, would generally 17 range from 0.010-0.040 inches in order to fct within the present 0.050-inch standard 18 SIMM module thickness specification. However, in other applications, the total thickness 19 may be appropriately increased to provide additional space for the mounted devices and components.
21 In instances where two composite semiconductor substrate subassemblies 32 are ~~.44740 1 attached to the molded frame 12, as shown in FIG. 13, - one in the first major plane and 2 another in the second major plane, the floor 28 can be hollowed or eliminated to increase 3 the available spacing between mounted devices and components. (Substrate-to-substrate electrical interconnect is normally provided via electrical shunting of the contact pads 22 across the bottom edge 20 of the molded frame 12. However, additional interconnections 5 may be facilitated around the entire perimeter of the internal stepped ledge 30 or edge of 7 molded frame 12 opposite contacts 22 (top edge of frame), similar to contacts 22.) In 8 this embodiment, signal communication between opposite and opposing composite 9 subassemblies 32 can be established via light emitting/receiving, point-to-point data/signal communication across the narrow air gap between juxtaposed semiconductor 11 devices - accurately positioned to face one another - thereby eliminating the necessity for 12 long crossover electrical paths through the thin laminate circuits 50 and across the stepped 13 ledge 30 or edges 20. Since it is expected that semiconductor or other electronic devices 14 employing light emitting/receiving structures on their respective surfaces or edges may eventually become a practical alternative for chip-to-chip communication, this invention t6 may become the preferred multichip package for shielding these components in a 17 compact, "light safe" enclosure.
18 Yet another alternate embodiment of the present invention includes the injection 19 or dispensing of a semi-rigid compound or elastomeric material to fill all or part of the volumetric void between adjacent composite semiconductor substrate subassemblies 32 2~ and/or floor 28 to improve the overall rigidity and mechanical integrity of the finished WO 94/07264 ' PCT/US93/08576 1 assembly. This technique also improves the hermeticity or moisture resistance of the 2 module. Additional manufacturing steps to improve hermeticity at the component or 3 semiconductor device level include special chip surface coatings or undercoatings - ..
depending upon device orientation and application methodology - including, but not 5 limited to organic epoxies (ex. "Praleen"~', die undercoating adhesives, etc.), 5 vacuum/plasma deposited ceramic or diamond coatings, moisture immobilized polyimide 7 and other suitable materials known within the industry.
8 The improved multichip module of the present invention offers numerous 9 advantages over the prior art. For example, the present invention provides a significant to decrease in cross-sectional thickness and overall weight reduction for the module as a 11 whole, thereby improving the total net packing density and making the module more 12 appealing for light-weight portable applications. Since this invention is approximately 13 one-third of the thickness of a standard SOJ-type SIMM, it is feasible to mount two or t4 three times more component modules within a specified area of the circuit board as 15 compared to the prior art. The present invention provides for mechanical protection of 16 fragile bare silicon devices by enclosing these devices inside the module, leaving no 17 exposed components. The exterior surfaces, therefore, are free of all obstructions which 1s may become damaged during handling or which may inhibit the placement of printed 19 information (ex. manufacturer's name, logo, date code, pan number, patent number, bar 2o code, etc.). Modules free of externally mounted components also simplify the design of 21 shipping trays and facilitates robotic handling and placement at the final end-users 1 manufacturing line. Although backward compatible with existing SIMM sockets and 2 therefore directly replaceable with conventional SOJ-type SIMMs, this invention is also 3 capable of mating with newer sockets - presently in development - that will mount the a modules closer together.
Though semiconductor memory devices occupy the vast majority of the module 6 market today, there is also a growing requirement to modularize other semiconductor 7 components including, but not limited to, microprocessor, application specific integrated 8 circuits, telecommunication and other device types. Accordingly, the present invention 9 provides an upgrade path for a greater number of interconnect pins/pads and improves the to thermal dissipation characteristics over present day microelectronic device modules.
1 t The molded frame 12 employed in the module of the present invention offers 12 significant improvements over prior art electronic packaging systems, including those 13 associated with currently available SIMM memory modules which employ conventional 14 printed circuit board (PCB) materials. A majority of SIMM connecting sockets in usage today, require the module thickness to be tightly controlled across the edge contacts, for 16 the module-socket combination to function reliably if the module is frequently inserted 1~ and removed from the socket. Standard lamination processes used in the construction of 18 PCB's, result in large thickness variations which are difficult to control.
This variation 19 in SIMM thickness directly effects the contact pad pressure inside the socket, and has been identified as a frequent cause of intermittent electrical failures.
Current practice 21 requires rigorous inspection procedures, adding to the material costs, in order to prevent WO 94/07264 ~ rt ~ ~; PCT/US93/08576 1 the inclusion of "out-of spec" SIMM substrates into the manufacturing line.
Substituting 2 a molded frame for this critical component of the module provides for more consistent 3 dimensional control across the contact pads and eliminate the necessity for I00%
inspection.
An additional benefit gained from a molded frame is the ability to mold custom 6 features on the module housing that are presently impractical with laminate PCBs.
7 Examples of potential molded features include special locking mechanisms designed to 8 mate with appropriate structures on the socket, finger grips, keying mechanisms and hold 9 fasts.
Although the method and apparatus of the present invention has been described I1 in connection with the preferred embodiment, it is not intended to be limited to the 12 specific form set forth herein, but on the contrary, it is intended to cover such alternatives, 13 modifications, and equivalents, as can be reasonably included within the spirit and scope 14 of the invention as defined by the appended claims.
Claims (42)
1. A semiconductor module, comprising:
a frame having major opposed coplanar surfaces arranged coplanar with an in-tegrally formed floor member defining an interior portion;
a plurality of electrical contacts along an edge of said frame extending coplanar with said surfaces;
a composite substrate comprising: a circuit layer, a substrate cover plate, and means for adhering said circuit layer to said substrate cover plate;
a plurality of electrical contacts along an edge of said frame;
a plurality of semiconductor devices mounted to said composite substrate to form a composite semiconductor substrate subassembly, wherein said composite substrate is attached to said frame such that at least a portion of said composite semiconductor substrate sub-assembly is received in said interior portion of said frame and wherein said plurality of semiconductor devices are electrically coupled together; and electrical connecting means for electrically connecting said semiconductor devices on said composite substrate to said electrical contacts on said edge of said frame.
a frame having major opposed coplanar surfaces arranged coplanar with an in-tegrally formed floor member defining an interior portion;
a plurality of electrical contacts along an edge of said frame extending coplanar with said surfaces;
a composite substrate comprising: a circuit layer, a substrate cover plate, and means for adhering said circuit layer to said substrate cover plate;
a plurality of electrical contacts along an edge of said frame;
a plurality of semiconductor devices mounted to said composite substrate to form a composite semiconductor substrate subassembly, wherein said composite substrate is attached to said frame such that at least a portion of said composite semiconductor substrate sub-assembly is received in said interior portion of said frame and wherein said plurality of semiconductor devices are electrically coupled together; and electrical connecting means for electrically connecting said semiconductor devices on said composite substrate to said electrical contacts on said edge of said frame.
2. The semiconductor module according to claim 1, said frame having a generally rectangular shape with first and second major planes, said interior portion being defined by a generally rectangular aperture.
3. The semiconductor module according to claim 1, wherein said substrate cover plate has heat dissipation properties, said substrate cover plate being in thermal communication with said semiconductor devices to conduct thermal energy therefrom.
4. A semiconductor module, comprising:
(a) a frame having major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion, said interior portion being defined by an aperture;
(b) a plurality of electrical contacts along an edge of said frame extending coplanar with said surfaces;
(c) a composite semiconductor substrate sub-assembly including a composite substrate and a plurality of semiconductor devices mounted to said composite substrate, said composite substrate comprising:
(i) a circuit layer comprising a plurality of circuit traces for providing electrical interconnection between said semiconductor devices;
(ii) a substrate cover plate; and (iii) means for adhering said circuit layer to said substrate cover plate;
wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface and wherein said bottom surface of said composite substrate is connected to said frame such that said bottom surface faces said interim portion of said frame and wherein at least a portion of said composite semiconductor substrate sub-assembly is received in said interior portion of said frame; and (d) electrical connecting means for electrically connecting said semiconductor devices on said composite semiconductor substrate sub-assembly to said electrical contacts on said edge of said frame.
(a) a frame having major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion, said interior portion being defined by an aperture;
(b) a plurality of electrical contacts along an edge of said frame extending coplanar with said surfaces;
(c) a composite semiconductor substrate sub-assembly including a composite substrate and a plurality of semiconductor devices mounted to said composite substrate, said composite substrate comprising:
(i) a circuit layer comprising a plurality of circuit traces for providing electrical interconnection between said semiconductor devices;
(ii) a substrate cover plate; and (iii) means for adhering said circuit layer to said substrate cover plate;
wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface and wherein said bottom surface of said composite substrate is connected to said frame such that said bottom surface faces said interim portion of said frame and wherein at least a portion of said composite semiconductor substrate sub-assembly is received in said interior portion of said frame; and (d) electrical connecting means for electrically connecting said semiconductor devices on said composite semiconductor substrate sub-assembly to said electrical contacts on said edge of said frame.
5. A semiconductor carrier comprising:
(a) a generally rectangular perimeter frame member having side portions and major opposed coplanar surfaces arranged coplanar with an integrally formed floor portion forming a cavity for receiving at least a portion of a semi-conductor substrate;
(b) a plurality of electrical contacts associated with a portion of said perimeter frame member extending coplanar with said surfaces;
(c) a semiconductor substrate sub-assembly including a composite substrate comprising a cover plate and a laminate circuit applied to the cover plate and a plurality of spaced apart semiconductor devices mounted to the composite substrate, wherein said plurality of semiconductor devices are electrically coupled together;
(d) wherein said substrate sub-assembly is connected to said frame member such that a portion of said substrate sub-assembly is received in said cavity of the frame member but does not contact said floor portion of said cavity, and (e) means for electrically connecting said semiconductor devices of said substrate sub-assembly to the electrical contacts on said perimeter frame member.
(a) a generally rectangular perimeter frame member having side portions and major opposed coplanar surfaces arranged coplanar with an integrally formed floor portion forming a cavity for receiving at least a portion of a semi-conductor substrate;
(b) a plurality of electrical contacts associated with a portion of said perimeter frame member extending coplanar with said surfaces;
(c) a semiconductor substrate sub-assembly including a composite substrate comprising a cover plate and a laminate circuit applied to the cover plate and a plurality of spaced apart semiconductor devices mounted to the composite substrate, wherein said plurality of semiconductor devices are electrically coupled together;
(d) wherein said substrate sub-assembly is connected to said frame member such that a portion of said substrate sub-assembly is received in said cavity of the frame member but does not contact said floor portion of said cavity, and (e) means for electrically connecting said semiconductor devices of said substrate sub-assembly to the electrical contacts on said perimeter frame member.
6. The semiconductor module according to claim 1, wherein said composite semiconductor substrate sub-assembly has a thickness ranging between .010 and .040 inches.
7. The semiconductor module according to claim 1, wherein said semiconductor module has a thickness of approximately .050 inches.
8. The module of claim 1, wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface;
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
9. The module of claim 8, wherein said bottom surface of said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame, wherein said semiconductor devices do not contact said interior portion of said frame.
10. The module of claim 8 , wherein said top surface of said composite substrate is external to the module.
11. The module of claim 1, wherein said means affixing said cover plate to said circuit layer comprises a film adhesive positioned between said cover plate and said circuit layer which bonds said circuit layer to said cover plate.
12. The module of claim 1, wherein said circuit layer circuit includes windows to enhance thermal conduction from said semiconductor devices to said cover plate.
13. The module of claim 1, wherein said circuit layer includes thermal vias to enhance thermal conduction from said semiconductor devices to said cover plate.
14. The module of claim 1 or 4, wherein said frame includes a stepped ledge in said interior portion for receiving substrate sub-assembly to said stepped ledge of said frame.
15. The module of claim 14, wherein said means to mount said substrate subassembly to said frame comprises a rectangular ring including an anisotropic, electrically conducting material which mechanically and electrically connects said composite substrate and said frame.
16. The module of claim 1, wherein said semiconductor devices include one or more stacks of semiconductor devices mounted at various locations on said composite substrate.
17. The module of claim 1, wherein said plurality of electrical contacts on said frame are adapted for mating with a single in-line memory module socket.
18. The module of claim 1, wherein said frame and said plurality of electrical contacts disposed on said frame are adapted for mating with a single in-line memory module socket.
19. A semiconductor module, comprising:
a frame having major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion;
a plurality of electrical contacts along an edge of said frame extending coplanar with said surfaces;
a composite semiconductor substrate sub-assembly having a plurality of semiconductor devices mounted thereon, wherein said composite semiconductor substrate sub-assembly is received in said interior portion of said frame and wherein said plurality of semiconductor devices are electrically coupled together, and wherein said composite semiconductor substrate sub-assembly has a thickness ranging between .010 and .040 inches; and electrical connecting means for electrically connecting said semiconductor devices on said composite semiconductor substrate sub-assembly to said electrical contacts on said edge of said frame.
a frame having major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion;
a plurality of electrical contacts along an edge of said frame extending coplanar with said surfaces;
a composite semiconductor substrate sub-assembly having a plurality of semiconductor devices mounted thereon, wherein said composite semiconductor substrate sub-assembly is received in said interior portion of said frame and wherein said plurality of semiconductor devices are electrically coupled together, and wherein said composite semiconductor substrate sub-assembly has a thickness ranging between .010 and .040 inches; and electrical connecting means for electrically connecting said semiconductor devices on said composite semiconductor substrate sub-assembly to said electrical contacts on said edge of said frame.
20. The module of claim 19, wherein said composite semiconductor substrate subassembly comprises a composite substrate and a plurality of semiconductor devices mounted to said composite substrate;
wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame.
wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame.
21. The module of claim 20, wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface;
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
22. The module of claim 21, wherein said bottom surface of said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame, wherein said semiconductor devices do not contact said interior portion of said frame.
23. The module of claim 20, wherein said composite substrate comprises:
a substrate cover plate; and a circuit layer attached to said substrate cover plate.
a substrate cover plate; and a circuit layer attached to said substrate cover plate.
24. The module of claim 20, wherein said frame and said plurality of electrical contacts disposed on said frame are adapted for mating with a single in-line memory module socket.
25. A semiconductor module, comprising:
a frame having major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion;
a plurality of electrical contacts along an edge of said frame extending coplanar with said surface;
a composite semiconductor substrate sub-assembly having a plurality of semiconductor devices mounted thereon, wherein said composite semiconductor substrate sub-assembly is received in said interior portion of said frame and wherein said plurality of semiconductor devices are electrically coupled together, and electrical connecting means for electrically connecting said semiconductor devices on said composite semiconductor substrate subassembly to said electrical contacts on said edge of said frame, wherein said semiconductor module has a thickness of approximately .050 inches.
a frame having major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion;
a plurality of electrical contacts along an edge of said frame extending coplanar with said surface;
a composite semiconductor substrate sub-assembly having a plurality of semiconductor devices mounted thereon, wherein said composite semiconductor substrate sub-assembly is received in said interior portion of said frame and wherein said plurality of semiconductor devices are electrically coupled together, and electrical connecting means for electrically connecting said semiconductor devices on said composite semiconductor substrate subassembly to said electrical contacts on said edge of said frame, wherein said semiconductor module has a thickness of approximately .050 inches.
26. The module of claim 25, wherein said composite semiconductor substrate subassembly comprises a composite substrate and a plurality of semiconductor devices mounted to said composite substrate;
wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame.
wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame.
27. The module of claim 26, wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface;
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
28. The module of claim 30, wherein said bottom surface of said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame, wherein said semiconductor devices do not contact said interior portion of said frame.
29. The module of claim 26, wherein said composite substrate comprises:
a substrate cover plate; and a circuit layer attached to said substrate cover plate.
a substrate cover plate; and a circuit layer attached to said substrate cover plate.
30. The module of claim 25, wherein said frame and said plurality of electrical contacts disposed on said frame are adapted for mating with a single in-line memory module socket.
31. A thin multichip module, comprising, in combination:
a frame defining major opposed coplanar surfaces arranged coplanar with an in-tegrally formed interior portion;
a plurality of electrical contacts disposed on said frame extending coplanar with said surface;
a composite substrate comprising a cover plate portion having heat dissipation capabilities, a thin laminate circuit, and means affixing said cover plate to said thin laminate circuit;
semiconductor devices mounted on said composite substrate to form a substrate sub-assembly, wherein said semiconductor devices are in electrical connection with said laminate circuit and in thermal proximity to said cover plate; and mounting means for mounting said composite substrate to said frame whereby at least a portion of said substrate assembly is maintained within said interior portion of the frame and the substrate sub-assembly is in electrical communication with said electrical contacts on said frame.
a frame defining major opposed coplanar surfaces arranged coplanar with an in-tegrally formed interior portion;
a plurality of electrical contacts disposed on said frame extending coplanar with said surface;
a composite substrate comprising a cover plate portion having heat dissipation capabilities, a thin laminate circuit, and means affixing said cover plate to said thin laminate circuit;
semiconductor devices mounted on said composite substrate to form a substrate sub-assembly, wherein said semiconductor devices are in electrical connection with said laminate circuit and in thermal proximity to said cover plate; and mounting means for mounting said composite substrate to said frame whereby at least a portion of said substrate assembly is maintained within said interior portion of the frame and the substrate sub-assembly is in electrical communication with said electrical contacts on said frame.
32. The module of claim 31, wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface;
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
33. The module of claim 32, wherein said bottom surface of said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame, wherein said semiconductor devices do not contact said interior portion of said frame.
34. A thin multichip module, comprising, in combination:
a frame defining major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion;
a plurality of electrical contacts disposed on said frame extending coplanar with said surface;
a composite substrate comprising a cover plate portion having heat dissipation capabilities and a thin laminate circuit attached to said cover plate portion, wherein said composite substrate is attached to said frame, and wherein the laminate circuit is in electrical communication with said electrical contacts on said frame;
semiconductor devices mounted on said composite substrate such that portions of said semiconductor devices are maintained within said interior portion of the frame, wherein said semiconductor devices are in electrical connection with said laminate circuit and in thermal proximity to said cover plate.
a frame defining major opposed coplanar surfaces arranged coplanar with an integrally formed interior portion;
a plurality of electrical contacts disposed on said frame extending coplanar with said surface;
a composite substrate comprising a cover plate portion having heat dissipation capabilities and a thin laminate circuit attached to said cover plate portion, wherein said composite substrate is attached to said frame, and wherein the laminate circuit is in electrical communication with said electrical contacts on said frame;
semiconductor devices mounted on said composite substrate such that portions of said semiconductor devices are maintained within said interior portion of the frame, wherein said semiconductor devices are in electrical connection with said laminate circuit and in thermal proximity to said cover plate.
35. The module of claim34, wherein said composite substrate includes top and bottom surfaces and said semiconductor devices are mounted to said bottom surface;
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
and wherein said bottom surface of said composite substrate is attached to said frame such that said bottom surface faces said interior portion of said frame.
36. The module of claim 35, wherein said bottom surface of said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said interior portion of said frame, wherein said semiconductor devices do not contact said interior portion of said frame.
37. A semiconductor module comprising:
a frame having a member defining first and second cavities on opposite sides of said member;
a plurality of electrical contacts on an edge of said frame;
a first composite semiconductor substrate subassembly having a plurality of semiconductor devices mounted thereon, wherein said first composite semiconductor substrate subassembly is received in said first cavity of said frame and wherein said first composite semiconductor substrate subassembly has a thickness ranging between .010 and .040 inches;
a second composite semiconductor substrate subassembly having a plurality of semiconductor devices mounted thereon, wherein said second composite semiconductor substrate subassembly is received in said second cavity of said frame and wherein said second composite semiconductor substrate subassembly has a thickness ranging between .010 and .040 inches;
and electrical connecting means for electrically connecting said semiconductor devices on said first and second composite semiconductor substrate sub-assemblies to said electrical contacts on said edge of said frame.
a frame having a member defining first and second cavities on opposite sides of said member;
a plurality of electrical contacts on an edge of said frame;
a first composite semiconductor substrate subassembly having a plurality of semiconductor devices mounted thereon, wherein said first composite semiconductor substrate subassembly is received in said first cavity of said frame and wherein said first composite semiconductor substrate subassembly has a thickness ranging between .010 and .040 inches;
a second composite semiconductor substrate subassembly having a plurality of semiconductor devices mounted thereon, wherein said second composite semiconductor substrate subassembly is received in said second cavity of said frame and wherein said second composite semiconductor substrate subassembly has a thickness ranging between .010 and .040 inches;
and electrical connecting means for electrically connecting said semiconductor devices on said first and second composite semiconductor substrate sub-assemblies to said electrical contacts on said edge of said frame.
38. A thin multichip module, comprising, in combination:
a frame having a member defining first and second interior portions;
a plurality of electrical contacts disposed on said frame;
first and second composite substrates each comprising a cover plate portion having heat dissipation capabilities and a thin Laminate circuit affixed to said cover plate portion;
semiconductor devices mounted on said first and second composite substrates to form first and second substrate subassemblies, wherein said semiconductor devices are in electrical connection with said laminate circuit and in thermal proximity to said cover plate;
first attaching means to attach said first composite substrate to said frame whereby at least a portion of said first substrate assembly is maintained within said first interior portion of the frame and the substrate subassembly is in electrical communication with said electrical contacts on said frame; and second attaching means to attach said second composite substrate to said frame whereby at least a portion of said second substrate assembly is maintained within said second interior portion of the frame and the substrate subassembly is in electrical communication with said electrical contacts on said frame.
a frame having a member defining first and second interior portions;
a plurality of electrical contacts disposed on said frame;
first and second composite substrates each comprising a cover plate portion having heat dissipation capabilities and a thin Laminate circuit affixed to said cover plate portion;
semiconductor devices mounted on said first and second composite substrates to form first and second substrate subassemblies, wherein said semiconductor devices are in electrical connection with said laminate circuit and in thermal proximity to said cover plate;
first attaching means to attach said first composite substrate to said frame whereby at least a portion of said first substrate assembly is maintained within said first interior portion of the frame and the substrate subassembly is in electrical communication with said electrical contacts on said frame; and second attaching means to attach said second composite substrate to said frame whereby at least a portion of said second substrate assembly is maintained within said second interior portion of the frame and the substrate subassembly is in electrical communication with said electrical contacts on said frame.
39. The module of claim 38, wherein said semiconductor devices mounted to said first composite substrate are received in said first interior portion of said frame and wherein said semiconductor devices mounted to said second composite substrate are received in said second interior portion of said frame.
40. The module of claim 39, wherein said semiconductor devices mounted to said first and second composite substrates do not contact said member of said frame.
41. The module of claim 39, wherein said first and second composite substrates each include top and bottom surfaces, wherein said semiconductor devices are attached to said bottom surfaces of each of said first and second composite substrates, and wherein said bottom surfaces of said first and second composite substrates face said first and second interior portions, respectively.
42. A semiconductor module comprising:
a frame having a floor member defining first and second cavities on opposite sides of said floor member, a plurality of electrical contacts on an edge of said frame;
a first composite substrate comprising a cover plate and a circuit layer applied to said cover plate, said composite substrate having a plurality of semiconductor devices mounted thereon, wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said first cavity of said frame;
a second composite substrate comprising a cover plate and a circuit layer applied to said cover plate, said composite substrate having a plurality of semiconductor devices mounted thereon, wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said second cavity of said frame; and electrical connecting means for electrically connecting said semiconductor devices on said first and second composite semiconductor substrate sub-assemblies to said electrical contacts on said edge of said frame.
a frame having a floor member defining first and second cavities on opposite sides of said floor member, a plurality of electrical contacts on an edge of said frame;
a first composite substrate comprising a cover plate and a circuit layer applied to said cover plate, said composite substrate having a plurality of semiconductor devices mounted thereon, wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said first cavity of said frame;
a second composite substrate comprising a cover plate and a circuit layer applied to said cover plate, said composite substrate having a plurality of semiconductor devices mounted thereon, wherein said composite substrate is attached to said frame such that at least a portion of said semiconductor devices are received in said second cavity of said frame; and electrical connecting means for electrically connecting said semiconductor devices on said first and second composite semiconductor substrate sub-assemblies to said electrical contacts on said edge of said frame.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US94729392A | 1992-09-16 | 1992-09-16 | |
| US07/947,293 | 1992-09-16 | ||
| PCT/US1993/008576 WO1994007264A1 (en) | 1992-09-16 | 1993-09-13 | A thin multichip module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2144740A1 CA2144740A1 (en) | 1994-03-31 |
| CA2144740C true CA2144740C (en) | 2005-11-22 |
Family
ID=35474738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002144740A Expired - Lifetime CA2144740C (en) | 1992-09-16 | 1993-09-13 | A thin multichip module |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2144740C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3854186A1 (en) * | 2018-09-19 | 2021-07-28 | Tesla, Inc. | Mechanical architecture for a multi-chip module |
-
1993
- 1993-09-13 CA CA002144740A patent/CA2144740C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3854186A1 (en) * | 2018-09-19 | 2021-07-28 | Tesla, Inc. | Mechanical architecture for a multi-chip module |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2144740A1 (en) | 1994-03-31 |
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