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CA2025711A1 - Apparatus and method for asynchronously delivering control elements with a pipe interface - Google Patents

Apparatus and method for asynchronously delivering control elements with a pipe interface

Info

Publication number
CA2025711A1
CA2025711A1 CA2025711A CA2025711A CA2025711A1 CA 2025711 A1 CA2025711 A1 CA 2025711A1 CA 2025711 A CA2025711 A CA 2025711A CA 2025711 A CA2025711 A CA 2025711A CA 2025711 A1 CA2025711 A1 CA 2025711A1
Authority
CA
Canada
Prior art keywords
pipe
control elements
memory
units
adapters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2025711A
Other languages
French (fr)
Other versions
CA2025711C (en
Inventor
Francis Michael Bonevento
Joseph Patrick Mcgovern
Eugene Mitchell Thomas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lenovo Singapore Pte Ltd
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2025711A1 publication Critical patent/CA2025711A1/en
Application granted granted Critical
Publication of CA2025711C publication Critical patent/CA2025711C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/064—Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)

Abstract

A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O
devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements on the pipe which represent requests, replies, and status information. The units send and receive control elements independent of the other units which allows free flowing asynchronous delivery of control information and data between units. The shared memory can be organized as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements and the other pipe for inbound control elements.
The control elements have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
CA002025711A 1989-09-22 1990-09-19 Apparatus and method for asynchronously delivering control elements with a pipe interface Expired - Fee Related CA2025711C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41114589A 1989-09-22 1989-09-22
US411,145 1989-09-22

Publications (2)

Publication Number Publication Date
CA2025711A1 true CA2025711A1 (en) 1991-03-23
CA2025711C CA2025711C (en) 1998-03-31

Family

ID=23627758

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002025711A Expired - Fee Related CA2025711C (en) 1989-09-22 1990-09-19 Apparatus and method for asynchronously delivering control elements with a pipe interface

Country Status (13)

Country Link
US (1) US5325492A (en)
EP (1) EP0419066A2 (en)
JP (1) JP3208397B2 (en)
KR (1) KR950002391B1 (en)
CN (1) CN1025518C (en)
AU (1) AU630493B2 (en)
BR (1) BR9004685A (en)
CA (1) CA2025711C (en)
GB (1) GB9012970D0 (en)
MY (1) MY107143A (en)
NZ (1) NZ235002A (en)
PH (1) PH30203A (en)
SG (1) SG44433A1 (en)

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US7613840B2 (en) * 2006-08-17 2009-11-03 General Electric Company Methods and apparatus for dynamic data acquisition configuration parameters
US10848811B2 (en) 2007-07-05 2020-11-24 Coherent Logix, Incorporated Control information for a wirelessly-transmitted data stream
US8478915B2 (en) 2008-02-14 2013-07-02 International Business Machines Corporation Determining extended capability of a channel path
US8117347B2 (en) 2008-02-14 2012-02-14 International Business Machines Corporation Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system
US7941570B2 (en) 2008-02-14 2011-05-10 International Business Machines Corporation Bi-directional data transfer within a single I/O operation
US9052837B2 (en) 2008-02-14 2015-06-09 International Business Machines Corporation Processing communication data in a ships passing condition
US8312189B2 (en) * 2008-02-14 2012-11-13 International Business Machines Corporation Processing of data to monitor input/output operations
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Also Published As

Publication number Publication date
CA2025711C (en) 1998-03-31
CN1050450A (en) 1991-04-03
NZ235002A (en) 1992-08-26
EP0419066A2 (en) 1991-03-27
MY107143A (en) 1995-09-30
PH30203A (en) 1997-02-05
BR9004685A (en) 1991-09-10
KR950002391B1 (en) 1995-03-17
CN1025518C (en) 1994-07-20
JPH03130863A (en) 1991-06-04
GB9012970D0 (en) 1990-08-01
AU6130990A (en) 1991-03-28
AU630493B2 (en) 1992-10-29
US5325492A (en) 1994-06-28
JP3208397B2 (en) 2001-09-10
KR910006842A (en) 1991-04-30
EP0419066A3 (en) 1994-04-20
SG44433A1 (en) 1997-12-19

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