CA2002999A1 - Packet-switching exchange and input converter unit therefor - Google Patents
Packet-switching exchange and input converter unit thereforInfo
- Publication number
- CA2002999A1 CA2002999A1 CA002002999A CA2002999A CA2002999A1 CA 2002999 A1 CA2002999 A1 CA 2002999A1 CA 002002999 A CA002002999 A CA 002002999A CA 2002999 A CA2002999 A CA 2002999A CA 2002999 A1 CA2002999 A1 CA 2002999A1
- Authority
- CA
- Canada
- Prior art keywords
- packet
- packets
- switching
- input
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000015654 memory Effects 0.000 claims description 46
- 230000035508 accumulation Effects 0.000 claims 1
- 238000009825 accumulation Methods 0.000 claims 1
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- 239000000872 buffer Substances 0.000 abstract description 5
- 230000001360 synchronised effect Effects 0.000 abstract description 5
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 241000518994 Conta Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/568—Load balancing, smoothing or shaping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
Abstract Packet-Switching Exchange and Input Converter Unit Therefor To reduce the loss of data packets, it is known to pro-vide buffers, priority logics and traffic-metering de-vices. All this must be present in each switching stage, in most cases once per input line.
This complexity within the switching network is to be reduced.
According to the invention, the incoming packet streams are converted into synchronous TDM data streams in which tine slots and individual calls are associated with one another. Switching can then be effected using synchronous time-division multiplexing. The switching network is simpler in con-struction but must be slightly oversized.
(Figure) D. B?ttle - S. Wahl 13-2
This complexity within the switching network is to be reduced.
According to the invention, the incoming packet streams are converted into synchronous TDM data streams in which tine slots and individual calls are associated with one another. Switching can then be effected using synchronous time-division multiplexing. The switching network is simpler in con-struction but must be slightly oversized.
(Figure) D. B?ttle - S. Wahl 13-2
Description
~0029g9 P 38 40 688.8 Packet-Switching Exchange and Input Converter Unit Therefor The present invention relates to a packet-switching exchange as set forth in the preamble of cLaim 1 and to an input converter unit therefor.
In future, voice, text, image, and data are to be no longer transmitted using time-division multiplexing because this technique is not flexible enough with re-gard to various services. A fast packet-switching technique is to be used.
As a rule, packet switching makes use of virtual cir-cuits, i.e., at the beginning of each call, a path is determined but not set up. Each l;nk of the path may aLso be assigned to other connections. The path is then set up link by link for each packet and subsequently cleared again. In this process, collisions may occur which may result in packets being lost.
To reduce the loss of data packets, it is known to pro-vide buffers and priority logics. It has also been proposed to provide traffic-metering devices~ All this 16 October, 1989 D. Bottle - S. Wahl 13-2 .
~ ~ ' ' . .
20025~9 must be present in each switching stage, in most cases once per input line.
It ;s object of the invention to reduce the cost and compLexity of the switching network in a packet-switching exchange.
This object is attained by a packet-switching exchange according to the teaching of claim 1.
Claim 4 sets forth an input converter unit suitable for such a packet-switching exchange. Further advantageous features are defined in claims 2 and 3 as well as 5 to 8.
According to the invention, the incoming packet data streams are converted into synchronous TDM data streams in which time slots and ;ndividual calls are associated with one another. Switching is then preferably effected using synchronous time-division multiplexing.
~ut even if an assynchronous switching technique is employed, the use of input converter units in accordance with the invention will be advantageous since these units smooth the data stream and, there-for, reduce the technical complexity, particularly the number of buffers required.
An embodiment of the invention will now be explained with reference to the accompanying drawing.
~ D. ~ottle - S. Wahl 13-2 2'00299~
The drawing sho~s an input converter unit in accordance with the invention.
For simplicity, the input converter unit will be de-scribed as if all bits of a packet ~q in the figure) were processed in parallel.
If, as is to be expected for the future, a packet con-sists of about 40 8-bit octets, i.e., of about 320 bits, parallel processing is virtually impossible. For the persons skilled in the art, however, it is no problem to process the data stream, in whole or in part, serially. Also, nearly aLl necessary clock signals, write and read pulses have been omitted, since they are familiar to the persons skilled in the art. Instead of outputting the bits or octets of a packet serially and then outputting the bits or octets of ~he next packet, it may be advantageous to divide the output frame into subframes and, e.g., to serially output first the first octets of all packets, then the second octets of all packets, etc. For further details, see Patent Applications P 37 42 939.6 and P 37 42 941.8 ~internal file references H. Weik 1 and G. Eilenberger et al 1-3-1), which were not publ;shed prior to the filing date of the present application.
Theinput converter unit shown consists of a packet memory 10, a control unit 21 ... 26, and a buffer 30.
The control unit contains an ;nput table 21, an input counter 22, an assignment memory 23, an output counter 24, an output table 25, and an assignment circuit 26.
D. Pottle - S. Wahl 13~2 4 _ The packet memory 10 is designed to be capable of temporarily storing as many packets as are necessary for the conversion to be performed. The conversion of the asynchronous data stream into a synchronous data stream also provides smoothing. The amount of cir-cuitry required depends on how irregular the input data stream may be in order to be still compensated. This will have to be specified somehow by the operator of the system, who will comply with national or international standards. Standarization in this field is still in progress. At this time it is quite certain that the packet data stream will have a frame structure with a frame length of 125 microseconds. About 70 packets con-taining about 40 octets each will then be transmitted per frame. It is also quite certain that during the establishment of a connection, the capacity needed will have to be specified somehow. This may be done by specifying a ma~imum number of packets within a given number of frames. It is also possible to require the specification of an average number. The capacity specification should always relate to a period of time which is equal to one frame length or a multiple thereof.
But even if no frame structure should be Predetermined from outside, the input converter unit can form a frame and smooth the data stream.
The packet memory 10 must be at least so large as to be capable of temporarily storing the packets contained in one frame. If the maximum number of packets within a D. Battle - S. Wahl 13-2 ~:0~)2~9~3 frame has to be specif;ed, it will be sufficient to temporariLy store one frame. If the maximum number within a longer period of time or an average number has to be specified, the packet memory will have to be correspondingly larger, e.g., a memory for two or four complete frames. It is not imperative that the packet memory should be designed for integral multip~es of one frame. If it can be assumed that the capacity of the input line will be utilized only in part, this can be taken into account in the design of the packet memory 10.
The packets arriving at the input E of the input con-verter unit are written sequentially into the packet memory 10. To this end, the input counter 22 continuously counts the addresses of the locations of the packet memory 10. Packets without information to be passed on, e.g., empty packets, synchronization packets, and control packets destined exclusively for the assignment c;rcu;t 26, are not stored. To th;s end, the input table 21 evaluates the packet headers contained in the packets and causes the input counter 22 to advance whenever a new packet has to be wr;tten in.
Theinput table 21 recognizes by the packet headers which call the respective packets belong to. Each cal~
is assigned a call number which is passed from the in-put table 21 to the assignment memory 23. At the same time, the input counter 22 specifies to the assignment memory 23 the current address for the packet memory.
D. Bottle - S. Wahl 13-2 2002~9~3 The assignment memory 23 then stores at which locations of the packet memory 10 the packets belonging to a given call are stored.
The assignment memory 23 preferably conta;ns a plurality of FIF0 memories with associated counters. Each call is assigned one FIF0 memory with associated counter.
To write a packet into the packet memory 10, the associated FIF0 memory is selected by the call number indicated by the ;nput table 21, and the address of the location to be used is written ;nto the FIF0 memory.
Each FIF0 memory thus stores sequentially the addresses of those locations at which the packets belonging to the same call are stored. The assoc;ated counter then indicates how many packets belong;ng together are still stored~
The number of FIF0 memories in the assignment memory 23 must be equal to the maximum permissible number of calls. Since, according to the invention, the time slots on the output line A and the individual calls are to be permanently associated with one another, the maximum number of FIF0 memories required is equal to the number of time slots on the output line. Since the purpose of high-speed packet switching is to achieve greater flexibiLity with respect to transmission capacity, it must be assumed that a given portion of the calls always requires more capacity than is contained in one time slot. In practice it will be sufficient to provide not quite as many FIF0 memories as there are time D. Battle - S. Wahl 13-2 slots. The number of locations a FIFO memory must have depends on the size of the packet memory 10 and on how irregularLy the packets arrive at the input E. If the packet memories 10 can store about one frame, about eight locations for one address each should be sufficient for each FIFO memory. In the case of calls requiring a higher capacity, more addresses have to be temporarily stored, but they become free again more quickLy.
The packets are read out of the packet memory 10 as follows.
Theoutpùt counter 24 counts the time slots on the output line A. To this end, it is frame-synchronized by a clock signal T1 and advanced for each packet by a clock signal T2. The output counter 24 addresses the output table 25, which knows and selects the FIFO memory of the assignment memory 23 associated with the respective output channel This FIFO memory contains the address of that location in the packet memory 10 which holds the next packet for the selected time slot, which is then read out.
If the number of the same FIFO memory is contained in the output table 25 for two or more time slots, this means that these time slots are assigned to one and the same call.
On the other hand, the number of the same FIFO memory may be contained in the input table 21 for two or more D. Bottle - S. Wahl 13-2 21002~9~3 different packet headers~ Then, the same time slot is assigned to two or more calls. This is appropriate if two or more calls have the same destination and require a small total capacity.
The assignments within the input table 21 and the output table 25 are made from the assignment circuit 26. The latter receives its control commands via control packets contained in the input data stream.
The input data stream does not constantly contain useful information. In addition, in order to have more paths available, the output data stream may have a greater capacity than the input data stream. Whenever the packet memory 10 no longer contains a packet for a time slot, an empty packet must be outputted. This empty packet may be contained in a separate memory or in a location of the packet memory 10 which is not reached by the input counter 22. Whenever either no FIF0 memory is assigned to a time slot or its counter indicates that it is empty, an empty packet must be outputted. The contents of the empty packet may be either hard-wired, it being sufficient to wire those bit positions which identify a packet as an empty packet, or written into a location of the packet memory 10, e.g., on power-up or at predetermined intervals.
The buffer 30 serves to delay the input data stream such that it appears at the packet memory 10 when the latter is properly controlled by the input table 21 and the input counter 22.
D. 80ttle - S. Wahl 13-2 . ' -, . . ~
-, . . : . . . : .
.
In future, voice, text, image, and data are to be no longer transmitted using time-division multiplexing because this technique is not flexible enough with re-gard to various services. A fast packet-switching technique is to be used.
As a rule, packet switching makes use of virtual cir-cuits, i.e., at the beginning of each call, a path is determined but not set up. Each l;nk of the path may aLso be assigned to other connections. The path is then set up link by link for each packet and subsequently cleared again. In this process, collisions may occur which may result in packets being lost.
To reduce the loss of data packets, it is known to pro-vide buffers and priority logics. It has also been proposed to provide traffic-metering devices~ All this 16 October, 1989 D. Bottle - S. Wahl 13-2 .
~ ~ ' ' . .
20025~9 must be present in each switching stage, in most cases once per input line.
It ;s object of the invention to reduce the cost and compLexity of the switching network in a packet-switching exchange.
This object is attained by a packet-switching exchange according to the teaching of claim 1.
Claim 4 sets forth an input converter unit suitable for such a packet-switching exchange. Further advantageous features are defined in claims 2 and 3 as well as 5 to 8.
According to the invention, the incoming packet data streams are converted into synchronous TDM data streams in which time slots and ;ndividual calls are associated with one another. Switching is then preferably effected using synchronous time-division multiplexing.
~ut even if an assynchronous switching technique is employed, the use of input converter units in accordance with the invention will be advantageous since these units smooth the data stream and, there-for, reduce the technical complexity, particularly the number of buffers required.
An embodiment of the invention will now be explained with reference to the accompanying drawing.
~ D. ~ottle - S. Wahl 13-2 2'00299~
The drawing sho~s an input converter unit in accordance with the invention.
For simplicity, the input converter unit will be de-scribed as if all bits of a packet ~q in the figure) were processed in parallel.
If, as is to be expected for the future, a packet con-sists of about 40 8-bit octets, i.e., of about 320 bits, parallel processing is virtually impossible. For the persons skilled in the art, however, it is no problem to process the data stream, in whole or in part, serially. Also, nearly aLl necessary clock signals, write and read pulses have been omitted, since they are familiar to the persons skilled in the art. Instead of outputting the bits or octets of a packet serially and then outputting the bits or octets of ~he next packet, it may be advantageous to divide the output frame into subframes and, e.g., to serially output first the first octets of all packets, then the second octets of all packets, etc. For further details, see Patent Applications P 37 42 939.6 and P 37 42 941.8 ~internal file references H. Weik 1 and G. Eilenberger et al 1-3-1), which were not publ;shed prior to the filing date of the present application.
Theinput converter unit shown consists of a packet memory 10, a control unit 21 ... 26, and a buffer 30.
The control unit contains an ;nput table 21, an input counter 22, an assignment memory 23, an output counter 24, an output table 25, and an assignment circuit 26.
D. Pottle - S. Wahl 13~2 4 _ The packet memory 10 is designed to be capable of temporarily storing as many packets as are necessary for the conversion to be performed. The conversion of the asynchronous data stream into a synchronous data stream also provides smoothing. The amount of cir-cuitry required depends on how irregular the input data stream may be in order to be still compensated. This will have to be specified somehow by the operator of the system, who will comply with national or international standards. Standarization in this field is still in progress. At this time it is quite certain that the packet data stream will have a frame structure with a frame length of 125 microseconds. About 70 packets con-taining about 40 octets each will then be transmitted per frame. It is also quite certain that during the establishment of a connection, the capacity needed will have to be specified somehow. This may be done by specifying a ma~imum number of packets within a given number of frames. It is also possible to require the specification of an average number. The capacity specification should always relate to a period of time which is equal to one frame length or a multiple thereof.
But even if no frame structure should be Predetermined from outside, the input converter unit can form a frame and smooth the data stream.
The packet memory 10 must be at least so large as to be capable of temporarily storing the packets contained in one frame. If the maximum number of packets within a D. Battle - S. Wahl 13-2 ~:0~)2~9~3 frame has to be specif;ed, it will be sufficient to temporariLy store one frame. If the maximum number within a longer period of time or an average number has to be specified, the packet memory will have to be correspondingly larger, e.g., a memory for two or four complete frames. It is not imperative that the packet memory should be designed for integral multip~es of one frame. If it can be assumed that the capacity of the input line will be utilized only in part, this can be taken into account in the design of the packet memory 10.
The packets arriving at the input E of the input con-verter unit are written sequentially into the packet memory 10. To this end, the input counter 22 continuously counts the addresses of the locations of the packet memory 10. Packets without information to be passed on, e.g., empty packets, synchronization packets, and control packets destined exclusively for the assignment c;rcu;t 26, are not stored. To th;s end, the input table 21 evaluates the packet headers contained in the packets and causes the input counter 22 to advance whenever a new packet has to be wr;tten in.
Theinput table 21 recognizes by the packet headers which call the respective packets belong to. Each cal~
is assigned a call number which is passed from the in-put table 21 to the assignment memory 23. At the same time, the input counter 22 specifies to the assignment memory 23 the current address for the packet memory.
D. Bottle - S. Wahl 13-2 2002~9~3 The assignment memory 23 then stores at which locations of the packet memory 10 the packets belonging to a given call are stored.
The assignment memory 23 preferably conta;ns a plurality of FIF0 memories with associated counters. Each call is assigned one FIF0 memory with associated counter.
To write a packet into the packet memory 10, the associated FIF0 memory is selected by the call number indicated by the ;nput table 21, and the address of the location to be used is written ;nto the FIF0 memory.
Each FIF0 memory thus stores sequentially the addresses of those locations at which the packets belonging to the same call are stored. The assoc;ated counter then indicates how many packets belong;ng together are still stored~
The number of FIF0 memories in the assignment memory 23 must be equal to the maximum permissible number of calls. Since, according to the invention, the time slots on the output line A and the individual calls are to be permanently associated with one another, the maximum number of FIF0 memories required is equal to the number of time slots on the output line. Since the purpose of high-speed packet switching is to achieve greater flexibiLity with respect to transmission capacity, it must be assumed that a given portion of the calls always requires more capacity than is contained in one time slot. In practice it will be sufficient to provide not quite as many FIF0 memories as there are time D. Battle - S. Wahl 13-2 slots. The number of locations a FIFO memory must have depends on the size of the packet memory 10 and on how irregularLy the packets arrive at the input E. If the packet memories 10 can store about one frame, about eight locations for one address each should be sufficient for each FIFO memory. In the case of calls requiring a higher capacity, more addresses have to be temporarily stored, but they become free again more quickLy.
The packets are read out of the packet memory 10 as follows.
Theoutpùt counter 24 counts the time slots on the output line A. To this end, it is frame-synchronized by a clock signal T1 and advanced for each packet by a clock signal T2. The output counter 24 addresses the output table 25, which knows and selects the FIFO memory of the assignment memory 23 associated with the respective output channel This FIFO memory contains the address of that location in the packet memory 10 which holds the next packet for the selected time slot, which is then read out.
If the number of the same FIFO memory is contained in the output table 25 for two or more time slots, this means that these time slots are assigned to one and the same call.
On the other hand, the number of the same FIFO memory may be contained in the input table 21 for two or more D. Bottle - S. Wahl 13-2 21002~9~3 different packet headers~ Then, the same time slot is assigned to two or more calls. This is appropriate if two or more calls have the same destination and require a small total capacity.
The assignments within the input table 21 and the output table 25 are made from the assignment circuit 26. The latter receives its control commands via control packets contained in the input data stream.
The input data stream does not constantly contain useful information. In addition, in order to have more paths available, the output data stream may have a greater capacity than the input data stream. Whenever the packet memory 10 no longer contains a packet for a time slot, an empty packet must be outputted. This empty packet may be contained in a separate memory or in a location of the packet memory 10 which is not reached by the input counter 22. Whenever either no FIF0 memory is assigned to a time slot or its counter indicates that it is empty, an empty packet must be outputted. The contents of the empty packet may be either hard-wired, it being sufficient to wire those bit positions which identify a packet as an empty packet, or written into a location of the packet memory 10, e.g., on power-up or at predetermined intervals.
The buffer 30 serves to delay the input data stream such that it appears at the packet memory 10 when the latter is properly controlled by the input table 21 and the input counter 22.
D. 80ttle - S. Wahl 13-2 . ' -, . . ~
-, . . : . . . : .
.
Claims (8)
1. Packet-switching exchange having input lines over which packets of equal length belonging to different calls arrive in an arbitrary sequence, c h a r a c t e r i z e d i n that it includes in-put converter units each of which reorders the incoming packets to form an input data stream in which accumu-lations of packets belonging to a given call (bursts) are dissolved.
2. A packet-switching exchange as claimed in claim 1, characterized in that each of the input converter units reorders the incoming packets to form a time division multiplex signal in which the time slots and the packets belonging to a given call are associated with one another.
3. A packet-switching exchange as claimed in claim 2, characterized in that it includes time division multiplex switching apparatus for circuit-switching the converted input data streams.
D. B?ttle - S. Wahl 13-2
D. B?ttle - S. Wahl 13-2
4. Input converter unit for insertion into an input line of the packet-switching exchange claimed in claim 2 or 3, c h a r a c t e r i z e d i n that it includes a memory (10) and a control unit (21 ... 26), that all incoming packets are first written into the memory (10) under control of the control unit (21 ... 26), and that the packets are read from the memory (10) so as to form a time division multiplex signal in which the time slots and the packets belonging to a given call are associated with one another.
5. An input converter unit as claimed in claim 4, characterized in that the number of time slots assigned to a call depends on the maximum number of packets occurring in this call within a given unit of time.
6. An input converter unit as claimed in claim 4, characterized in that the number of time slots assigned to a call depends on the average number of packets occurring in this call within a given unit of time.
7. An input converter unit as claimed in claim 5 or 6, characterized in that the frame length of the time division multiplex signal has an integral ratio to the given unit of time.
8. An input converter unit as claimed in any one of claims 4 to 7, characterized in that the packets D. B?ttle - S. Wahl 13-2 of two or more calls are assigned to one time slot if they are destined for the same output of the packet-switching exchange and if the capacity of the time slot is sufficient.
D. B?ttle - S. Wahl 13-2
D. B?ttle - S. Wahl 13-2
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3840688A DE3840688A1 (en) | 1988-12-02 | 1988-12-02 | PACKAGE SWITCH AND INPUT CONVERSION UNIT HERE |
| DEP3840688.8 | 1988-12-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2002999A1 true CA2002999A1 (en) | 1990-06-02 |
Family
ID=6368352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002002999A Abandoned CA2002999A1 (en) | 1988-12-02 | 1989-11-15 | Packet-switching exchange and input converter unit therefor |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0372283A3 (en) |
| JP (1) | JP2933653B2 (en) |
| CN (1) | CN1043415A (en) |
| AU (1) | AU622948B2 (en) |
| CA (1) | CA2002999A1 (en) |
| DE (1) | DE3840688A1 (en) |
| MX (1) | MX174535B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0921705B1 (en) * | 1997-12-04 | 2008-07-16 | Nippon Telegraph And Telephone Corporation | STM Based circuit-switched network for transferring data |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60165851A (en) * | 1984-02-09 | 1985-08-29 | Nitsuko Ltd | Data storage transmission system of start-stop system |
| JPS61187497A (en) * | 1985-02-15 | 1986-08-21 | Nec Corp | Circuit/packet combination switching system |
| BE904100A (en) * | 1986-01-24 | 1986-07-24 | Itt Ind Belgium | SWITCHING SYSTEM. |
| DE3742939A1 (en) * | 1987-12-18 | 1989-07-06 | Standard Elektrik Lorenz Ag | METHOD FOR HYBRID PACKING AND DEVICES THEREFOR |
| JP2667868B2 (en) * | 1988-04-06 | 1997-10-27 | 株式会社日立製作所 | Cell switching system |
-
1988
- 1988-12-02 DE DE3840688A patent/DE3840688A1/en not_active Withdrawn
-
1989
- 1989-11-15 CA CA002002999A patent/CA2002999A1/en not_active Abandoned
- 1989-11-18 EP EP19890121388 patent/EP0372283A3/en not_active Ceased
- 1989-11-21 AU AU45325/89A patent/AU622948B2/en not_active Ceased
- 1989-11-30 MX MX018538A patent/MX174535B/en unknown
- 1989-12-01 JP JP31311989A patent/JP2933653B2/en not_active Expired - Lifetime
- 1989-12-01 CN CN89108923.3A patent/CN1043415A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN1043415A (en) | 1990-06-27 |
| EP0372283A3 (en) | 1992-07-15 |
| AU622948B2 (en) | 1992-04-30 |
| JP2933653B2 (en) | 1999-08-16 |
| MX174535B (en) | 1994-05-23 |
| JPH02202145A (en) | 1990-08-10 |
| DE3840688A1 (en) | 1990-06-13 |
| EP0372283A2 (en) | 1990-06-13 |
| AU4532589A (en) | 1990-06-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |