CA1336446C - Switch hook flash detection circuit - Google Patents

Abstract

A digital signal calibration circuit for receiving an input digital signal, filtering transient signal pulses, lengthening pulses of a first predetermined duration to a second predetermined duration, and generating a calibrated digital output signal in response thereto. The output signal is then digitally sampled to detect predetermined digital signal bit patterns. The signal calibration circuit can be used in a communication system for detecting digital hookswitch flash and dial pulsing signals.

Description

~- 1336446 01 This invention relates in general to 02 communication systems, and more particularly to a 03 signal calibration circuit for use in a communication 04 system to detect hookswitch flash and dial pulse 05 signals.
06 In a digital communication system, signals o7 generated by a subscriber set and applied to a 08 two-wire balanced line are received via a peripheral 09 line circuit and are digitized therein. Such signals may include, for example, voice signals, hookswitch ll flash signals, dial pulse signals, and DTMF tones. A
12 hookswitch flash signal is generated in response to a 13 momentary depression of the hookswitch on a subscriber 14 set, and is used to initiate a special feature such as call forwarding, call transferring, hold, speed dial, 16 etc.
17 Dial pulse and hookswitch flash signals 18 are required to be detected and distinguished by a 19 peripheral processor of the communication system in order to implement the desired special feature or to 21 connect the subscriber set to an extension 22 corresponding to dialed numbers. The dial signals are 23 typically in the form of a succession of logic high 24 and logic low level pulses of approximately 40 and 60 milliseconds respectively. Hookswitch flash signals 26 are typically in the form of momentary logic high 27 level signals which can have durations as low as 24 28 milliseconds.
29 One prior art method for detecting dial pulse and hookswitch flash signals involves constant 31 scanning of the digital input signal at a high 32 sampling rate (i.e. much greater than 1000 samples per 33 second) by the peripheral processor. The peri~heral 34 processor is required to execute many additional tasks, so that high speed sampling of the digital 36 input signal from the line circuit typically consumes 37 excess processor time and is therefore impractical.

01 Another prior art method utilizes 02 intelligent hardware comprising an onboard 03 microprocessor disposed on each peripheral card in 04 order to perform the aforementioned high speed digital 05 sampling. However, this has been found to be 06 expensive, to occupy a large amount of circuit board 07 area, and to consume a large amount of power.
08 According to the present invention, 09 circuitry is provided for debouncing the digital signal generated by the line circuit, in order to 11 eliminate transient pulses, and additional circuitry 12 is provided for calibrating the hookswitch flash and 13 dial pulse signals to a standard duration. Discrete 14 implementation of these functions can be implemented utilizing analog timing either on the line hybrid or 16 line circuit card, or with digital filtering on the 17 line circuit card. The calibration circuitry is then 18 followed by circuitry for digital multiplexing of the 19 calibrated signals to the peripheral processor backplane.
21 A minor disadvantage of the discrete 22 implementation discussed above is the lack of 23 available space on many line circuit cards and hybrids 24 to support the discrete circuit components. In the event that the hybrid or line circuit is modified, a 26 compatability problem may develop with some existing 27 systems.
28 Thus, according to a preferred embodiment 29 of the present invention, a CMOS uncommitted logic array (ULA) is utilized to implementing the circuitry 31 of the present invention. ULA technology can be used 32 to effectively realize any combinatorial or sequential 33 logic circuit in an inexpensive, and easy to define 34 semiconductor chip. The advantages of using a ULA are low cost and low space consumption, compatability with 36 existing line circuits, and reduction of random logic 37 already existing on the line circuits. In a ~ 13364~6 01 successful prototype, the digital signal calibration 02 circuitry of the present invention was realized on a 03 single ULA per line circuit card, thereby optimizing 04 circuit pin count for implementation of as many 05 peripheral card logic functions as possible.
06 Functionally, the circuit of the present 07 invention is connected in series between digital 08 signal outputs of the line circuit cards, and the o9 peripheral processor backplane. Latches read the hookswitch bit from each of a plurality of time 11 division channels of digital signals received from the 12 line circuit cards, and forward the information to 13 individual real time processing networks within the 14 ULA. These ULA networks produce two output bits per channel; one indicating detection of a short 16 hookswitch flash signal, and the other being a 17 debounced and conditionally stretched version of the 18 hookswitch signal, ignoring transient logic level 19 signals (ie. "glitches"). The ULA networks stretch short makes and breaks of the hookswitch signal to a 21 standard calibrated duration.
22 As a result of debouncing and stretching 23 of the hookswitch signal, the peripheral processor is 24 able to sample at a relatively slow (approximately 100 samples per second) scan rate, and still reliably 26 detect rapidly changing logic levels (e.g. a 20 pulse 27 per second dialing signal).
28 In general, according to the present 29 invention there is provided a signal calibration circuit, comprised of circuitry for receiving a 31 digital input signal comprised of logic high and logic 32 low level pulses, circuitry for eliminating transient 33 ones of the pulses from the signal, which are of 34 duration less than a first predetermined time period, and circuitry for lengthening the duration of further 36 ones of the pulses from a second predetermined time 37 period which is greater than the first time period to 13364~6 01 a third predetermined time period greater than the 02 first and second time periods, whereby the input 03 signal is debounced and calibrated enabling sampling 04 thereof at a low sampling rate.
05 A better understanding of the present 06 invention will be obtained with reference to the 07 detailed description below in conjunction with the 08 following drawings in which:
09 Figure 1 is a block diagram showing digital signal calibration circuitry according to the 11 present invention, for use in a communication system, 12 in its most general form, 13 Figures 2A-2G are timing waveform 14 representations showing the relationship between digital input signals and calibrated output signals 16 for various circumstances, in accordance with the 17 present invention, 18 Figure 3 is a block schematic diagram 19 showing the circuitry of the present invention disposed in a ULA, 21 Figure 4 is a detailed schematic diagram 22 of ripple counter circuitry for implementing the 23 hookswitch debounce and stretching functions according 24 to a preferred embodiment of the present invention.
Figure 5 is a timing waveform 26 representation illustrating signal waveforms that 27 result in the ripple counter circuitry in response to 28 a digital input signal and timing control signals, 29 Figure 6A is a timing waveform representation illustrating the relationshp between 31 timing control signals applied to the ripple counter 32 circuitry, 33 Figure 6B is a timing waveform 34 representation illustrating the relationship between digital input signals, timing control signals and 36 digital output signals in the signal calibration 01 portion of the circuit of Figure 4, and 02 Figure 7 is a timing waveform 03 representation illustrating the relationship between 04 digital input signals, timing control signals and 05 digital output signals in the calibrated flash portion 06 of the circuit of Figure 4.
07 With reference to Figure 1, a plurality of 08 line circuit cards 1, 3 and 5 are shown for connection 09 to respective pluralities of subscribers' sets via a plurality of bi-directional communication leads, shown 11 generally as 7. For the purposes of explanation, only 12 three line circuit cards are illustrated. However, 13 typically many more are actually utilized in a typical 14 communication system such as a PABX or key telephone system.
16 Each of the line circuit cards 1, 3, and 5 17 receives analog voice and control signals from a 18 plurality of telephone sets, and generates a 19 multiplexed serial digital signal in response thereto in a well known manner. For example, in many well 21 known digital PABX systems, up to 16 analog subscriber 22 sets may be connected to a single line circuit card.
23 The line circuit card, such as line circuit card 1, 24 digitizes incoming analog signals received from the sets (e.g. voice signals, dial pulses, DTMF tones, 26 etc.) and multiplexes the digitized signals from the 27 sets onto 32 channel PCM and TDM data links for 28 transmission to digital switching circuitry, such as a 29 dual time and space division cross-point switching matrix (not shown), in a well known manner. Such a 31 prior art system that performs this function is sold 32 by Mitel Corporation as SX-2000~.
33 Also, the line circuit cards, 1, 3 and 5 34 detect momentary grounding of the ring lead (i.e. one of the leads in each of bidirectional balanced tip and 36 ring lead pairs 7), and momentary high impedance 37 conditions between the tip and ring leads of the 13364~6 01 bidirectional balanced lead pair. A serial data 02 output 8 from each of the line circuit cards 1, 3 and 03 5 carries digital control information relating to 04 respective ones of the subscriber sets connected 05 thereto.
06 In particular, typically 32 channels of 8 07 bit digital signals are transmitted from the data 08 output of the line circuit cards 1, 3 and 5 in serial 09 fashion, for reception by the peripheral processor 9.
Each of the 8 bit signals is comprised of four least 11 significant bits (designated as "GB") each of which 12 indicates the status of European ground button (EGB) 13 voltage associated with respective ones of the sets, 14 and four most significant bits (designated as "SHK"), each of which indicates the status of the hookswitch 16 impedance associated with the respective subscriber 17 sets. More particularly, logic low level of the SHK
18 signal indicates an on-hook impedance between tip and 19 ring leads of the balanced lead pair 7, and logic high level of the SHK signal indicates an off-hook 21 impedance between the tip and ring leads. Similarly, 22 a logic high level of each of the least significant GB
23 bits indicates that the ring lead of the bidirectional 24 balanced lead pair has been connected to ground at the subscriber set, while a logic low level of the GB bits 26 indicates that the ring lead is connected to a source 27 of battery voltage (eg. typically -48 volts).
28 The serial data output signals from the 29 line circuit cards 1, 3 and 5 are transmitted for reception by signal calibration circuits 11, 13 and 31 15, respectively, which, in the preferred embodiment 32 of the present invention, are disposed in respective 33 uncommitted logic arrays (ULAs). Each of the signal 34 calibration circuits 11, 13 and 15 receive the serial digital signals output on line 8 from the line circuit 36 cards 1, 3 and 5, as well as timing signals generated 37 by peripheral controller 9 on C244, FP and RST

`- 1336446 01 inputs. In response to receiving the serial digital 02 signals and timing signals, circuits 11, 13 and 15 03 digitally filter transient logic level pulses of the 04 SHK and GB signals, and generate further serial 05 digital output signals including a debounced and 06 stretched hookswitch signal denoted SHKD, and a 07 calibrated flash signal, denoted as CF.
08 The serial digital output signal from each 09 of the calibration circuits 11, 13 and 15 is preferably comprised of 32 channels of information, 11 each channel being in the form of an eight bit byte, 12 the most significant location in the byte being 13 occupied by the SHKD bit, the next most significant 14 location being occupied by the CF bit, the next two most significant locations being occupied by redundant 16 versions of the SHK bit, and each of the last four 17 locations being occupied by redundant versions of the 18 GB bit.
19 A series of latches internal to the signal calibration circuits 11, 13 and lS read the SHK bit 21 from channels 0-15 output from circuits 1, 3 and 5 and 22 forward the SHK bits to individual real time 23 processing networks within the signal calibration 24 circuits, as discussed in greater detail below with reference to figures 3 and 4. The individual real 26 time processing networks produce the aforementioned 27 "calibrated flash" bit (CF) and the debounced and 28 conditionally stretched version of the SHK bit, (i.e.
29 SHKD). The real-time processing networks ignore 6-9 millisecond transient pulses of SHK and also digitally 31 stretch the short make and break intervals of the SHK
32 signal to produce the calibrated SHKD output. By 33 filtering transient logic level pulses and stretching 34 or elongating the SHK bit, the SHKD bit is calibrated in order that peripheral controller 9 may sample the 36 serial output signals from the calibration circuits 37 11, 13 and 15 at a relatively low sampling rate, 01 thereby reducing the processor's real time work load.
02 The data output streams from individual 03 ones of the circuits 11, 13 and 15 are selectively 04 multiplexed with the unprocessed serial digital input 05 signals received from the line circuit cards in 06 response to predetermined control signals being 07 applied to the select inputs SO and Sl by line circuit 08 cards 1, 3 and 5, respectively.
09 In particular, groups of channels of the unprocessed serial digital input signals are modified 11 in accordance with the SO and Sl bit values as shown 12 in Table 1.

SO Sl CHANNELS MODIFIED
16 0 0 None 18 0 1 CH 0-3, CH 8-11 21 For channels 16-30, the internal 22 multiplexer of the calibration circuits passes the 23 data output stream through transparently to the 24 backplane for reception by the peripheral controller 9. Channel 31 is assigned as an 8 bit parallel input 26 port which allows for serialization of an 8 bit 27 identification PROM data signal which does not form 28 part of the present invention.
29 In operation, the circuits 11, 13 and 15 30 receive the serial digital input signals from the line 31 cards in the following format, in which DO-D7 32 represent the bits of each byte constituting a 33 channel:

D7 D6 D5 D4 D3 D2 Dl DO

37 The SHK bits are extracted and processed 38 to generate the aforementioned SHKD and CF bits. In 39 particular, with reference to Figures 2A-2G (which ~- 1336446 01 will be described in more detail later), the SHKD bit 02 forms a delayed, debounced and stretched version of 03 the SHK bit. The SHKD bit goes to a logic high level 04 in the event the SHK bit maintains a logic high level 05 for at least 6-9 milliseconds (see Figure 2A).
06 Therefore, in the event of a transient logic high 07 level pulse of the SHK bit having duration of less 08 than 6 milliseconds, the SHKD bit remains at a logic 09 low level. In the event the SHK bit is at a logic high level for greater than 9 milliseconds and less 11 than 16.5 milliseconds then the SHKD goes to a logic 12 high level for between 13.5 and 16.5 milliseconds.
13 The SHKD bit goes to a logic low level 6-9 14 milliseconds after the SHK bit has gone to a logic low level (see "delay" in Figures 2A-2G). Therefore, in 16 the event of a transient logic low level pulse of the 17 SHK bit having a duration less than 6 milliseconds, 18 the SHKD bit maintains a logic high level. In the 19 event the SHK bit goes to a logic low level for greater than 9 milliseconds and less than 16.5 21 milliseconds then the SHKD bit drops to a logic low 22 level for 13.5 - 16.5 milliseconds.
23 By the circuit stretching and debouncing 24 the SHK hookswitch signal, the typically busy peripheral controller 9 is able to scan the hookswitch 26 signal at a relatively low (eg. 10 milliseconds) scan 27 rate, allowing it to serve other functions with 28 greater efficiency, yet it can capture rapidly 29 changing data (e.g. 20 pulse per second dial pulses received from the subscriber sets).
31 The calibrated flash (CF) bit goes to a 32 logic high level for 168 milliseconds in the event the 33 SHK bit remains at a logic low level for greater than 34 18 milliseconds. This allows the peripheral controller 9 to scan for short hookswitch flashes at a 36 slow scan rate (e.g. 100 milliseconds), therefore 37 optimizing the real time task performing capability of 38 _ 9 _ 01 the typically busy peripheral controller 9.
02 During assertion of the CF bit, the CF
03 time out (i.e. 168 milliseconds) is restarted by any 04 validated SHK breaks, (i.e. dial pulses).
05 The serial digital signal output from 06 circuits 11, 13 and 15 is provided to the backplane 07 for sampling by the peripheral controller 9, in the 08 following format:

D7 D6 D5 D4 D3 D2 Dl D0 12 Considering Figures 2A-2G in greater 13 detail, the signal waveforms are illustrated for the 14 SHKD bit and the CF bit in response to various waveforms of the SHK bit.
16 With reference to Figure 2A representing 17 the offhook instruction of a call, the SHK bit is 18 shown changing from a logic low level to a logic high 19 level, (i.e. the subscriber set has gone off-hook).
The SHKD bit changes from a logic low to a logic high 21 level after an approximately 6-9 milliseconds delay.
22 The CF bit remains at a logic low level.
23 Turning to Figure 2B, the SHK bit waveform 24 illustrates the presence of dial pulses. In response, the SHKD bit reproduces the SHK bit waveform delayed 26 by 6-9 milliseconds. During the break portion of the 27 SHK bit waveform, the SHK bit assumes a logic low 28 level for greater than at least 18-24 milliseconds, 29 resulting in the CF bit changing from a logic low to a logic high level approximately 26-32 milliseconds 31 after the SHK bit changes from a logic high level to a 32 logic low level. The CF bit maintains the logic high 33 level for a period extending to approximately 200 34 milliseconds after the final transition of the SHKD
bit from a logic high level to a logic low level.
36 Turning to Figure 2C, the SHK waveform is 37 shown representing dial pulses with short 10 ms 38 breaks, rather than 60 ms as in the example of Figure 01 2B. The SHKD bit constitutes a waveform in which the 02 break (logic low) portion is stretched from 10 03 milliseconds to approximately 13.5-16.5 milliseconds.
04 The SHKD bit then changes to a logic high level for 05 the remainder of the duration of the logic high level 06 make portion of the SHK bit plus the aforementioned 07 delay of 6-9 milliseconds (>33 ms). Since the logic 08 low level or break portion of the SHK bit is 09 maintained for less than 18 milliseconds, the CF bit stays at a logic low level.
11 With reference to Figure 2D, the SHK bit 12 waveform is shown representing dialling digits having 13 short 10 ms make intervals. The SHKD bit waveform is 14 delayed by 6-9 milliseconds from the SHK bit waveform, and the short make interval is stretched from 10 16 milliseconds to approximately 13. 5-16.5 milliseconds.
17 Since the break portion of the SHK bit exceeds 18 18 milliseconds in duration, the CF bit changes from a 19 logic low level to a logic high level approximately 26-32 milliseconds after the SHK bit switches from a 21 logic high level to a logic low level, and is 22 maintained at a logic high level for approximately 200 23 milliseconds after the last transition of the SHK
24 signal from the logic high to the logic low level.
Considering Figure 2E, a talk state flash 26 condition is indicated wherein ~he SHK hookswitch bit 27 waveform goes from a logic high level to a logic low 28 level signal for a duration of 25 milliseconds and 29 then reverts to the logic high level. In response, the SHKD bit waveform follows the SHK bit waveform 31 with a delay of 6-9 milliseconds, as discussed above.
32 Also, the CF bit goes to a logic high level signal for 33 168 milliseconds, after an initial delay of 26-32 34 milliseconds.
Turning to Figure 2F, transient low and 36 high logic level pulses lOA and lOB respectively of 37 the SHK bit waveform are illustrated, indicating -01 "glitches". These glitches are ignored and the SHKD
02 bit goes to a logic low level for 13.5-16.5 03 milliseconds approximately 6-9 milliseconds after the 04 SHK bit has changed from a logic high to a logic low 05 level. The CF bit is maintained at a logic low level.
06 With reference to Figure 2G, the SHK bit 07 waveform indicates the condition when a subscriber set 08 releases the line and goes on-hook. The SHKD bit goes 09 from a logic high to a logic low level 6-9 milliseconds after the SHK bit, and the CF bit goes 11 from a logic low to a logic high level for 168 12 milliseconds, 26-32 milliseconds after the SHK bit 13 goes from a logic high to a logic low level.
14 In Figure 3 a block schematic diagram is shown illustrating the principle components of each of 16 the calibration circuits 11, 13 and 15. In 17 particular, a timing circuit 30 is shown for receiving 18 244 nanosecond clock, and 125 microsecond frame pulse 19 timing and control signals from the backplane, on C244 and FP respectively. In addition, timing circuit 21 30 receives reset signal RST generated at the line 22 circuit card. The timing circuit 30 generates a 23 plurality of timing signals and applies them onto a 24 clock bus 32 for application to the clock inputs CLKIN
of a multiplex controller 34 and a serial-to-parallel 26 converter 36, as well as to the timing input of a 27 signal processing circuit 38.
28 Multiplex controller 34 receives control 29 bits S0 and Sl from the line card. In response, the multiplex controller generates a multiplex clock 31 signal for application to the multiplex control input 32 MUX CLKIN of an output multiplexer 40. The multiplex 33 controller 34 supervises TDM channel modification in 34 accordance with the select control signals S0 and Sl received from its respective line card, as discussed 36 above with reference to Figure 1 and Table 1.
37 The serial-to-parallel converter 36 01 receives the serial digital input signal from 02 corresponding ones of the line circuit cards 1, 3 or 03 5, on a serial input IN. The serial digital input 04 signal is passed transparently to a serial output SOUT
05 thereof for application to a serial input SIN of the 06 output multiplexer 40. The input signal is also 07 converted to parallel form and is transmitted via a 16 08 bit parallel bus from a SHK output of the 09 serial-to-parallel converter 36 to the SIGNAL INPUT of signal processing circuit 38.
Il Signal processing circuit 38 is comprised 12 of sixteen individual circuits for receiving 13 respective channels of the parallel SHK input signals 14 and for generating the corresponding CF and SHKD
signals in response to receiving the clock signal 16 output from timing circuit 30. The respective 17 circuits comprising the processing circuit 38, are 18 described in greater detail below with reference to 19 Figure 4.
AS discussed above with reference to 21 Figure 3, output multiplexer 40 modifies predetermined 22 ones of the input channels received from 23 serial-to-parallel converter 36 under control of 24 multiplex controller 34, whereby the CF and SHKD bits are selectively inserted into the outgoing serial 26 output stream.
27 The sixteen CF and SHKD outputs of signal 28 processing unit 38 are applied to parallel CF IN and 29 SHKD IN inputs of the output multiplexer 40.
The serial digital output signal from 31 multiplexer 40 is applied to the PABX backplane as 32 discussed above with reference to Figure 1.
33 Turning now to Figure 4, a schematic 34 diagram is shown illustrating the components comprising a representative first one of the sixteen 36 ULA calibration circuits comprising signal processing 37 unit 38, for processing the SHK bit on the first TDM

01 channel (i.e. channel 0). The remaining fifteen ULA
02 circuits of signal processing unit 38, corresponding 03 to channels 1-15, are of identical construction to 04 that shown in Figure 4.
05 The hookswitch bit SHKO from the first 06 TDM channel of the serial digital input signal is 07 received from the serial/parallel converter 36 on 8~ the data input D of a flip-flop 100 having enable inputs EN and EN connected to a source of timing 11 signal T3P2 carried by the clock bus 32(Figure 3).
12 The Q output of flip-flop 100 is connected to the data 13 input D of a second flip-flop 102 which in turn has a ~4 Q output connected to the data input D of a third 16 flip-flop 104. The enable inputs EN and EN of the 17 flip-flops 102 and 104 are connected to additional 18 sources of timing signal, designated T3Pl and T3PO
19 respectively. The T3P2, T3Pl and T3PO signals are three phases of a 3 millisecond sampling list clock 21 for clocking in the SHKO signal into the flip-flops 22 100, 102 and 104. Thus, at a given instant in time, 23 the signal appearing on the Q outputs of the 24 flip-flops, constitute a 9 milliseconds "snapshot" of three successive SHKO bits.
26 With reference to Figure 5, signal 27 waveforms Q100, Q102 and Q104 are illustrated for the 28 Q outputs of corresponding flip-flops 100, 102 and 104 29 in response to the clocking in of a logic high SHKO
signal by the T3P2, T3Pl and T3PO signals of the 31 sampling list clock. With reference to sampling time 32 A in Figure 5, since the Q outputs of the flip-flops 33 are all high, then the SHKO signal must have been high 34 during the previous three samples, i.e. the SHKO
signal was high for at least 6 milliseconds.
36 Logic circuitry comprising NAND gates 106 37 and 108, NOR gates 110, 112, 118 and 120, and 38 flip-flops 114 and 116, performs a state code monitor 39 function for determining when three successive SHKO

1336l46 01 bits are identical and in response clock out a 02 corresponding debounced and stretched hookswitch bit 03 DSHK0. In the event at least one of the logic level 04 signals appearing on one of the Q outputs of the 05 flip-flops 100-104 is different from the others, the 06 debounced output DSHK0 bit does not change.
07 A signal STRTCH is received from an 08 additional flip-flop 126 forming part of a shift 09 register comprised of flip-flops 124-132. The flip-flops 124-132 perform timing signal generation 11 for stretching SHK0 bits having duration greater than 12 9 milliseconds but less than 16.5 milliseconds.
13 A better understanding of the operation of 14 the state code monitor circuit will be obtained with reference to Table 2, below:

FLIP-FLOPS NAND NOR NOR NAND NOR NOR

23 0 0 0 1 1 0 0 0 1*

1 1 1 0 0 1 1 0 1*

32 * when STRTCH = 0 33 A signal SDPOR is carried by the clock bus 34 32 connected to timing circuit 30, and is in the form of a logic high level for 12 milliseconds following 36 power up. Once the 12 milliseconds time period has 37 elapsed the SDPOR signal goes to a logic level low 38 thus enabling the debouncing and calibrated flash 39 functions of processing circuit 38 (Figure 3). In particular, the SDPOR signal is applied to a first 41 input of a NOR gate 134 having a second input 42 connected to the Q output of flip-flop 132. An output 01 of NOR gate 134 is connected to a first input of NAND
02 gate 136 having an output connected to a first input 03 of a further NAND gate 138. The output of NAND gate 854 138 is connected to the second input of NAND gate 136 06 as well as to the reset inputs R of flip-flops 07 126-132. A second input of NAND gate 138 is connected 08 to a further timing control signal output CC16BX from 09 the clock bus 32 (Figure 3), which signal is inverted via an inverter 140. The inverted CC16BX signal is 11 also applied to the enable input EN of flip-flops 114 12 and 116 discussed above.
13 A further timing control signal CC16X is 14 received from the clock bus 32 and inverted via an additional inverter 142 and applied to the clock input ~q C of flip-flop 124 and the complimentary enable input 18 EN of the flip-flops 114 and 116.
19 The output from NOR gate 118 is connected to the data input D of the first flip-flop 124 of the 21 bit stretching shift register. Enable inputs EN of 22 flip-flops 128-132 are connected to three phases of a 23 further timing control signals T6P2, T6Pl and T6PO
24 respectively. Each of the "T6" signals form a different phase of a 6 millisecond list clock signal.
26 In Figure 6A signal waveforms are 27 illustrated for timing control signals TGP2, TGPl and 28 TGPO in relation to timing control signals T3P2, T3Pl 29 and T3PO, and further in relation to timing control signals CC16X and CC16BX.
31 Thus, in operation, the logic level output 32 signal from NOR gate 118 is clocked through flip-flop 33 124 such that in the event of a transition in the 34 logic level output of NOR gate 118, a logic high level signal is clocked into the D input of flip-flop 126 36 and further clocked through flip-flops 128-132 for 37 application to the second input of NOR gate 134.
38 A better understanding of the operation of 39 the signal calibration portion of the circuit will be 13.364g~

01 obtained with reference to Figure 6B in which timing 02 and control signal waveforms are illustrated for the 03 case of a SHKO signal that maintains a logic high 04 level for at least 6-9 milliseconds. Signals T3-0,1,2 05 represent samplings of timing control signals T3P0, 06 T3Pl and T3P2 respectively, and signals TG-0,1,2, 07 represent samplings of timing control signals TGP0, 08 TGPl and TGP2 respectively. The sampling arrows are 09 shown for illustrative purposes and represent the signals at the Q outputs of flip-flops 100, 102 and 11 104.
12 As stated previously the T3P0, T3Pl and 13 T3P2 timing control signals clock in the SMK0 signal 14 into flip-flops 100, 102 and 104, and at a given instant in time, the signal appearing on the Q outputs 16 of the flip-flops constitute a 9 milliseconds snapshot 17 of three successive SHEO bits.
18 With further reference to Table 2, the 19 output of NOR gate 118 assumes a logic high level when the Q outputs of flip-flops 100, 102 and 104 are of 21 different logic levels, and assumes a logic low value 22 when the Q outputs are all of the same logic level.
23 Thus, the output of NOR gate 118 assumes a 24 logic low value when the SHKO signal maintains a logic high level for at least 6-9 milliseconds.
26 The transition of the output of NOR gate 27 118 from a logic high to a logic low level is 28 transferred to the output Q of flip-flop 124 during a 29 logic high to logic low transition of timing control signal CC16X (not shown).
31 Moreover, just prior to the output Q of 32 flip-flop 124 going low and during the time period 33 during which CC16X is high, the output of NOR gate 118 34 and the output Q of flip-flop 126 (STRTCM) are both low, thus the output of ~OR gate 120 assumes a logic 36 high level, enabling the Q output of flip-flop 104 to 37 be sampled and sent to the Q output of flip-flop 122 -01 (DSHKO). Thus, the signal DSHKO transforms from a 02 logic low level to a logic high level.
03When the Q output of flip-flop 124 04 (STRTCH) transforms from a logic low to a logic high 8~ level, the Q output of flip-flop 126 (DSHKO) is set to 88 a logic low level by an R input of flip-flop 126 09 assuming a logic low level. The reset input R of 10flip-flops 126-132 is derived from NOR gate 134, NAND
11gate 126, NA~D gate 138 and by logic inputs SDPOR, the 12 Q output of flip-flop 132 and timing control signal 13 CC16BX (not shown).
14Operation of the logic circuitry 15controlling resetting of flip-flops 126-132, will be 16 better understood with reference to the following 17 table:

~1LOGIC LEVEL SIGNAL OUTPUTS

23 SDPOR FLIP-FLOP CClGBX NOR NAND NAND

33As stated previously the SDPUR signal is 34 at a logic high level for only a 12 millisecond time period following power up. Thus in steady-state when 36 a STRTCM signal (Q output of flip-flop 126) propagates 37 through to the Q output of flip-flop 132, the output 38of NAND gate 138 (reset for flip-flops 126-132) will 39 assume a logic low level as soon as timing control signal CC16X assumes a logic low level.
41Thus, in operation from the time that 42 DSHKO transforms from a logic low to high level to the 43 time that the reset occurs, two 6 millisecond samples 44 and one-half of the 3 millisecond clock periods 01 elapse, effectively making DSHKO at least 13.5 02 millisecond in duration.
03 Considering the calibrated flash portion 04 of the circuit, a plurality of flip-flops 144-156 are 8~ linked together in the form of a ripple counter. In 88 particular, the Q and Q outputs of flip-flops 144-152 ~0~ are connected to the C and C inputs respectively of flip-flops 146-154. The Q output of flip-flop 154 is 13 connected to the reset input R of the last flip-flop 14 156, as well as to a first input of NAND gate 158. A
second input of ~AND gate 158 receives a timing signal ~7 T6MX at a period of 6 milliseconds, and the output of 18 NAND gate 158 is connected to the C input of flip-flop 144, and inverted via inverter 160 and applied to the ~2 C input of flip-flop 144.
23 Accordingly, the Q outputs of flip-flops 24 144, 146, 148, 150, 152 and 154 comprise respective outputs of the ripple counter, carrying clock signals 26 denoted as EDGE 6, EDGE 12, EDGE 24, EDGE 48, EDGE 96 27 and EDGE 192 respectively.
28 The Q output of flip-flop 148 is connected 29 to the enable input EN of flip-flop 156. The data input D of flip-flop 156 is connected a logic high 31 voltage level and the set input S is connected to 32 ground. The Q output of flip-flop 156 carries the 33 calibrated flash signal CF for the first TDM channel, 34 designated as CF0.
The CF0 signal is applied to a first input 36 of a NAND gate 162, the second input thereof being 37 connected to the output of NOR gate 118 via an 38 inverter 164. An output of NAND gate 162 is connected 39 to a first input of a further NAND gate 166 having a second input thereof connected to the Q output of 41 flip-flop 122 for receiving the DSHK0 signal. An 42 output of NAND gate 166 is inverted via inverter 168 43 and applied to a first input of a NOR gate 170. The 1336446`
01 second input of NOR gate 170 is connected to the clock 02 bus 32 (Figùre 3) for receiving the aforementioned 84 SDPOR signal. The output of NOR gate 170 is connected 05 to the reset input R of each of the flip-flops 06 144-154.
07 In operation, the flip-flops 144-154 are 08 reset in response to the output of NOR gate 170 going 09 to a logic low level.
Operation of the logic circuitry 11 controlling resetting of the ripple counter, will be 12 better understood with reference to the following 13 table:

38 Accordingly, it is seen that the ripple 39 counter is in a state of reset, and does not count whenever the SDPOR signal is at a logic high level 41 (i.e. for the first 12 milliseconds after power up), 42 as well as whenever the DSHK0 signal is at a logic 43 high level and the outputs of NOR gate 118 and CF0 are 44 not at logic low and logic high levels respectively.
A better understanding of the operation of 46 the calibrated flash portion of the circuit will be 01 obtained with reference to Figure 6B with 02 consideration of the case of the signal DSHKO on a 03 transition from a high logic level to a low logic 04 level and the signals SDPOR and CFO at a logic low 05 level.
06 As stated previously, when DSHKO is at a 07 logic high level and NOR gate 118 and the Q output of 08 flip-flop 156, (output CFO) are not at logic low and 09 high levels respectively, the ripple counter is in a state of reset until the signal DSHKO assumes a logic 11 low level i.e. the output of NOR gate 170 is at a 12 logic high level.
13 Once the signal DSHKO makes a transition 14 from a logic high level to a logic low level i.e. the output of NOR gate 170 is at a logic low level, the 16 clocking signal TGMX will start a ripple count through 17 flip-flops 144-154.
18 Turning to Figure 7, signal waveforms are 19 illustrated for the Q outputs of flip-flops 144-154 and 156 (output CFO) which comprise respective outputs 21 of the ripple counter. Q144-Q156 represent the Q
22 outputs of flip-flops 144-156 respectively and 23 illustrate signal waveforms that result in response to 24 the clocking signal TGMX starting a ripple count ~ through flip-flops 144-154.
27 As stated previously, the Q outputs of 28 flip-flops 144, 146, 148, 150, 152 and 154 comprise 29 respective outputs of the ripple counter, carrying clock signals denoted as EDGE 6, EDGE 12, EDGE 24, 3~ EDGE 48, EDGE 96 and EDGE 192 respectively (Figure 4).
33 The Q outputs of flip-flops 144 (EDGE 6), 34 148 (EDGE 12), 150 (EDGE 24), 150 (EDGE 48), 152 (EDGE
96) and 154 (EDGE 192) change from a high logic level 36 to a low logic level 6, 12, 24, 48, 96 and 192 37 milliseconds respectively after the ripple count has 1336~46 ~ started.
03 The Q output of flip-flop 150 (EDGE 24) is 04 applied to the EN input of flip-flop 156 and it is 05 seen that EDGE 24 is set to a logic low level then the 06 Q output of flip-flop 156 (CFO) will be set to a logic 07 high level. This is dependent on the condition that 08 the signal DSHKO remains at a logic low level after 09 the transition from a logic high level to a logic low level for a time period greater than 18 milliseconds, 11 i.e. 4 counts of the 6 millisecond sample clock TGMX.
12 If however, the signal DSHKO remains at a logic low 13 level for a period less than 18 milliseconds, the Q
~ output of flip-flop 150 (EDGE 24) will remain at a 16 logic high level and the Q output of flip-flop 150 17 (EDGE 24) will remain at a logic high level and the Q
18 output of flip-flop 156 (output CFO) will remain at a ~ logic low level.

2~ The Q output of flip-flop 154 (EDGE 142) 23 is applied to the R input of flip-flop 156 and it is 24 seen that if EDGE 142 is set to a low logic level then the Q output of flip-flop 156 (CFO) will be set to a 26 logic low level.
27 The total time of which the Q output of 28 flip-flop 156 (CFO) is at a logic high level is the 29 time interval between EDGE 142 and EDGE 24, i.e.
192-24 milliseocnds = 168 milliseconds.
31 Thus, according to the circuit of Figure 32 4, the DSHK0 signal provides a stretched and debounced 33 version of the SHK0 signal applied thereto, and the 34 CF0 signal provides a calibrated flash signal which is valid for 200 milliseconds after a valid hookswitch 36 flash.
37 As discussed previously, the DSHK and CF
38 signals output from respective ones of the signal 39 calibration circuits are applied to the output multiplexer 40 (Figure 3) via respective 16 bit 41 parallel busses. The serial output from the 01 muliplexer 40 is applied to the backplane (Figure 1) 02 for sampling via the peripheral controller 9.
03 In summary, according to the present 04 invention there is provided a signal calibration 05 circuit for receiving the hookswitch bits SHK from 06 respective line circuit cards and in response 07 generating a calibrated hookswitch signal DSHK and a 08 calibrated flash signal CF which are then sampled by a 09 peripheral controller. By debouncing and stretching the SHK and CF signals, the peripheral controller is 11 able to sample the signals at a relatively low 12 sampling rate, thereby freeing up additional processor 13 time for other functions. However, according to the 14 circuit of the present invention, relatively short hookswitch flashes, as well as dial pulsing can be 16 accurately detected.
17 The circuitry of the present invention can 18 be advantageously disposed on an uncommitted logic 19 array (ULA) and disposed between respective ones of the line circuit cards and the peripheral controller 21 backplane in a communication system, such as a PABX.
22 By implementing the present invention on a ULA, 23 circuit board area is optimized, and additional 24 circuitry such as timing generation, etc., may be incorporated within ULA to further decrease circuit 26 board real estate. Of course, the circuitry can also 27 be implemented using discrete components, with the 28 resultant sacrifices in circuit board area.
29 A person understanding the present invention may conceive of other embodiments or 31 variations therein.
32 For example, the principles of the present 33 invention may be applied to any system requiring 34 digital sampling of pulses having predetermined durations. It is contemplated that a multiplicity of 36 applications outside of the telecommunications field 37 are possible. The circuit of the present invention 01 can be inserted in any digital serial data stream for 02 debouncing or filtering short data pulses and 03 extending or stretching valid data pulses to a 04 predetermined duration for sampling via a computer or 05 other digital sampling circuitry at a slow sampling 06 rate.
07 These and other embodiments or variations 08 are believed to be within the sphere and scope of the 09 present invention as defined by the claims appended hereto.

Claims (9)

1. In a communication system including one or more signal ports for generating serial data signals comprised of logic high and logic low level pulses, and a peripheral processor connected to said signal ports for sampling said data signals, a signal calibration circuit comprised of first means for receiving said logic high and logic low level pulses, and in response eliminating transient ones of said pulses having durations less than a first predetermined time period, and second means for detecting further ones of said pulses having durations greater than said first time period and less than a second predetermined time period and in response lengthening each of said further pulses to a duration equal to said second predetermined time period, whereby said peripheral processor is able to sample said serial data signals at a sampling rate of at least one sample per said first predetermined time period.

2. A signal calibration circuit as defined in claim 1, including additional means for detecting logic low level pulses having duration greater than a third predetermined time period greater than said second time period, and in response generating a calibrated logic high level signal having duration equal to a fourth predetermined time period greater than said third time period for sampling by said peripheral processor at a further sampling rate of at least one sample per said fourth predetermined time period and less than one sample per said third predetermined time period.

3. A signal calibration circuit as defined in claim 2, wherein said first, second, third and fourth predetermined time periods are approximately 6 msec, 13.5 msec, 18 msec and 168 msec, respectively.

4. A signal calibration circuit as defined in claim 1, 2 or 3 further comprised of:
(a) a 3-stage shift register for receiving and clocking said logic high and logic low level pulses at a rate equal to said first predetermined time period, (b) an output latch for receiving and latching said pulses clocked via said shift register, (c) logic circuitry connected to said shift register and output latch, for detecting successive opposite polarity ones of said pulses and in response disabling said output latch, thereby eliminating transient pulses, and (d) timing circuitry connected to said shift register and output latch for controlling said clocking of said logic high and logic low level pulses and said latching of said pulses clocked via said shift register, for lengthening said further pulses to said duration equal to said second predetermined time period.

5. A signal calibration circuit as defined in claim 2, wherein said additional means is comprised of a ripple counter for generating a plurality of digital count signals, a predetermined one of said count signals for changing logic levels once per said fourth predetermined time period, and logic circuitry connected to reset inputs of said counter for detecting said logic low level pulses having duration greater than said third predetermined time period, and in response generating a reset signal for resetting said counter.

6. A signal calibration circuit as defined in claim 2 or 3 wherein said first, second and additional means are disposed on a signal chip ULA.

7. In a communication system including one or more signal ports for generating serial data signals comprised of logic high and logic low level pulses, a method for calibrating said data signals for sampling at a predetermined sampling rate, comprising the steps of:
(a) receiving said logic high and logic low level pulses, (b) eliminating transient ones of said pulses of duration less than a first predetermined time period, (c) detecting further ones of said pulses of duration greater than said first time period and less than a second predetermined time period, and (d) lengthening each of said further pulses to a duration equal to said second predetermined time period, whereby said lengthened pulses can be sampled at said sampling rate, said sampling rate being at least one sample per said second predetermined time period and less than one sample per said first predetermined time period.

8. A signal calibration circuit, comprised of:
(a) means for receiving a digital input signal comprised of logic high and logic low level pulses, (b) means for eliminating transient ones of said pulses from said signal, said transient pulses being of duration less than a first predetermined time period, and (c) means for lengthening the duration of further ones of said pulses from a second predetermined time period greater than said first time period to a third predetermined time period greater than said first and second time periods, whereby said input signal is debounced and calibrated enabling sampling thereof at a low sampling rate.

9. A signal calibration circuit as defined in claim 8, wherein said means for eliminating transient ones of said pulses is comprised of a shift register having a plurality of stages for receiving successive pulses of said signal, logic circuitry for detecting the polarity of said successive pulses received by individual ones of said stages and generating a control signal in response to detection of three successive pulses of alternating polarity, and a latch circuit for receiving said input signal from said shift register and said control signal from said logic circuitry, for transmitting said digital input signal unmodified in the absence of receipt of said control signal and reversing the polarity of the second of said three successive pulses in response to receiving said control signal.