CA1325260C - Beamforming/null-steering adaptive array - Google Patents

Abstract

BEAMFORMING/NULL-STEERING ADAPTIVE ARRAY

ABSTRACT OF THE DISCLOSURE

A beamforming adaptive control loop is simultaneously employed in combination with a null-steering adaptive control loop to enhance the signal/interference ratio resulting in an increase in the message quality. The loops may employ temporal processing in which case on-epoch sample/hold filters and off-epoch sample/hold filters form separate loops which enhance the desired signal and cancel the undesired signal, respectively. The correlated output from the beamforming loop is added to the correlated output of the null-steering loop and mixed with the incoming signal.

Description

1 ~a~ QUND OF THE INVENTION

3 1. Field of the Invention 4 The invention generally relates to an apparatus for adaptive signal processing and, in 6 particular, an adaptive processor including beamforming 7 and null-steering for an array antenna.

9 2. Description of the Prior Art Phase-coded spread spectrum communication 11 signals may be acquired and synchronized in the presence 12 of interference with the aid of an adaptive array 13 antenna under the control of a well-known LMS (least 14 mean square) algorithm performing power minimization.
However, the signal to interference (S/I) ratio at the 16 adaptive array output port of a system using this type 17 of processing, although adequate for acquisition and 18 synchronization, provides undesirable message quality 19 which, at best, is several decibels below the theoretical maximum obtainable when direction of arrival 21 (beam steering) information is available.

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1 In narrow band interference (e.g., AM

2 radios) communication systerns, the spectral bandwidth 3 of the interference source is significantly wider than 4 the desired signal's bandwidth. Null~steering in such a case may be obtained by an LMS algorithm with 6 spectral preconditioning of control signals of an 7 adaptive processor to prevent null formation on the 8 desired signal.

9 SUMMARY ûF THE INVENTION

It is an object of this invention to 11 provide an adaptive processor which performs 12 simultaneously beamforming and null-steering.
13 It is another object of this invention to 14 provide adaptive processing with a first adaptive control loop having off-epoch sample/hold filters and 16 a second adaptive control loop having on-epoch 17 sample/hold filters.
18 The invention includes an apparatus for 19 cancelling interference effecting a desired signal, which interference is produced by a source distant 21 from a source of the desired signal. First means 22 provides the desired signal and any undesired signal 23 received with the desired signal and is associated . , : . ' . ; :

1 with a null-steering means for separating the desired 2 signal and the undesired signal. The null-steering 3 means cancels at least a portion of the undesired 4 signal. A beamforming means is also associated with the f`irst means for separating the desired siqnal and 6 the undesired signal and enhancing at least a portion 7 of the desired signal. Second means are provided for 8 coordinating the null-steering means and the 9 beamforming means. The null-steering and beamforming loops employ ON and OFF epoch processors. The 11 null-steering means is operative to reduce the gain of 12 the radiation pattern of an array antenna in the 13 direction of the source of the interference. The 14 beam-forming means is operative to increase the gain of the radiation pattern of the array antenna in the 16 direction of the source of the desired signal.
17 For a better understanding of the present 18 invention, together with other and further objects, 19 reference is made to the following description, taken 2û in conjunction with the accompanying drawings, and its 21 scope will be pointed out in the appended claims.

23 Figure 1 is a block diagram of an array 24 antenna with adaptive processor according to the invention.

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1 Figure 2 is a block diagram of a wideband 2 spread spectrum temporal processor for one of a set of 3 signal channels of Figure 1 according to the invention.
4 Figure 3 is a block diagra~ of an epoch processor of Figure 2 according to the invention.
6 Figure 4 is an array antenna pattern in 7 the horizontal plane illustrating null-steering 8 simulation.
9 Figure 5 is an array antenna pattern in lû the horizontal plane illustrating beamforming/null-11 steering simulation according to the invention.

13 Figures 1-3 are single line block diagrams 14 used generally to represent a vector system with multiple signals. As used herein, references to a 16 "line" are intended to generally mean multiple paths 17 transmitting more than one signal. Similarly, 18 references to "mixers" generally mean multiplication 19 with vectorial weights for combining multiple signals.
2û Figure 1 illustrates in block diagram form 21 the general features of the invention. Practice of 22 the invention is demonstrated with reference to an 23 array antenna 30û having four antenna elements 3ûl, 24 302, 3û3, and 304 positioned for receiving an electromagnetic signal. It should be understood that, ' 1 32526~
1 while the invention will be described with reference 2 to reception of electromagnetic signals, the theory of 3 the invention is applicable equally to the reception 4 of sonic signals in which case the elements of the antenna would be transducers for converting sonic 6 energy to electric energy. The four elements 301-304 7 of the antenna 300 are presented by way of example, it 8 being understood that many more elements may be 9 employed in practice. Also, in the general case, it is to be understood that the elements 301-304 may be 11 positioned in a straight line or on a curved surface 12 in accordance with the circumstances under which the 13 antenna 300 is to be deployed. The situation in which 14 the elements of the antenna 3ûû are to be positioned along a curved surface is found in the locating of 16 antenna elements on an aircraft in which case the 17 elements may be positioned on the curved surface of a 18 fuselage or wing of the aircraft.
19 Adaptive processing of input signals received at the elements 301-304 is accomplished by 21 adaptive signal processors 305, 306, 307, and 308, 22 respectively, coupled to the elements 301-304. Output 23 signals of the processors 305-308 are applied to input 24 terminals of a summer 309 which sums together the output signals of the processors 3û5-3û8 to output on 26 line 310 a combined signal of the contributions of all 27 of the elements 301-304 of the antenna 300. The .. : : - . ,.. : . ~ :
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1 output signal on line 31û is also fed back to each of 2 the processors 305-308 to be used as a reference 3 signal in the generation of weighting factors which 4 are applied by the processors 305~3û8 in an adaptive fashion to the input signals of the respective 6 elements 301-304 in accordance with the invention as 7 will be described hereinafter.
8 It is noted that each of the processors 9 305-3û8 in combination with its respective antenna lû element 3û1-304 constitutes a separate signal 11 processing channel, each channel sharing the summer 12 309 in common to provide the common reference signal 13 on line 310. Each of these channels operates in the 14 same fashion and comprises the same circuitry.
Accordingly, in the ensuing description of the 16 invention, the description will be directed to the 17 circuitry of one of the channels, namely the circuitry 18 within the processor 305, it being understood that 19 this description applies equally well to the other processors 306-308. The overall configuration of a 21 set of processors sharing a common summer for 22 weighting antenna signals is well known and need not 23 be described further for an understanding of the 24 invention. The invention resides within the circuitry of a single processor, such as the processor 3ûS, as 26 will now be described.

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1 As shown in Figure 1, a desired signal 2 with undesired signals (i.e., interference) is 3 provided by line lû to mixer 11. The desired signal 4 with interference is also provided via line 12 to beamforming circuit 200 and via line 13 to 6 null-steering circuit 100. The output of 7 null-steering circuit 100 is provided via line 14 to 8 coordinator 15 and added to the output of beamforming 9 circuit 200 provided via line 16. The coordinated sum is provided via line 9 to mixer 11, and further 11 combined with the corresponding signals of the other 12 channels by the summer 309, so that mixed output lines 13 310 and 17 carry the desired signal with interference 14 mixed with the output of coordinator 15. This mixed signal is provided via line 18 to beamforming circuit 16 200 and via line 19 to null-steering circuit lOû.
17 Effectively, the null-steering circuit 100 functions 18 as a first vector loop 1 to cancel at least a portion 19 of the interfering signals. Conversely, the beamforming circuit 200 functions as a second vector 21 loop 2 to enhance at least a portion of the desired 22 signal so that the mixed signal provided by line 17 23 has an enhanced S/I ratio and hence message quality.
24 The null-steering circuit and beamforming circuit may accomplish their functions by temporal 26 processing or by spectral processing. In the 27 processing of phase-coded wideband spread spectrum , ~

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1 communication signals, temporal processing may be 2 employed as illustrated in a detailed diagram of the ~ processor 3û5 in Figure 2.
4 As shown in Figure 2, the desired and interfering signals may be provided via line 10 to an 6 automatic gain control circuit (AGC) 20 for 7 stabilizing the signal amplitude. The output of AGC
8 20 is applied via line 21 to matched filter 22 and 9 coded with the particular code of the desired signal.
The output of matched filter 22 is provided via line 11 23 to first wideband vector weight control loop lWB
12 for null-steering and second wideband vector weight 13 control loop 2WB for beamforming. In the first vector 14 loop lWB, the reference signal provided by line 24 and feedback signal provided by line 25 are processed by 16 off-epoch sample/hold filter circuit 101 and off-epoch 17 sample/hold filter circuit 103, respectively. The 18 processed signals are provided to correlator 102 for 19 weighting the signal of antenna element 301 with the output of correlator 102 provided by line 106 to adder 21 28. This effectively removes the desired signal from 22 the control signal of a modified LMS algorithm 23 effected in loop lWB by correlator 102 with the minus 24 sign in the vector loop lWB shown at adder 28 representing implementation of a minimization process.
26 In the second vector loop 2WB, the 27 reference signal provided by line 26 and the feedback _ g_ ;. - . .
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1 signal provided by line 27 are processed by on-epoch 2 sample/hold filter circuit 2ûl and on-epoch 3 sample/hold filter circuit 203, respectively. The 4 processed signals are provided to correlator 202 for weighting with the output of the correlator lû2 6 provided by line 206 to adder 28. The second loop 2WB
7 enhances the desired signal to interference power 8 ratio of the control signal of a modified LMS
9 algorithm effected by correlator 202 with a net positive signal shown at adder 28 representing 11 implementation of a maximization process.
12 Correlator 102 of vector loop lWB
13 comprises mixer 104 for mixing the output of the 14 off-epoch circuits 101 and 103 and integrator 105 for integrating the mixed outputs. Correlator 202 of 16 vector loop 2WB comprises mixer 204 for mixing the 17 outputs of on-epoch circuits 201 and 203 and 18 integrator 205 for integrating the mixed outputs. The 19 output (line 106) of correlator 102 of loop lWB is added to the output (line 206) of correlator 2û2 of 21 loop 2WB by adder 28 and the sum is mixed by mixer 29 22 with the input signal provided by line 23 resulting in 23 a mixed output signal provided by line 17.
24 The epoch processing circuits 101 and 201 are fabricated conveniently as a single unit 311 and, 26 similarly, the epoch processing circuits 103 and 203 27 are fabricated conveniently as a single unit 312.

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1 Both of the units 311 and 312 have the same 2 configuration and, accordingly, only the unit 311 need 3 be described in detail, it being understood that the 4 description thereof applies also to the unit 312. A
unit 311 is found in each of the processors 305-308 of 6 Figure 1. Also, a unit 312 may be placed in each of 7 the processors 3û5-3û8 or, alternatively, only one 8 unit 312 need be provided for the entire antenna 300, 9 with the output signals of the single unit 312 being 10 employed by all of the processors 305-308.
11 With reference to Figure 3, there is shown 12 a block diagram of epoch processing circuits contained 13 within the unit 311, the description in Figure 3 14 applying also to the epoch processing unit 312. Output signals are applied to the mixers 104 and 204 as shown 16 in Figure 2. The input signal to the epoch processing 17 circuits are obtained from line 23 in the case of the 18 unit 311, and from the line 17 in the case of the unit 19 312.
The unit 311 comprises an envelope 21 detector 313, a threshold unit 314, a clock 315, a 22 counter 316, and two signal generators 317 and 318 for 23 producing an early-gate signal and a late-gate signal 24 respectively. Input signals from line 23 are detected by the detector 313 which outputs the amplitude of the 26 signal envelope to the threshold unit 314. The 27 counter 316 counts clock pulses applied thereto by the .

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1 clock 315. The threshold unit 314 outputs a command 2 signal to the counter 316 during the interval of time 3 when a detector 313 outputs a signal amplitude above 4 the threshold of the unit 314. Thereby, the counter 316 is activated and deactivated to count the duration 6 of a pulse of the input signal. The counter 316 7 strobes the generators 317 and 318. In the case of a 8 repetitive input signal, as is the usual case in radar 9 communication, the strobing of the generator 317 lû activates the generator 317 to output an early-gate 11 signal, indicated graphically at 319, which extends in 12 time from a point prior to the input signal pulse to 13 the end of the input signal pulse. Similarly, the 14 strobing of the generator 318 activates the generator 318 to output a late-gate signal, indicated 16 graphically at 32û, extending in time from a point at 17 the beginning of the input pulse signal to a point 18 after the conclusion of the input pulse signal. The 19 two signals 319 and 320 overlap during the interval of time of the next anticipated occurrence of the input 21 pulse signal.
22 The units 311 further comprises two gates 23 321 and 322, two low-pass filters 323 and 324, and a 24 subtractor 325. Both of the gates 321 and 322 have input terminals connected to the detector 313 for 26 receiving signals outputted by the detector 313. The 27 gates 321 is activated by the early-gate signal 319 of ;~ -12-. , . . .

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1 the generator 317 to pass detector signals to the 2 filter 323 during the early-gate. The gate 322 is 3 activated by the late-gate signal 32û of the generator 4 318 to pass detector signals to the filter 324 during the late-gate. The filters 323 and 324 average the 6 signals applied repetitively by the gates 321 and 7 322. The average values outputted by the filters 323 8 and 324 are subtracted by the subtractor 325 to 9 produce an error signal which indicates any error in the emplacement of the gate signals 319 and 320 about 11 an input signal pulse. The error signal is applied to 12 the clock 315 to advance or retard the occurrence of 13 clock pulses as commanded by the error signal, thereby 14 to align the overlapping region of the gate signals 319 and 320 with the input signal pulse. Stylized 16 representations of the signals outputted by the 17 early-gate 321 and the late-gate 322 are indicated at 18 326 and 327.
19 The unit 311 also comprises two gates 328 and 329, a delay unit 330 and a summer 331. The 21 summer 331 provides an AND function between the 22 early-gate signal 319 and the late-gate signal 32û to 23 output a signal on line 332 having a value of logic-l 24 during the overlap region of the two signals 319 and 320, and a value of logic-û otherwise, the overlap 26 region between the two signals 319 and 320 is 27 indicated graphically at 333. The logic-l signal ... ..
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1 outputted by the summer 331 is indicated at 334.
2 The signal 334 indicates the expected time 3 of arrival of the next input signal pulse on line 23, 4 and is applied to a terminal of the gate 329 to activate the gate 329 to conduct a signal from line 23 6 to the mixer 2û4. This is termed the on-epoch part of 7 the transmission of signals received by the antenna 8 element 301. The signal 334 is also coupled via the 9 delay 33û to a terminal of the gate 328 to activate lû the gate to couple signals from the line 23 to the 11 mixer lû4. The delay imparted by the delay unit 330 12 is sufficient to offset the activation interval of the 13 gate 328 to a time after termination of the on-epoch 14 of the gate 329. Accordingly, the interval of activation of the gate 328 is termed an off-epoch 16 portion of the signal received at the antenna element 17 3ûl.
18 In operation, the epoch processiny 19 circuitry of the unit 311 provides for a tracking of 2û the substantially periodic occurrences of pulses of 21 the input signal outputted by the match filter on line 22 23. The tracking of the input signal pulse is 23 employed to operate the on-epoch gate 329 and the 24 off-epoch gate 328 to provide samples of the signal energy during the times of receipts of the desired 26 signal, and during the times wherein an interfering 27 signal may be received. The off-epoch interval ' '' : ' `'.' '. ..

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1 provides jamming data utilized by the loop lWB
2 (Figure 2) for directing a null in the direction of an 3 interfering signal. The on-epoch interval provides 4 energy of the desired signal which is employed by the loop 2WB (Figure 2) for maximizing the gain of the 6 antenna 300 in the direction of a source of the 7 desired signal. It is also noted that in the 8 operation of the processor 305, that the integration 9 operation of the correlators 102 and 202 converts the lû pulsed signal outputted by the epoch gates 328 and 329 11 to continuous signals applied to the adder 28 for 12 formation of a continuously present weighting factor 13 applied to the mixer 29. Thereby, the epoch 14 processing circuits in conjunction with the correlators provide the adaptive control, loops with 16 the characteristic of a sample-hold filter circuit 17 with the temporal filtering being accomplished by the 18 late and early-gate tracking operation.
19 Figures 4 and 5 illustrate the benefits of simultaneous null-steering and beamforming for a 21 five-element random spaced array of antennas with an 22 extent of 1 x 6 wavelengths in the azimuth plane and 2 23 wavelengths in elevation in a scenario consisting of 24 three equal strength jammers (Jl, J2, J3) which are lOdB above the desired signal at each antenna:

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1 32526a 1 Elevation Azimuth 2 Jammer 1 (Jl) 0 0.4 3 Jammer 2 (J2) 0 22.3 4 Jammer 3 (J3) 0 93.8 User (5) 0 62.2 6 Figure 4 is the adapted antenna pattern 7 attained from a null-steering only control on the full 8 signal band of fre4uencies for a loop bias condition 9 which results in a single element "on" quiescent weight vector. In the adapted state, all the jammers 11 are nulled by about 30dB and the desired signal(s) 12 falls on the sides of a null which leads to a net 13 improvement in S/J (signal to jammer) ratio of about 14 22dB. Figure 5 is the adapted pattern for the same scenario when the adaptive processor is configured 16 according to the invention employing both 17 null-steering and beamforming. In this adapted state, 18 the null in the vicinity of the desired signal(s) is 19 filled in leading to an additional 6d8 improvement in SiJ ratio.

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Claims (2)

1. Claim 1. An apparatus for cancelling undesired signals received with a desired spread spectrum signal, said apparatus comprising:
   first means for providing the desired and any undesired signals received with the desired signal;
   null-steering means, including a first temporal processing means associated with said first means, for temporally separating the desired and any undesired signals and cancelling at least a portion of any undesired signals;
   beamforming means, including a second temporal processing means associated with said first means, for temporally separating the desired and any undesired signals and enhancing at least a portion of the desired signal; and second means for coordinating said null-steering means and said beamforming means;
   wherein said first temporal processing means comprises a first adaptive control loop coupled to said first means, said first loop having a negative correcting output for minimizing the undesired signal;
   said second temporal processing means comprises a second adaptive control loop coupled to said first means, said second loop having a positive correcting output for maximizing the desired signal; and said second means comprises means for summing the negative correcting output and the positive correcting output, and a mixer for mixing the desired and any undesired signals with the sum to provide a mixed output;
   further wherein said first adaptive control loop comprises a first off-epoch sample-and-hold filter circuit coupled to the first means and providing an off-epoch unmixed output, a second off-epoch sample-and-hold filter circuit coupled to the mixed output and providing an off-epoch mixed output, and a correlator for correlating the off-epoch unmixed output with the off-epoch mixed output to provide said negative correcting output;
   and finally wherein each of said epoch filter circuits includes means for tracking a desired signal, said tracking means including an early-gate and a late-gate overlapping a time of occurrence of the desired signal, there being an off-epoch gate and an on-epoch gate driven by said tracking means, for extracting samples of the desired signal and any interfering signal.
2. Claim 2. The apparatus of claim 1 wherein said second adaptive control loop comprises a first on-epoch sample-and-hold filter circuit coupled to the first means and providing an on-epoch unmixed output, a second on-epoch sample-and-hold filter circuit coupled to the mixed output and providing an on-epoch mixed output, and a correlator for correlating the on-epoch unmixed output with the on-epoch mixed output to provide said positive correcting output; and wherein each of said on-epoch filter circuits includes means for tracking a desired signal, said tracking means including an early-gate and a late-gate overlapping a time of occurrence of the desired signal, there being an off-epoch gate and an on-epoch gate driven by said tracking means, for extracting samples of the desired signal and any interfering signal.