CA1294380C - Display system - Google Patents
Display systemInfo
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- CA1294380C CA1294380C CA000563038A CA563038A CA1294380C CA 1294380 C CA1294380 C CA 1294380C CA 000563038 A CA000563038 A CA 000563038A CA 563038 A CA563038 A CA 563038A CA 1294380 C CA1294380 C CA 1294380C
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- 239000000872 buffer Substances 0.000 claims abstract description 213
- 238000012545 processing Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- WTGQALLALWYDJH-WYHSTMEOSA-N scopolamine hydrobromide Chemical compound Br.C1([C@@H](CO)C(=O)OC2C[C@@H]3N([C@H](C2)[C@@H]2[C@H]3O2)C)=CC=CC=C1 WTGQALLALWYDJH-WYHSTMEOSA-N 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 101001129784 Autographa californica nuclear polyhedrosis virus Per os infectivity factor 0 Proteins 0.000 description 1
- 241000288147 Meleagris gallopavo Species 0.000 description 1
- 101800000089 Movement protein P3N-PIPO Proteins 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N ferric oxide Chemical compound O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Digital Computer Display Output (AREA)
- Image Input (AREA)
Abstract
DISPLAY SYSTEM
ABSTRACT
The present invention relates to a display system comprising a display buffer 36 data indicative of picture elements with a facility for moving an image from a source to a destination position by manipu-lating the data in the display buffer. The present invention provides this facility by having means for reading, processing and Storing bursts of display buffer words. In the described embodiment of the invention control logic 44 first causes a burst of display buffer words containing bytes representative of the image in its source position to be read out from the display buffer. These words are passed through a barrel shifter 66, where the word is rotated as necessary and stored in appropriate byte locations in a FIFO buffer 68. The FIFO buffer has the capability to write to two word addresses simultaneously so that data words are created in the FIFO buffer which contain data in the correct alignment for writing unmodified into the corresponding display buffer words. When the source has been completely read or the buffer is full (whichever comes first) the display adapter automatically switches from reading to writing and stores the burst of data words it has in its FIFO buffer into memory at the destination locations.
ABSTRACT
The present invention relates to a display system comprising a display buffer 36 data indicative of picture elements with a facility for moving an image from a source to a destination position by manipu-lating the data in the display buffer. The present invention provides this facility by having means for reading, processing and Storing bursts of display buffer words. In the described embodiment of the invention control logic 44 first causes a burst of display buffer words containing bytes representative of the image in its source position to be read out from the display buffer. These words are passed through a barrel shifter 66, where the word is rotated as necessary and stored in appropriate byte locations in a FIFO buffer 68. The FIFO buffer has the capability to write to two word addresses simultaneously so that data words are created in the FIFO buffer which contain data in the correct alignment for writing unmodified into the corresponding display buffer words. When the source has been completely read or the buffer is full (whichever comes first) the display adapter automatically switches from reading to writing and stores the burst of data words it has in its FIFO buffer into memory at the destination locations.
Description
UK9-87-00~ 1 DISPLAY SYSTEM
Description The present invention relates to a display system comprising a display buffer for data indicative of picture elements with a facility for moving an image from one position to another by manipulating the data in the display buffer.
In order to move images ~eg. a character) around or onto a display screen a technique commonly called "bit blit" or "bit blt" has been developed. ~ssentially, the technique involves the provision of logic for automatically copying data indicative of the picture elements (pels) forming an image in response to commands teg. using a mouse) identifying the image in its original, or source, position and in its destination position. In conventional bit-blit implementations a memory location is read and the data thus obtained is then written to another memory location thus copyinq one pel of the image. By incrementing the source ~read) and destination twrite) addresses appropriately, and repeating the operation, images (eg text or graphical characters) of any size can be moved a pel at a time.
This process can be used, both for copying images from one position I to another in a part of a display buffer which is actually scanned in order to generate a screen of displayed images, (ie. in an on-screen portion of the display buffer) and for copying images between an off-screen (ie. non visible) and an on-screen portion of a display buffer.
This latter technique is used in all points addressable (APA) display buffers for copying symbol definitions which are held in an off-screen part of a display buffer into an on-screen part of the display buffer when the symbols are actually to be displayed.
Conventionally, this is done by the system microprocessor which may use string move instructions if it is provided with them. The rates of blit obtained are, however, relatively low because of the limited bus 3~
~K9-87-008 2 bandwidth of microprocessor system and the very large amounts of data involved with large displays. ~s a consequence of this, it is not normally possible to move the image (unless it is very simple) around the screen in real time in response, for example, to mouse movements.
Also a not in-considerable time is taken to move an image from off-screen to on-screen storage.
The object of the present invention is to provide a display system With a mechanism for copying an image from a source position to a destination position which does not suffer from the disadvantages of prior art mechanisms.
This object is met by a display system comprising a word organised display buffer for storing bytes of data indicative of picture elements ~pels) with a plurality of bytes of data stored in each buffer word, and means for copying an image from a source position to a destination position, said means for copying comprising means for reading one or more bursts of source words from a first set of word locations in the display buffer, the source words including bytes of data indicative of pels for the image in its source position, means for rearranging the bytes of data in a burst of read source words so as to form a set of destination words in which the bytes of data indicative of pels for the image are in destination order within the words and means for writing the destination words generated from each burst of read source words in a write burst to a second set of word locations in the display buffer such that the bytes of data indicative of the pels for the image are stored in the correct display buffer byte locations for representing the image in its destination position.
In a preferred embodiment of the invention the means for rearrang-ing the bytes of data in a burst of source words comprises a word-wide barrel shifter for rotating a data word by a selectable integral ~umber of bytes, a plurality of word-wide registers organised as a first-in-first-out ~FIFO) buffer for temporarily storing said bytes of data indicative of pels for the image, FIF0 buffer addressing logic such that lZ943~0 individual bytes within the registers can be addressed, and control logic for providing control signals to the barrel shifter and to the FIF0 buffer addressing logic such that the bytes of data in a burst of read source words are rearranged so as to form a set of destination words in which said bytes of data indicative of pels for the image are in destination order within the words.
In a first example the barrel shifter is connected to the data output of the display buffer for receiving a source word read out of the display buffer and for rotating the source word by a selectable integral number of bytes. The data input of the FIFO buffer is connected to the output o~ the barrel shifter for receiving a rotated word and the data output of the FIFO buffer is connected to the data input of the display buffer. The control logic provides control signals to the barrel shifter and to the FIFO buffer addressing logic such that any byte in a rotated word which was rotated across the word boundary in the barrel shifter is stored in the FIF0 buffer in an appropriate byte location in a register adjacent to the reqister in which is stored any byte in the rotated word which which was not rotated across the word boundary in the barrel shifter, whereby the set of destination words in which said bytes of data indicative of pels for the image are stored in destination order within the words is stored in the FIFO buffer.
In an alternative example the FIFO buffer is connected instead to the data output of the display buffer for receiving a source word read out of the display buffer. The input to the barrel shifter is connected to the output of the FIF0 buffer for receiving a data word from the PIPO
buffer to be rotated by a selectable integral number of bytes and the output of the barrel shifter is connected to the data input of the display buffer. The control logic provides control signals to the barrel shifter and to the FIF0 buffer addressing logic such that any byte of said data word which is to be rotated across the word boundary in the barrel shifter is read from an appropriate byte location in a register adjacent to the register from which is read any byte in said data word which is not to be rotated across the word boundary in the barrel 3-29438~
shifter, whereby the set of destination words in which said bytes of data indicative of pels for the image are in destination order is formed by the rotated word at the output of the barrel shifter.
In the embodiments of the invention mentioned above, the means for reading one or more bursts of source words and the means for writing the destination words comprise means for generating a first set of display buffer addresses from which to read the source words and a set of display buffer addresses to which to write the destination words. The control logic causes the display buffer address generating means to generate a sequence of addresses from said first set, for a burst of source words to be read, until the FIFO buffer is full or until the words in which bytes of data inaicative of pels for the image in the source position are exhausted, which ever occurs first, and then cause the display buffer address generating means to generate a sequence of addresses from said second set forming a burst of write addresses until FIFO buffer is emptied of bytes of data indicative of the image. In addition~ the control logic can synchronise the addressing of the display buffer and the operation of the means for rearranging the bytes of data in a burst of read source words such that, after an appropriate number of bursts of source words have been read, rearranged and stored in the destination locations in the display buffer, the image is copied from the source position to the destination position.
A display system as above may include a display buffer which comprises an on-screen portion for storing bytes of data indicative of pels to be displayed on a display screen and an off-screen portion for bytes of data indicative of pels which are not displayed on a display screen. In this case the means for copying an image from a source position to a destination position will enable enable an image to be copied within one of the on-screen or off-screen portions and to be copied between said portions in either direction.
With a display system in accordance with the present invention alpha numericS, teXt and even graphics images can be moved around a 1~94380 display sereen in real t-'me (eg in response to mouse movements) which ean faeilitate the editing of screens containing images of all types (eg for page composition in desk-top publishing). It is possible to rapidly eopy images from an off-screen portion to an on-screen portion of an all points addressable (APA) display buffer in order to display symbols (eg.
charaeters) whose pel definitions are held in the off-screen portion. In this way a sereen of images, ineluding alpha numeries, text and even graphies, ean be ereated on a graphies display which is driven using an APA graphies display buffer with the performanee normally assoeiated with eoded buffer alphanumerics only displays.
In order to enable a more complete understanding of the present invention, there follows a particular description of a specific embodi-ment of a display system in aeeordanee with the present invention with referenee to the aeeompanying drawings in whieh:
Figure 1 is a bloek diagram of a workstation;
Figures 2A and 2B are sehematie diagrams illustrating, respective-ly, the relationship between pereeived pieture element (pel) positions on a display sereen and the eorresponding storage positions in a display buffer for data indieative of those pels;
Figure 3 is a sehematie biock diagram showing aspects of a display adapter ineluded in Figure l; and Figures 4 and 5 form a flow diagram illustrating aspects of the operation of the display adapter of Figure 3.
Figure 1 shows an overview of a workstation ineluding a display adapter in which the invention may be implemented. The workstation eomprises a number of different system units connected via a sy5tem bus 12. The system bus comprises a data bus 14, an address bus 16 and a control bus 18. Connected to the system bus is a microprocessor 10, random access memory 20, a keyboard adapter 28, a display adapter 32, an 1~:94380 I/0 adapter 22 and a communications adapter 26. The keyboard adapter isused to connect a keyboard 30 to the system bus. The display adapter, which forms a specific embodiment of the present invention, connects the system bus to a display device 34. The I/0 adapter likewise provides a connection between other input/output devices 24 (eg. DASDs) and the system bus, and the communications adapter allows the workstation to be connected to and to communicate with an external processor or processors such as a host processor (not shown).
The display adapter includes an all points addressable (APA) display buffer 36 which can be accessed by the display device in order to fetch the data corresponding to the individual picture elements on the screen (see Figure 2A). The data are fetched in synchronism with the scanning of the display screen. To facilitate this the information in the display buffer is organised in accordance with the scanning sequence of the display refresh circuitry. In addition to the on-screen, or visible portion of the display screen which is scanned by the display device, the display buffer also comprises an off-screen, or non-visible portion in which are stored images (eg. character or symbol definitions) which are not visible on the screen.
Figure 2A illustrates the display screen 38 as perceived. The screen has "Y" lines of "X" pel positions each. As shown the rows of the screen are numbered from 0 to Yl starting from the top and moving down the screen. The pel positions in each row are likewise shown numbered, from left to right, 0 to Xl. It will be appreciated that the numbering is purely an arbitrary choice and that other numbering schemes could have been chosen.
In order to generate the screen shown in Figure 2A, data is stored in a display buffer 36, the on-screen portion of which is represented in Figure 2B.
This specific display buffer is organised on words of 32 bits. Each pel is represented by an 8-bit byte of data defining the intensity . 1~94~80 and/or colour of the pel. It will be understood however, that other display buffer organisations are possible. For example, the buffer could be organised on words of another length and/or a different number of bits could make up a byte defining the intensity and/or colour of a pel (eg. 8 bit words and 4 bit bytes).
It will be noted that the display buffer is shown, for reasons of simplicity of explanation, as being organised from the bottom up as a linear stream of bytes within the buffer starting with the byte for the top left-most pel, followed by the bytes for the pels, from left to right, in the first row, the second row, and so on until the byte for the bottom right-~ost pel. The display buffer could be organised for a screen which i9 refreshed using an interleaved scanning technique (i.e.
where the scanning of even numbered rows alternates with the scanning of odd numbered rows) by arranging for the image data for the individual pels of the display screen shown in Figure 2A to be stored with the data relating to the even numbered rows stored in a first sequence from a first address in the display buffer and the data relating to the odd numbered rows stored in a second sequence starting at a second address at or after the end of the first sequence. Alternatively, the display buffer could be organised as a single sequence as shown in Figure 2B and the display scanning logic provided with the capability to extract the data it needs from the buffer in order to support an interleaved scanned .
display screen.
Figure 2A shows two rectangular blocks 40 and 42 which represent the source position 40 and the destination position 42 on the screen for a rectangular image to be moved. The rectangular image comprises a row of 6 pels, the top-left of which is initially located at the screen position b,a. The top-left of the destination position is d,c. Figure 2B
illustrates the source rectangle to be represented in the display buffer by a set of 6 bytes of data at 41. Likewise the destination rectangle is represented in the display buffer by a set of 6 bytes of data at 43. It will be noted that the alignment of the sets of data for the source and destination rectangles with respect to the word boundaries of the 1~43~0 display buffer tie. the left/right edges of the block at bit address 0/31 shown in Figure 2B) is different. It should be noted that a simple image lying on one row only of pels has been illustrated for reasons of ease of explanation. In practice the images to be moved will normally be larger and will normally cover a plurality of rows.
The display buffer in this adapter is formed from a 32 bit wide array of D-RAMS. The minimum addressing unit is one 32 bit word. The display buffer is, however provided with separate byte enables so that 0 to 4 bytes (each of 8 bits) may be written to as required for each write access with the remaining of the four bytes remaining unchanged. In this way the display buffer can be configured as an APA buffer so that each pel (ie. each 8-bit byte) can be selectively written to or not as the case may be even though four bytes (ie. a word) at a time are (is) addressed.
In view of this it would be possible to apply the prior art app-roach to moving an image on a display screen (ie. to successively read single bytes and each time to write the data thus obtained to the equivalent destination location in the buffer, thereby copying succes-sively sinqle pels until the whole image has been copied). This approach is, however, very slow because each byte is processed in turn. It would not be possible to simply read and write a word at a time because the position of a byte within the word boundaries may be different in the source and destination words as illustrated in ~igure 2B.
The present invention provides a solution to this problem by providing means for reading, processing and storing bursts of display buffer words.
Although, in the specific embodiment of the invention described herein the display buffer is implemented in D-RAMS and can be accessed on both word and byte boundaries, the present invention is not limited to such an organisation. It can equally be implemented with a display buffer in some other technology and where the buffer can only be accessed on the word boundaries and not on the byte boundaries.
~2943~
If the display buffer is implemented in D-PAMS, however, and if consecutive words in the display buffer are arranged to define consecu-tive sets of four pels, the burst operation of the present invention allows, for example, a D-RAM "page mode" feature to be utilised which provides a further significant performance advantage. "Page mode" is a feature conventionally provided in D-RAMS which, as a consequence of their internal chip organisation, allows faster access to sequential locations than to random locations.
Figure 3 is a schematic block diagram showing the interrelationship between various functional elements in the display adapter shown in Figure 1 which forms the specific embodiment of the present invention.
The adapter comprises a control unit 44 which is connected to the address bus 16 and to the control bus 18. Associated with the control unit is control storage 46 which is connected to the data bus 14 for the receipt of initialisation data from the workstation RAM.
The inputs to Y and x source registers 48 and 50 and Y and X
destination registers 52 and 54 are also connected to the data ~us 14 for receiving initial position data as part of the initialisation data to be explained later. Connected to the outputs of the Y and X source and the Y and X destination registers are Y and X source and Y and X
destination counters 56, 58, 60, 62, respectively. An arithmetic logic unit 64 has four inputs each connected to the output of a respective one of the four counters 56, 58, 60, 62. The oUtput of the arithmetic unit is connected to the address input of the display buffer 38.
The data outpUts of the display buffer 36 are connected in parallel to the inputs Of a barrel shifter 66 known per se, and whose purpose is to rotate a data word input thereto by an integral number of byte positions. The data outputs of the barrel shifter are connected in parallel to the data inputs of a FIF0 ~uffer 68 which is formed from a plurality tin this display adapter, eight) word-wide registers. The FIFO
buffer is provided with addressing logic 70 such that individual bytes in the FIFO buffer may be separately addressed and such that individual 129~3~30 ~K9-87~008 10 bytes presented simultaneously on the data inputs to the FIFO buffer may be stored in different words. The FIE'O buffer addressing logic contains byte pointers for indicating the start and finish of data in the FIFO
buffer, whereby the FIFO buffer addressing logic can determine when the buffer is full, and when it is empty. The data outputs of the FIFO
buffer are connected back to the data inputs to the display buffer.
Although shown as being separate, the data inputs and outputs of the display buffer may in fact be common - likewise for the FIFO buffer.
The control unit is connected via control inputs C to the control storage, the Y and X registers, the Y and x counters, the arithmetic logic unit the display buffer, the barrel shifter and the FIFO buffer address logic. The FIFO buffer address logic is also connected to the control logic for passing "buffer full" and "buffer empty" signals.
In this particular display adapter the various functional units shown are provided in the form of a special purpose circuitry. The logic units for example are provided by combinatorial logic. The present invention does not however, exclude the possibility of imple-menting the logic in a software-and-processor-based system.
An image to be copied is processed by the display adapter in bursts. The control logic first causes a burst of display buffer words containing bytes representative of the image in its source position to be read out from the display buffer. These words are passed through the barrel shifter, where the word is rotated as necessary and stored in appropriate byte locations in the FIFO buffer. The FIFO buffer has the capability to write to two addresses simultaneously to obtain the desired rasult which is that the buffer locations match the destination display buffer word locations byte for byte and indeed, bit for bit.
When the source has been completely read or the FIFO buffer is full (whichever comes first) the display adapter automatically switches from reading to writing and stores the burst of data words it has in its FIFO
buffer into the display buffer at the destination locations. It should 12943&0 be noted that the processes described above cause the buffer to contain data in the format it is required for writing. That is each buffer word contains data in the correct alignment for writing unmodified into the corresponding display buffer words.
In any case where the source rectangle is too large to fit into the FIFO buffer the display adapter automatically switches back and forth between read bursts filling the FIFO buffer and write bursts dumping the FIFO buffer into the destination display buffer locations. The size of the X dimension of the image to the size of the FIFO buffer is irrele-vant to this process. A large X dimension will result in many bursts being required to move one line of the image. A small X dimension will result in many lines of the image being transferred in a single burst.
The buffer is therefore logically invisible.
In the example illustrated in Figure 2A and Fiyure 2~ the source image is read completely in a burst of two reads. (It will be under-stood that in a trivial case where the image is four by one pels in size, the hurst might only include one read). The control logic calcu-lates from the source and destination X addresses that a rotation of one to the right is required in order to get the pels into the positions within the destination word in which they will be required during the write burst. Also further logic calculates that pels occupying the last position within the word need to be written in the FIFO buffer one location ahead of pels in the first, second and third positions.
Although the bytes "b,a+2", "b,a+l", " b,a" lie in the same display buffer word at the source position for the image (41, Figure 2A), it can be seen that they the equivalent bytes "d,c+2", "d,c+l", " d,c" lie in different (adjacent) memory words at the destination position (43, Figure 23~.
In order to explain more fully the manner in which an image is moved on the display screen of a display system according to the present inventlon, reference will be made to the flow diagrams in Figures 4 and 5 and to Figures 2A and 2B.
1~9~3&0 Before the display adapter can actually modify the data in the display buffer in order to update the display screen, an initialisation phase is, however, necessary.
In the workstation of Figure 1, the processor initialises the display adapter by sending positioning data to the adapter over the data bus. The positioning data comprise image size information, information about the initial, or source position and the final, or destination position for that image and scan direction information. These data can result from operations using a mouse or instructions from a keyboard, and so on, and are supplied over the data bus to the control storage.
The source and destination position information comprises the "x"
and "y" values for the screen position of one corner of the image (eg.
the bottom right hand corner) in its source and destination positions.
The image size information defines the length of the horizontal and vertical sides of the image in terms of numbers of pels. The scan direction in~ormation determines the directlons in which the soUrce and destination image positions should be scanned from the indicated screen position in order to avoid corrupting data. If the image positions are scanned in the wrong directions when the image positions overlap it might be that a location could receive new pel data before the old pel data had been read out.
The size and position information in the case of the block in Figure 2 is as follows:
source position information .............. x = a+S, y = b;
destination position information ......... x = c+5, y = d;
size information ..... horizontal 6 pels, vertical 1 pel;
scan direction information ... y decreasing, x decreasing.
In order to co~pute the scan direction information, it is necessary to determine in which direction the pels of the image need to be pro-cessed (ie in which direction the image needs to be scanned) in order 12943~1) that data shall not be corrupted in the display buffer. Figures 2A and 2~ illustrate a case where the source and destination rectangles do not overlap, though in practice it is common for images in the source and destination positions to overlap when an image is copied within the on-screen portion of the display bu f f er. The aim is to avoid the need to write to a location which contains a byte of pel data which has not yet been read out of the display buffer. This can be done by comparing the source and destination positions of the image. The direction of scanning of the image in the x or Y direction, or both as appropriate, will be opposite to the direction of movement of the image. If, for example, destination position of the image is to the right of the source position (ie. the direction of movement is to the right), the scanning will be from right to left.
The source and destination position information mentioned above identifies the position the screen location from which the "scanning" of the rectangles should start. These values can be calculated from the image position information, the image size information and the scanning direction information.
In the example shown in Figure 2, as both the "x' and "y" values of the destination position are higher than those of the source position it is possible to compute that the image should be scanned from bottom right to top left. Also, if the positions of the source and destination images are defined by their top left hand corners (ie. b,a and d,c) at some stage during processing of the images, it is possible to compute the bottom right hand pel positions. In the present workstation these computations are performed by 50ftware under the control of the pro-cessor and not in the adapter. In an alternative embodiment of the invention it would be possible for special purpose combinatorial logic to be incorporated for this in the display adapter. In this case the initial Y and X values would first be read into the control storage and the computed values then passed via the dashed line shown in Figure 3 between the control storaae and the registers. In either case, an indication of the scanning direction is stored in the control storage 12~ L~ 380 U~9-87-008 14 and the initial Y and X positions for the source and destination images are stored in respective ones of the registers 48, 50, 52 and 54. The values stored in the registers for the example in Figures 2 are as follows:
Source Y register ...................... b;
Source X register .................... a+5;
Destination Y re~ister ............ ~.... d;
Destination X register ............... c+5.
Specific combinatorial logic is provided in the control logic for determining the number of bytes of rotation which needs to be performed by the barrel shifter in order to align the bytes of the source words within the destination words. The rotation required is calculated by subtracting the value of the source X position from the destination x position and truncating the result to the number of bits requixed to describe the number of pels in the word. This assumes, as is indeed the case, that there is a integral number of words per row on the display screen and that the number of pels per word is an integral binary power ~eg. 4 as in this case). In the present example the source address is "a~S" whilst the destination address is "c+5" and the number of bits required to describe the number of pels in one memory word is 2 (ie.
there are 4 bytes per word~. Thus the calculation is:
Rotation = (c - a) trunc 2.
As illustrated in Figure 2B, the rotation necessary is in fact one byte to the left. This rotation value is stored in the control storaqe and supplied to the barrel shifter.
Once this initialisation information has been determined and stored, the display adapter is then ready to start the operations on the display buffer. A11 the calculations described above are performed directly by combinatorial logic and do not therefore take time either in the microprocessor during setting up of the display adapter hardware or during operation of the display adapter hardware.
~294380 Figure 4 illustrates the logical flow of operations performed by read burst logic in the control logic and Figure 5 illustrates the logical flow of operations performed in write burst logic in the control logic during the modification of the display buffer contents. These flow diagrams are not intended to suggest that each step shown in the Figures relates to a separate machine state. Some steps involve a plurality of operations and others are in practice done in parallel by combinatorial logic. The aim in any implementation is to minimise the number of clock states.
IN STEP 80 the screen position value, b, for the y ordinate of the bottom right-most part of the image in its source location is loaded into the source Y counter 56 from the source Y register 48.
IN STEP 81 the screen position value, a+5, for the x ordinate of the bottom right-most part of the image in its source location is loaded into the source X counter 58 from the source X register 50.
IN STEP 82 the control logic tests whether the FIF0 buffer is full.
This is done by examining the control output from the FIF0 buffer addressing logic.
IN STEP 83 (ie. the FIF0 buffer is full) control is passed to the logic controlling a write burst as set out in Figure 5 and expanded later.
IN STEP 84 on returning form a write burst, or alternatively if the FIF0 buffer was not full, the control logic causes the arithmetic logic to compute the address of the word in the display buffer containing the byte of data for the pel to be displayed on the screen at position indicated by the values currently in the source Y and X counters. The actual computation to be performed will depend on the display buffer organisation, the number of pels per word and so on.
. ~2~3~
IN STEP 85 the contro] logic determines whether the word address just calculated is a new source word address. If the address just calculated is the same as the last word address calculated for the source image, control passes to step 87.
IN STEP 86 (ie. the address just calculated was new) the control logic then causes the display buffer word pointed to by the arithmetic logic to be read from the display buffer into the barrel shifter where it is rotated by the number of bytes determined to be necessary by the control logic. The barrel shifter is formed from combinatorial logic and consequently allows pels to be rotated from their position in the source word to their position in the destination w~rd without extra clock cycles.
The rotated word appears at the output of the barrel shifter and is read into appropriate byte locations in the FIFo buffer as addressed by the FIFO addressing logic under the control of the control logic. It will be remembered that the byte locations in the registers can be separately enabled whereby the FIF~ addressing logic can address appro-priate bytes in two adjacent registers at onCe. ~ny byte in a rotated word which was rotated aCross the word boundary in the barrel shifter is stored in the FIF0 buffer in an appropriate byte location in a register adjacent to the register in whiCh iS stored any byte in the rotated word Which which was not rotated across the word boundary in the barrel shifter. In the present example, the number of bytes per word is 4 and the rotation is one so only pels occupying byte 3 within the source word are rotated across the word boundary ~ie. bytes in the left-hand word position as shown in Figure 2B).
IN STEP 87, following on from step 86, or step 85 in the case the display buffer source word address was the same as the previously determined display buffer source word address, the control logic deter-mines from the horizontal length of the image rectangle (ie. the hori-zontal size) whether any more display buffer addresses calculations are to be performed for the cUrrent row of pels. This is done by maintaining ~:~94~}~0 UKg-87-~08 17 a count in the control logic of the number of pels processed in the current row.
If there are, the control logic decrements the source X counter as "x decrementing" was stored in the control storage. The control logic then returns to step 82.
If there are no more pels in the current row of the image, the logic proceeds to step 88.
IN STEP 88 the control logic determines from the vertical length of the image rectangle (ie. the vertical size) whether there are any more rows to be processed for the image. This is done by maintaining a count in the control logic of the number of rows processed for the current image.
If there are, the control logic decrements the source Y counter as "y decreasing" indication was stored in the control storage. The control logic then returns to step 81 and causes the position value, a+5, for the x ordinate to be loaded from the source x position register into the source X position counter.
IN STEP 89 the control logic passes control to the write burst logic as there are no more bytes of data relating to image pels in the source position in the display buffer. When control returns from the write burst logic, the image copying operation is complete and the control logic terminates its operation.
IN STEP 90 on entering a write burst, control~is either passed to step 91 on the first entry into a write burst during processing of an image, or to step 95 otherwise.
IN STEP 91 the screen position ~alue, d, for the y ordinate of the bottom right-most part of the image in its destination location is loaded into the destination Y counter 60 from the destination Y register 52.
~2~43t30 IN STEP 92 the screen position value, c+5, for the x ordinate of the bottom right-most part of the image in its destination location is loaded into the destination X counter 62 from the destination x register 54.
IN STEP 93 the control logic tests whether there is another FIFO
buffer word containing bytes to be written into a destination word location in the display buffer. This is done by examining the control output from the FIF0 buffer addressing logic.
IN STEP 94 tie. there are no more FIF0 buffer words to be read out) control is returned to either step 83 or 89 in the read burst logic from which control was passed to the write burst logic.
IN STEP 95 (ie. there are FIF0 buffer words to be written into the display buffer) the control logic causes the arithmetic logic to computes the address of the word in the display buffer containing the byte of data for the pel to be displayed on the screen at the position indicated by the values currently in the destination Y and X counters.
The actual computation to be performed will depend on the display buffer organisation, the number of pels per word and so on.
IN STEP 96 the control logic determines whether the address just calculated is a new display buffer address. If the address just calcu-lated is not new, control passes to step 9~.
IN STEP 97 (ie. the address just calculated was new) the control logic then causes the next FIF0 buffer word to be written to the display buffer word pointed to by the arithmetic 1O5ic. In practice only bytes in the word which form part of the image are written to the display buffer. The control logic only enables the locations in the destination word for bytes indicative of pels of the image to be written within the display buffer address pointed to by the arithmetic logic, in order to avoid corrupting bytes in the display buffer not forming part of the i~age. The control logic keeps track of which bytes are to be written by counting the bytes in the FIF0 buffer.
~Z9~3~0 IN STEP 98, following on from step 97, or step 96 in the case the display buffer destination word address was the same as the display buffer destination word address last calculated, the control logic then determines from the horizontal length of the image rectangle (ie. the horizontal size) whether any more display buffer destination word calculations are to be performed for the current row of pels. This is done by maintaining a count in the control logic of the number of pels processed in the current row.
If there are, the control logic decrements the destination X
counter as "x decreasing" was stored in the control storage. The control logic then returns to step 93.
If there are no more pels in the current row of the image, the logic proceeds to step 99.
IN STEP 99 the control logic decrements the destination Y counter as a "y decreasing" indication was stored in the control storage. The control logic then returns to step 92 and causes the X position value, c+5, for the x ordinate to be loaded from the destination x position register into the destination X position counter. It is not necessary to determine whether there are any more rows to be processed for the image as the FIFO buffer will be emptied of bytes before this can happen.
Although a particular embodiment of the invention as claimed has been described it will be appreciated numerous modifications and alter-native structures are possible within the scope of the invention as claimed.
For example the positions of the barrel shifter and the FI~0 buffer could be reversed so that the words of data indicative of the image in its source location are read straight into the FIFO buffer, and then the special addressing mechanism of the FIFO buffer used to co~pile data words which can be fed to the barrel shifter where they are rotated to form destination words and then stored in the destination locations in ~Z~34L3~5~
the display buffer. In such an embodiment o~ the display system the FIFO
buffer is connected to the data output of the display buffer for receiv-ing a source word read out of the display buffer. The input to the barrel shifter is connected to the output of the FIF0 buffer for receiv-ing a data word from the PIF0 buffer to be rotated by a selectable integral number of bytes and the output of the barrel shifter is connected to the data input of the display buffer. The control logic provides control signals to the barrel shifter and to the FIFO buffer addressing logic such that any byte of said data word which is to be rotated across the word boundary in the barrel shifter is read from an appropriate byte location in a register adjacent to the register from which is read any byte in said data word which is not to be rotated across the word boundary in the barrel shifter. In this way the set of destination words in which said bytes of data indicative of pels for the image are in destination order is formed by the rotated word at the output of the barrel shifter.
In the particularly described embodiment the area displayed on the screen is rectangular. If desired, however, the adapter could also be provided with the facility to copy images which are not rectangular by incorporating masking logic in the adapter. In simple terms this could be achieved in the workstation of Figure 1 by transferring mask boundary information from the workstation RAM to the off screen portion of the dicplay buffer and subsequently copying image data for a rectangular area as described in the preceding description. In this case however the control logic would cause the data items relating to screen positions outside the mask boundary to be disregarded so that only that part of the rectangular image area within the boundary would be displaced.
As an alternative to merely writing bytes of data into the display buffer, it may be desired to logically combine the byte indicative of a pel for the image with the byte already stored at the destination location in order to achieve a particular effect on the display screen.
This can be achieved by providing further arithmetic logi.c to allow arithmetic and logical operations to be performed between the source and destination locations. Each pel could effectively be processed separate-ly in such logic although several pels could in practice be be processed concurrently. The operation on each pel could be of the type:-Destination := Source (Operation) Destination where the operation could be an exclusive-or, a logical AND, and so on.
In addition, scissoring logic may be employed to protect areas of the display buffer from being written to (but not from being copied).
For example, areas outside a window on the display screen, or areas in off-screen storage can be protected in this way.
In the above, the display adapter shown in part in Figure 3 has been identified as a specific embodiment of a display system according to the invention, as rightly it is. However, the term display system as used in the claims is not limited thereto. The workstation including the display adapter could equally be described as a display system. conse-quently it should be understood that the term display system as used herein includes within its scope, a workstation, or indeed any other system falling within the scope of the claims, whether or not it is possible to separately identify a display adapter in that system. Also, although the logic in the specific embodiment of the invention is in the form of combinatorial hardware logic, the present invention includes within its scope that one or more of the functions provided by that logic is implemented in software.
Description The present invention relates to a display system comprising a display buffer for data indicative of picture elements with a facility for moving an image from one position to another by manipulating the data in the display buffer.
In order to move images ~eg. a character) around or onto a display screen a technique commonly called "bit blit" or "bit blt" has been developed. ~ssentially, the technique involves the provision of logic for automatically copying data indicative of the picture elements (pels) forming an image in response to commands teg. using a mouse) identifying the image in its original, or source, position and in its destination position. In conventional bit-blit implementations a memory location is read and the data thus obtained is then written to another memory location thus copyinq one pel of the image. By incrementing the source ~read) and destination twrite) addresses appropriately, and repeating the operation, images (eg text or graphical characters) of any size can be moved a pel at a time.
This process can be used, both for copying images from one position I to another in a part of a display buffer which is actually scanned in order to generate a screen of displayed images, (ie. in an on-screen portion of the display buffer) and for copying images between an off-screen (ie. non visible) and an on-screen portion of a display buffer.
This latter technique is used in all points addressable (APA) display buffers for copying symbol definitions which are held in an off-screen part of a display buffer into an on-screen part of the display buffer when the symbols are actually to be displayed.
Conventionally, this is done by the system microprocessor which may use string move instructions if it is provided with them. The rates of blit obtained are, however, relatively low because of the limited bus 3~
~K9-87-008 2 bandwidth of microprocessor system and the very large amounts of data involved with large displays. ~s a consequence of this, it is not normally possible to move the image (unless it is very simple) around the screen in real time in response, for example, to mouse movements.
Also a not in-considerable time is taken to move an image from off-screen to on-screen storage.
The object of the present invention is to provide a display system With a mechanism for copying an image from a source position to a destination position which does not suffer from the disadvantages of prior art mechanisms.
This object is met by a display system comprising a word organised display buffer for storing bytes of data indicative of picture elements ~pels) with a plurality of bytes of data stored in each buffer word, and means for copying an image from a source position to a destination position, said means for copying comprising means for reading one or more bursts of source words from a first set of word locations in the display buffer, the source words including bytes of data indicative of pels for the image in its source position, means for rearranging the bytes of data in a burst of read source words so as to form a set of destination words in which the bytes of data indicative of pels for the image are in destination order within the words and means for writing the destination words generated from each burst of read source words in a write burst to a second set of word locations in the display buffer such that the bytes of data indicative of the pels for the image are stored in the correct display buffer byte locations for representing the image in its destination position.
In a preferred embodiment of the invention the means for rearrang-ing the bytes of data in a burst of source words comprises a word-wide barrel shifter for rotating a data word by a selectable integral ~umber of bytes, a plurality of word-wide registers organised as a first-in-first-out ~FIFO) buffer for temporarily storing said bytes of data indicative of pels for the image, FIF0 buffer addressing logic such that lZ943~0 individual bytes within the registers can be addressed, and control logic for providing control signals to the barrel shifter and to the FIF0 buffer addressing logic such that the bytes of data in a burst of read source words are rearranged so as to form a set of destination words in which said bytes of data indicative of pels for the image are in destination order within the words.
In a first example the barrel shifter is connected to the data output of the display buffer for receiving a source word read out of the display buffer and for rotating the source word by a selectable integral number of bytes. The data input of the FIFO buffer is connected to the output o~ the barrel shifter for receiving a rotated word and the data output of the FIFO buffer is connected to the data input of the display buffer. The control logic provides control signals to the barrel shifter and to the FIFO buffer addressing logic such that any byte in a rotated word which was rotated across the word boundary in the barrel shifter is stored in the FIF0 buffer in an appropriate byte location in a register adjacent to the reqister in which is stored any byte in the rotated word which which was not rotated across the word boundary in the barrel shifter, whereby the set of destination words in which said bytes of data indicative of pels for the image are stored in destination order within the words is stored in the FIFO buffer.
In an alternative example the FIFO buffer is connected instead to the data output of the display buffer for receiving a source word read out of the display buffer. The input to the barrel shifter is connected to the output of the FIF0 buffer for receiving a data word from the PIPO
buffer to be rotated by a selectable integral number of bytes and the output of the barrel shifter is connected to the data input of the display buffer. The control logic provides control signals to the barrel shifter and to the FIF0 buffer addressing logic such that any byte of said data word which is to be rotated across the word boundary in the barrel shifter is read from an appropriate byte location in a register adjacent to the register from which is read any byte in said data word which is not to be rotated across the word boundary in the barrel 3-29438~
shifter, whereby the set of destination words in which said bytes of data indicative of pels for the image are in destination order is formed by the rotated word at the output of the barrel shifter.
In the embodiments of the invention mentioned above, the means for reading one or more bursts of source words and the means for writing the destination words comprise means for generating a first set of display buffer addresses from which to read the source words and a set of display buffer addresses to which to write the destination words. The control logic causes the display buffer address generating means to generate a sequence of addresses from said first set, for a burst of source words to be read, until the FIFO buffer is full or until the words in which bytes of data inaicative of pels for the image in the source position are exhausted, which ever occurs first, and then cause the display buffer address generating means to generate a sequence of addresses from said second set forming a burst of write addresses until FIFO buffer is emptied of bytes of data indicative of the image. In addition~ the control logic can synchronise the addressing of the display buffer and the operation of the means for rearranging the bytes of data in a burst of read source words such that, after an appropriate number of bursts of source words have been read, rearranged and stored in the destination locations in the display buffer, the image is copied from the source position to the destination position.
A display system as above may include a display buffer which comprises an on-screen portion for storing bytes of data indicative of pels to be displayed on a display screen and an off-screen portion for bytes of data indicative of pels which are not displayed on a display screen. In this case the means for copying an image from a source position to a destination position will enable enable an image to be copied within one of the on-screen or off-screen portions and to be copied between said portions in either direction.
With a display system in accordance with the present invention alpha numericS, teXt and even graphics images can be moved around a 1~94380 display sereen in real t-'me (eg in response to mouse movements) which ean faeilitate the editing of screens containing images of all types (eg for page composition in desk-top publishing). It is possible to rapidly eopy images from an off-screen portion to an on-screen portion of an all points addressable (APA) display buffer in order to display symbols (eg.
charaeters) whose pel definitions are held in the off-screen portion. In this way a sereen of images, ineluding alpha numeries, text and even graphies, ean be ereated on a graphies display which is driven using an APA graphies display buffer with the performanee normally assoeiated with eoded buffer alphanumerics only displays.
In order to enable a more complete understanding of the present invention, there follows a particular description of a specific embodi-ment of a display system in aeeordanee with the present invention with referenee to the aeeompanying drawings in whieh:
Figure 1 is a bloek diagram of a workstation;
Figures 2A and 2B are sehematie diagrams illustrating, respective-ly, the relationship between pereeived pieture element (pel) positions on a display sereen and the eorresponding storage positions in a display buffer for data indieative of those pels;
Figure 3 is a sehematie biock diagram showing aspects of a display adapter ineluded in Figure l; and Figures 4 and 5 form a flow diagram illustrating aspects of the operation of the display adapter of Figure 3.
Figure 1 shows an overview of a workstation ineluding a display adapter in which the invention may be implemented. The workstation eomprises a number of different system units connected via a sy5tem bus 12. The system bus comprises a data bus 14, an address bus 16 and a control bus 18. Connected to the system bus is a microprocessor 10, random access memory 20, a keyboard adapter 28, a display adapter 32, an 1~:94380 I/0 adapter 22 and a communications adapter 26. The keyboard adapter isused to connect a keyboard 30 to the system bus. The display adapter, which forms a specific embodiment of the present invention, connects the system bus to a display device 34. The I/0 adapter likewise provides a connection between other input/output devices 24 (eg. DASDs) and the system bus, and the communications adapter allows the workstation to be connected to and to communicate with an external processor or processors such as a host processor (not shown).
The display adapter includes an all points addressable (APA) display buffer 36 which can be accessed by the display device in order to fetch the data corresponding to the individual picture elements on the screen (see Figure 2A). The data are fetched in synchronism with the scanning of the display screen. To facilitate this the information in the display buffer is organised in accordance with the scanning sequence of the display refresh circuitry. In addition to the on-screen, or visible portion of the display screen which is scanned by the display device, the display buffer also comprises an off-screen, or non-visible portion in which are stored images (eg. character or symbol definitions) which are not visible on the screen.
Figure 2A illustrates the display screen 38 as perceived. The screen has "Y" lines of "X" pel positions each. As shown the rows of the screen are numbered from 0 to Yl starting from the top and moving down the screen. The pel positions in each row are likewise shown numbered, from left to right, 0 to Xl. It will be appreciated that the numbering is purely an arbitrary choice and that other numbering schemes could have been chosen.
In order to generate the screen shown in Figure 2A, data is stored in a display buffer 36, the on-screen portion of which is represented in Figure 2B.
This specific display buffer is organised on words of 32 bits. Each pel is represented by an 8-bit byte of data defining the intensity . 1~94~80 and/or colour of the pel. It will be understood however, that other display buffer organisations are possible. For example, the buffer could be organised on words of another length and/or a different number of bits could make up a byte defining the intensity and/or colour of a pel (eg. 8 bit words and 4 bit bytes).
It will be noted that the display buffer is shown, for reasons of simplicity of explanation, as being organised from the bottom up as a linear stream of bytes within the buffer starting with the byte for the top left-most pel, followed by the bytes for the pels, from left to right, in the first row, the second row, and so on until the byte for the bottom right-~ost pel. The display buffer could be organised for a screen which i9 refreshed using an interleaved scanning technique (i.e.
where the scanning of even numbered rows alternates with the scanning of odd numbered rows) by arranging for the image data for the individual pels of the display screen shown in Figure 2A to be stored with the data relating to the even numbered rows stored in a first sequence from a first address in the display buffer and the data relating to the odd numbered rows stored in a second sequence starting at a second address at or after the end of the first sequence. Alternatively, the display buffer could be organised as a single sequence as shown in Figure 2B and the display scanning logic provided with the capability to extract the data it needs from the buffer in order to support an interleaved scanned .
display screen.
Figure 2A shows two rectangular blocks 40 and 42 which represent the source position 40 and the destination position 42 on the screen for a rectangular image to be moved. The rectangular image comprises a row of 6 pels, the top-left of which is initially located at the screen position b,a. The top-left of the destination position is d,c. Figure 2B
illustrates the source rectangle to be represented in the display buffer by a set of 6 bytes of data at 41. Likewise the destination rectangle is represented in the display buffer by a set of 6 bytes of data at 43. It will be noted that the alignment of the sets of data for the source and destination rectangles with respect to the word boundaries of the 1~43~0 display buffer tie. the left/right edges of the block at bit address 0/31 shown in Figure 2B) is different. It should be noted that a simple image lying on one row only of pels has been illustrated for reasons of ease of explanation. In practice the images to be moved will normally be larger and will normally cover a plurality of rows.
The display buffer in this adapter is formed from a 32 bit wide array of D-RAMS. The minimum addressing unit is one 32 bit word. The display buffer is, however provided with separate byte enables so that 0 to 4 bytes (each of 8 bits) may be written to as required for each write access with the remaining of the four bytes remaining unchanged. In this way the display buffer can be configured as an APA buffer so that each pel (ie. each 8-bit byte) can be selectively written to or not as the case may be even though four bytes (ie. a word) at a time are (is) addressed.
In view of this it would be possible to apply the prior art app-roach to moving an image on a display screen (ie. to successively read single bytes and each time to write the data thus obtained to the equivalent destination location in the buffer, thereby copying succes-sively sinqle pels until the whole image has been copied). This approach is, however, very slow because each byte is processed in turn. It would not be possible to simply read and write a word at a time because the position of a byte within the word boundaries may be different in the source and destination words as illustrated in ~igure 2B.
The present invention provides a solution to this problem by providing means for reading, processing and storing bursts of display buffer words.
Although, in the specific embodiment of the invention described herein the display buffer is implemented in D-RAMS and can be accessed on both word and byte boundaries, the present invention is not limited to such an organisation. It can equally be implemented with a display buffer in some other technology and where the buffer can only be accessed on the word boundaries and not on the byte boundaries.
~2943~
If the display buffer is implemented in D-PAMS, however, and if consecutive words in the display buffer are arranged to define consecu-tive sets of four pels, the burst operation of the present invention allows, for example, a D-RAM "page mode" feature to be utilised which provides a further significant performance advantage. "Page mode" is a feature conventionally provided in D-RAMS which, as a consequence of their internal chip organisation, allows faster access to sequential locations than to random locations.
Figure 3 is a schematic block diagram showing the interrelationship between various functional elements in the display adapter shown in Figure 1 which forms the specific embodiment of the present invention.
The adapter comprises a control unit 44 which is connected to the address bus 16 and to the control bus 18. Associated with the control unit is control storage 46 which is connected to the data bus 14 for the receipt of initialisation data from the workstation RAM.
The inputs to Y and x source registers 48 and 50 and Y and X
destination registers 52 and 54 are also connected to the data ~us 14 for receiving initial position data as part of the initialisation data to be explained later. Connected to the outputs of the Y and X source and the Y and X destination registers are Y and X source and Y and X
destination counters 56, 58, 60, 62, respectively. An arithmetic logic unit 64 has four inputs each connected to the output of a respective one of the four counters 56, 58, 60, 62. The oUtput of the arithmetic unit is connected to the address input of the display buffer 38.
The data outpUts of the display buffer 36 are connected in parallel to the inputs Of a barrel shifter 66 known per se, and whose purpose is to rotate a data word input thereto by an integral number of byte positions. The data outputs of the barrel shifter are connected in parallel to the data inputs of a FIF0 ~uffer 68 which is formed from a plurality tin this display adapter, eight) word-wide registers. The FIFO
buffer is provided with addressing logic 70 such that individual bytes in the FIFO buffer may be separately addressed and such that individual 129~3~30 ~K9-87~008 10 bytes presented simultaneously on the data inputs to the FIFO buffer may be stored in different words. The FIE'O buffer addressing logic contains byte pointers for indicating the start and finish of data in the FIFO
buffer, whereby the FIFO buffer addressing logic can determine when the buffer is full, and when it is empty. The data outputs of the FIFO
buffer are connected back to the data inputs to the display buffer.
Although shown as being separate, the data inputs and outputs of the display buffer may in fact be common - likewise for the FIFO buffer.
The control unit is connected via control inputs C to the control storage, the Y and X registers, the Y and x counters, the arithmetic logic unit the display buffer, the barrel shifter and the FIFO buffer address logic. The FIFO buffer address logic is also connected to the control logic for passing "buffer full" and "buffer empty" signals.
In this particular display adapter the various functional units shown are provided in the form of a special purpose circuitry. The logic units for example are provided by combinatorial logic. The present invention does not however, exclude the possibility of imple-menting the logic in a software-and-processor-based system.
An image to be copied is processed by the display adapter in bursts. The control logic first causes a burst of display buffer words containing bytes representative of the image in its source position to be read out from the display buffer. These words are passed through the barrel shifter, where the word is rotated as necessary and stored in appropriate byte locations in the FIFO buffer. The FIFO buffer has the capability to write to two addresses simultaneously to obtain the desired rasult which is that the buffer locations match the destination display buffer word locations byte for byte and indeed, bit for bit.
When the source has been completely read or the FIFO buffer is full (whichever comes first) the display adapter automatically switches from reading to writing and stores the burst of data words it has in its FIFO
buffer into the display buffer at the destination locations. It should 12943&0 be noted that the processes described above cause the buffer to contain data in the format it is required for writing. That is each buffer word contains data in the correct alignment for writing unmodified into the corresponding display buffer words.
In any case where the source rectangle is too large to fit into the FIFO buffer the display adapter automatically switches back and forth between read bursts filling the FIFO buffer and write bursts dumping the FIFO buffer into the destination display buffer locations. The size of the X dimension of the image to the size of the FIFO buffer is irrele-vant to this process. A large X dimension will result in many bursts being required to move one line of the image. A small X dimension will result in many lines of the image being transferred in a single burst.
The buffer is therefore logically invisible.
In the example illustrated in Figure 2A and Fiyure 2~ the source image is read completely in a burst of two reads. (It will be under-stood that in a trivial case where the image is four by one pels in size, the hurst might only include one read). The control logic calcu-lates from the source and destination X addresses that a rotation of one to the right is required in order to get the pels into the positions within the destination word in which they will be required during the write burst. Also further logic calculates that pels occupying the last position within the word need to be written in the FIFO buffer one location ahead of pels in the first, second and third positions.
Although the bytes "b,a+2", "b,a+l", " b,a" lie in the same display buffer word at the source position for the image (41, Figure 2A), it can be seen that they the equivalent bytes "d,c+2", "d,c+l", " d,c" lie in different (adjacent) memory words at the destination position (43, Figure 23~.
In order to explain more fully the manner in which an image is moved on the display screen of a display system according to the present inventlon, reference will be made to the flow diagrams in Figures 4 and 5 and to Figures 2A and 2B.
1~9~3&0 Before the display adapter can actually modify the data in the display buffer in order to update the display screen, an initialisation phase is, however, necessary.
In the workstation of Figure 1, the processor initialises the display adapter by sending positioning data to the adapter over the data bus. The positioning data comprise image size information, information about the initial, or source position and the final, or destination position for that image and scan direction information. These data can result from operations using a mouse or instructions from a keyboard, and so on, and are supplied over the data bus to the control storage.
The source and destination position information comprises the "x"
and "y" values for the screen position of one corner of the image (eg.
the bottom right hand corner) in its source and destination positions.
The image size information defines the length of the horizontal and vertical sides of the image in terms of numbers of pels. The scan direction in~ormation determines the directlons in which the soUrce and destination image positions should be scanned from the indicated screen position in order to avoid corrupting data. If the image positions are scanned in the wrong directions when the image positions overlap it might be that a location could receive new pel data before the old pel data had been read out.
The size and position information in the case of the block in Figure 2 is as follows:
source position information .............. x = a+S, y = b;
destination position information ......... x = c+5, y = d;
size information ..... horizontal 6 pels, vertical 1 pel;
scan direction information ... y decreasing, x decreasing.
In order to co~pute the scan direction information, it is necessary to determine in which direction the pels of the image need to be pro-cessed (ie in which direction the image needs to be scanned) in order 12943~1) that data shall not be corrupted in the display buffer. Figures 2A and 2~ illustrate a case where the source and destination rectangles do not overlap, though in practice it is common for images in the source and destination positions to overlap when an image is copied within the on-screen portion of the display bu f f er. The aim is to avoid the need to write to a location which contains a byte of pel data which has not yet been read out of the display buffer. This can be done by comparing the source and destination positions of the image. The direction of scanning of the image in the x or Y direction, or both as appropriate, will be opposite to the direction of movement of the image. If, for example, destination position of the image is to the right of the source position (ie. the direction of movement is to the right), the scanning will be from right to left.
The source and destination position information mentioned above identifies the position the screen location from which the "scanning" of the rectangles should start. These values can be calculated from the image position information, the image size information and the scanning direction information.
In the example shown in Figure 2, as both the "x' and "y" values of the destination position are higher than those of the source position it is possible to compute that the image should be scanned from bottom right to top left. Also, if the positions of the source and destination images are defined by their top left hand corners (ie. b,a and d,c) at some stage during processing of the images, it is possible to compute the bottom right hand pel positions. In the present workstation these computations are performed by 50ftware under the control of the pro-cessor and not in the adapter. In an alternative embodiment of the invention it would be possible for special purpose combinatorial logic to be incorporated for this in the display adapter. In this case the initial Y and X values would first be read into the control storage and the computed values then passed via the dashed line shown in Figure 3 between the control storaae and the registers. In either case, an indication of the scanning direction is stored in the control storage 12~ L~ 380 U~9-87-008 14 and the initial Y and X positions for the source and destination images are stored in respective ones of the registers 48, 50, 52 and 54. The values stored in the registers for the example in Figures 2 are as follows:
Source Y register ...................... b;
Source X register .................... a+5;
Destination Y re~ister ............ ~.... d;
Destination X register ............... c+5.
Specific combinatorial logic is provided in the control logic for determining the number of bytes of rotation which needs to be performed by the barrel shifter in order to align the bytes of the source words within the destination words. The rotation required is calculated by subtracting the value of the source X position from the destination x position and truncating the result to the number of bits requixed to describe the number of pels in the word. This assumes, as is indeed the case, that there is a integral number of words per row on the display screen and that the number of pels per word is an integral binary power ~eg. 4 as in this case). In the present example the source address is "a~S" whilst the destination address is "c+5" and the number of bits required to describe the number of pels in one memory word is 2 (ie.
there are 4 bytes per word~. Thus the calculation is:
Rotation = (c - a) trunc 2.
As illustrated in Figure 2B, the rotation necessary is in fact one byte to the left. This rotation value is stored in the control storaqe and supplied to the barrel shifter.
Once this initialisation information has been determined and stored, the display adapter is then ready to start the operations on the display buffer. A11 the calculations described above are performed directly by combinatorial logic and do not therefore take time either in the microprocessor during setting up of the display adapter hardware or during operation of the display adapter hardware.
~294380 Figure 4 illustrates the logical flow of operations performed by read burst logic in the control logic and Figure 5 illustrates the logical flow of operations performed in write burst logic in the control logic during the modification of the display buffer contents. These flow diagrams are not intended to suggest that each step shown in the Figures relates to a separate machine state. Some steps involve a plurality of operations and others are in practice done in parallel by combinatorial logic. The aim in any implementation is to minimise the number of clock states.
IN STEP 80 the screen position value, b, for the y ordinate of the bottom right-most part of the image in its source location is loaded into the source Y counter 56 from the source Y register 48.
IN STEP 81 the screen position value, a+5, for the x ordinate of the bottom right-most part of the image in its source location is loaded into the source X counter 58 from the source X register 50.
IN STEP 82 the control logic tests whether the FIF0 buffer is full.
This is done by examining the control output from the FIF0 buffer addressing logic.
IN STEP 83 (ie. the FIF0 buffer is full) control is passed to the logic controlling a write burst as set out in Figure 5 and expanded later.
IN STEP 84 on returning form a write burst, or alternatively if the FIF0 buffer was not full, the control logic causes the arithmetic logic to compute the address of the word in the display buffer containing the byte of data for the pel to be displayed on the screen at position indicated by the values currently in the source Y and X counters. The actual computation to be performed will depend on the display buffer organisation, the number of pels per word and so on.
. ~2~3~
IN STEP 85 the contro] logic determines whether the word address just calculated is a new source word address. If the address just calculated is the same as the last word address calculated for the source image, control passes to step 87.
IN STEP 86 (ie. the address just calculated was new) the control logic then causes the display buffer word pointed to by the arithmetic logic to be read from the display buffer into the barrel shifter where it is rotated by the number of bytes determined to be necessary by the control logic. The barrel shifter is formed from combinatorial logic and consequently allows pels to be rotated from their position in the source word to their position in the destination w~rd without extra clock cycles.
The rotated word appears at the output of the barrel shifter and is read into appropriate byte locations in the FIFo buffer as addressed by the FIFO addressing logic under the control of the control logic. It will be remembered that the byte locations in the registers can be separately enabled whereby the FIF~ addressing logic can address appro-priate bytes in two adjacent registers at onCe. ~ny byte in a rotated word which was rotated aCross the word boundary in the barrel shifter is stored in the FIF0 buffer in an appropriate byte location in a register adjacent to the register in whiCh iS stored any byte in the rotated word Which which was not rotated across the word boundary in the barrel shifter. In the present example, the number of bytes per word is 4 and the rotation is one so only pels occupying byte 3 within the source word are rotated across the word boundary ~ie. bytes in the left-hand word position as shown in Figure 2B).
IN STEP 87, following on from step 86, or step 85 in the case the display buffer source word address was the same as the previously determined display buffer source word address, the control logic deter-mines from the horizontal length of the image rectangle (ie. the hori-zontal size) whether any more display buffer addresses calculations are to be performed for the cUrrent row of pels. This is done by maintaining ~:~94~}~0 UKg-87-~08 17 a count in the control logic of the number of pels processed in the current row.
If there are, the control logic decrements the source X counter as "x decrementing" was stored in the control storage. The control logic then returns to step 82.
If there are no more pels in the current row of the image, the logic proceeds to step 88.
IN STEP 88 the control logic determines from the vertical length of the image rectangle (ie. the vertical size) whether there are any more rows to be processed for the image. This is done by maintaining a count in the control logic of the number of rows processed for the current image.
If there are, the control logic decrements the source Y counter as "y decreasing" indication was stored in the control storage. The control logic then returns to step 81 and causes the position value, a+5, for the x ordinate to be loaded from the source x position register into the source X position counter.
IN STEP 89 the control logic passes control to the write burst logic as there are no more bytes of data relating to image pels in the source position in the display buffer. When control returns from the write burst logic, the image copying operation is complete and the control logic terminates its operation.
IN STEP 90 on entering a write burst, control~is either passed to step 91 on the first entry into a write burst during processing of an image, or to step 95 otherwise.
IN STEP 91 the screen position ~alue, d, for the y ordinate of the bottom right-most part of the image in its destination location is loaded into the destination Y counter 60 from the destination Y register 52.
~2~43t30 IN STEP 92 the screen position value, c+5, for the x ordinate of the bottom right-most part of the image in its destination location is loaded into the destination X counter 62 from the destination x register 54.
IN STEP 93 the control logic tests whether there is another FIFO
buffer word containing bytes to be written into a destination word location in the display buffer. This is done by examining the control output from the FIF0 buffer addressing logic.
IN STEP 94 tie. there are no more FIF0 buffer words to be read out) control is returned to either step 83 or 89 in the read burst logic from which control was passed to the write burst logic.
IN STEP 95 (ie. there are FIF0 buffer words to be written into the display buffer) the control logic causes the arithmetic logic to computes the address of the word in the display buffer containing the byte of data for the pel to be displayed on the screen at the position indicated by the values currently in the destination Y and X counters.
The actual computation to be performed will depend on the display buffer organisation, the number of pels per word and so on.
IN STEP 96 the control logic determines whether the address just calculated is a new display buffer address. If the address just calcu-lated is not new, control passes to step 9~.
IN STEP 97 (ie. the address just calculated was new) the control logic then causes the next FIF0 buffer word to be written to the display buffer word pointed to by the arithmetic 1O5ic. In practice only bytes in the word which form part of the image are written to the display buffer. The control logic only enables the locations in the destination word for bytes indicative of pels of the image to be written within the display buffer address pointed to by the arithmetic logic, in order to avoid corrupting bytes in the display buffer not forming part of the i~age. The control logic keeps track of which bytes are to be written by counting the bytes in the FIF0 buffer.
~Z9~3~0 IN STEP 98, following on from step 97, or step 96 in the case the display buffer destination word address was the same as the display buffer destination word address last calculated, the control logic then determines from the horizontal length of the image rectangle (ie. the horizontal size) whether any more display buffer destination word calculations are to be performed for the current row of pels. This is done by maintaining a count in the control logic of the number of pels processed in the current row.
If there are, the control logic decrements the destination X
counter as "x decreasing" was stored in the control storage. The control logic then returns to step 93.
If there are no more pels in the current row of the image, the logic proceeds to step 99.
IN STEP 99 the control logic decrements the destination Y counter as a "y decreasing" indication was stored in the control storage. The control logic then returns to step 92 and causes the X position value, c+5, for the x ordinate to be loaded from the destination x position register into the destination X position counter. It is not necessary to determine whether there are any more rows to be processed for the image as the FIFO buffer will be emptied of bytes before this can happen.
Although a particular embodiment of the invention as claimed has been described it will be appreciated numerous modifications and alter-native structures are possible within the scope of the invention as claimed.
For example the positions of the barrel shifter and the FI~0 buffer could be reversed so that the words of data indicative of the image in its source location are read straight into the FIFO buffer, and then the special addressing mechanism of the FIFO buffer used to co~pile data words which can be fed to the barrel shifter where they are rotated to form destination words and then stored in the destination locations in ~Z~34L3~5~
the display buffer. In such an embodiment o~ the display system the FIFO
buffer is connected to the data output of the display buffer for receiv-ing a source word read out of the display buffer. The input to the barrel shifter is connected to the output of the FIF0 buffer for receiv-ing a data word from the PIF0 buffer to be rotated by a selectable integral number of bytes and the output of the barrel shifter is connected to the data input of the display buffer. The control logic provides control signals to the barrel shifter and to the FIFO buffer addressing logic such that any byte of said data word which is to be rotated across the word boundary in the barrel shifter is read from an appropriate byte location in a register adjacent to the register from which is read any byte in said data word which is not to be rotated across the word boundary in the barrel shifter. In this way the set of destination words in which said bytes of data indicative of pels for the image are in destination order is formed by the rotated word at the output of the barrel shifter.
In the particularly described embodiment the area displayed on the screen is rectangular. If desired, however, the adapter could also be provided with the facility to copy images which are not rectangular by incorporating masking logic in the adapter. In simple terms this could be achieved in the workstation of Figure 1 by transferring mask boundary information from the workstation RAM to the off screen portion of the dicplay buffer and subsequently copying image data for a rectangular area as described in the preceding description. In this case however the control logic would cause the data items relating to screen positions outside the mask boundary to be disregarded so that only that part of the rectangular image area within the boundary would be displaced.
As an alternative to merely writing bytes of data into the display buffer, it may be desired to logically combine the byte indicative of a pel for the image with the byte already stored at the destination location in order to achieve a particular effect on the display screen.
This can be achieved by providing further arithmetic logi.c to allow arithmetic and logical operations to be performed between the source and destination locations. Each pel could effectively be processed separate-ly in such logic although several pels could in practice be be processed concurrently. The operation on each pel could be of the type:-Destination := Source (Operation) Destination where the operation could be an exclusive-or, a logical AND, and so on.
In addition, scissoring logic may be employed to protect areas of the display buffer from being written to (but not from being copied).
For example, areas outside a window on the display screen, or areas in off-screen storage can be protected in this way.
In the above, the display adapter shown in part in Figure 3 has been identified as a specific embodiment of a display system according to the invention, as rightly it is. However, the term display system as used in the claims is not limited thereto. The workstation including the display adapter could equally be described as a display system. conse-quently it should be understood that the term display system as used herein includes within its scope, a workstation, or indeed any other system falling within the scope of the claims, whether or not it is possible to separately identify a display adapter in that system. Also, although the logic in the specific embodiment of the invention is in the form of combinatorial hardware logic, the present invention includes within its scope that one or more of the functions provided by that logic is implemented in software.
Claims (8)
1. A display system comprising a word organised display buffer for storing bytes of data indicative of picture elements (pels) with a plurality of bytes of data stored in each display buffer word, and means for copying an image from a source position to a destination position, said means for copying comprising means for reading one or more bursts of source words from a first set of word locations in the display buffer, the source words including bytes of data indicative of pels for the image in its source position, means for rearranging the bytes of data in a burst of read source words so as to form a set of destination words in which said bytes of data indicative of pels for the image are in destination order within the words and means for writing the destina-tion words generated from each burst of read source words in a write burst to a second set of word locations in the display buffer whereby the bytes of data indicative of the pels for the image are stored in the correct display buffer byte locations for representing the image in its destination position.
2. A display system as claimed in claim 1 in which the means for rearranging the bytes of data in a burst of source words comprises a word-wide barrel shifter for rotating a data word by a selectable integral number of bytes, a plurality of word-wide registers organised as a first-in-first-out (FIFO) buffer for temporarily storing said bytes of data indicative of pels for the image, FIFO buffer addressing logic such that individual bytes within the registers can be addressed, and control logic for providing control signals to the barrel shifter and to the FIFO buffer addressing logic such that the bytes of data in a burst of read source words are rearranged so as to form a set of destination words in which said bytes of data indicative of pels for the image are in destination order within the words.
3. A display system as claimed in claim 2 in which the barrel shifter is connected to the data output of the display buffer for receiving a source word read out of the display buffer and for rotating the source word by a selectable integral number of bytes, in which the data input of the FIFO buffer is connected to the output of the barrel shifter for receiving a rotated word and the data output of the FIFO buffer is connected to the data input of the display buffer, and in which the control logic provides control signals to the barrel shifter and to the FIFO buffer addressing logic such that any byte in a rotated word which was rotated across the word boundary in the barrel shifter is stored in the FIFO buffer in an appropriate byte location in a register adjacent to the register in which is stored any byte in the rotated word which was not rotated across the word boundary in the barrel shifter, whereby the set of destination words in which said bytes of data indicative of pels for the image are stored in destination order within the words is stored in the FIFO buffer.
4. A display system as claimed in claim 2 in which the FIFO buffer is connected to the data output of the display buffer for receiving a source word read out of the display buffer, in which the input to the barrel shifter is connected to the output of the FIFO buffer for receiving a data word from the FIFO buffer to be rotated by a selectable integral number of bytes and the output of the barrel shifter is connected to the data input of the display buffer and in which the control logic provides control signals to the barrel shifter and to the FIFO buffer addressing logic such that any byte of said data word which is to be rotated across the word boundary in the barrel shifter, is read from an appropriate byte location in a register adjacent to the register from which is read any byte in said data word which is not to be rotated across the word boundary in the barrel shifter,whereby the set of destination words in which said bytes of data indicative of pels for the image are in destination order is formed by the rotated word at the output of the barrel shifter.
5. A display system as claimed in claim 3 wherein said means for copying comprises means for generating a first set of display buffer addresses from which to read the source words and a set of display buffer addresses to which to write the destination words, and wherein the control logic causes the display buffer address generating means to generate a sequence of addresses from said first set, for a burst of source words to be read, until the FIFO buffer is full or until the words in which bytes of data indicative of pels for the image in the source location are exhausted, which ever occurs first, and then causes the display buffer address generating means to generate a sequence of addresses from said second set forming a burst of write addresses until FIFO buffer is emptied of bytes of data indicative of the image, the control logic synchronising the addressing of the display buffer and the operation of the means for rearranging the bytes of data in a burst of read source words such that, after one or more bursts of source words have been read, rearranged and stored in the destination locations in the display buffer, the image is copied from the source position to the destination position.
6. A display system as claimed in claim 4 wherein said means for copying comprises means for generating a first set of display buffer addresses from which to read the source words and a set of display buffer addresses to which to write the destination words, and wherein the control logic causes the display buffer address generating means to generate a sequence of addresses from said first set, for a burst of source words to be read, until the FIFO buffer is full or until the words in which bytes of data indicative of pels for the image in the source location are exhausted, which ever occurs first, and then causes the display buffer address generating means to generate a sequence of addresses from said second set forming a burst of write addresses until FIFO buffer is emptied of bytes of data indicative of the image, the control logic synchronising the addressing of the display buffer and the operation of the means for rearranging the bytes of data in a burst of read Source words such that, after one or more bursts of source words have been read, rearranged and stored in the destination locations in the display buffer, the image is copied from the source position to the destination position.
7. A display system as claimed in any one of claims 1, 2 or 3 wherein the display buffer comprises an on-screen portion for storing bytes of data indicative of pels to be displayed on a display screen and an off-screen portion for bytes of data indicative of pels which are not displayed on a display screen and wherein the means for copying an image from a source position to a destination position enable an image to be copied within one of the on-screen or off-screen portions and to be copied between said portions in either direction.
8. A display system as claimed in any one of claims 4, 5 or 6 wherein the display buffer comprises an on-screen portion for storing bytes of data indicative of pels to be displayed on a display screen and an off-screen portion for bytes of data indicative of pels which are not displayed on a display screen and wherein the means for copying an image from a source position to a destination position enable an image to be copied within one of the on-screen or off-screen portions and to be copied between said portions in either direction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8707851A GB2203317B (en) | 1987-04-02 | 1987-04-02 | Display system |
| US8707851 | 1987-04-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1294380C true CA1294380C (en) | 1992-01-14 |
Family
ID=10615089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000563038A Expired - Lifetime CA1294380C (en) | 1987-04-02 | 1988-03-31 | Display system |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0284905B1 (en) |
| JP (1) | JPS63251864A (en) |
| CA (1) | CA1294380C (en) |
| DE (1) | DE3885926T2 (en) |
| GB (1) | GB2203317B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69033158T2 (en) * | 1989-07-28 | 1999-10-14 | Hewlett-Packard Co. | Method and device for accelerating picture windows in graphic systems |
| EP0679313A1 (en) * | 1993-11-16 | 1995-11-02 | International Business Machines Corporation | Method and apparatus for alignment of images for template elimination |
| DE4405330A1 (en) * | 1994-02-21 | 1995-08-24 | Vobis Microcomputer Ag | Method for scrolling multiple raster lines in a window of a graphics mode operated screen of a personal computer |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2123656B (en) * | 1982-06-09 | 1987-02-18 | Tatsumi Denshi Kogyo Kk | A method and an apparatus for displaying a unified picture on crt screens of multiple displaying devices |
| JPH06100911B2 (en) * | 1983-12-26 | 1994-12-12 | 株式会社日立製作所 | Image data processing apparatus and method |
| EP0158314B1 (en) * | 1984-04-10 | 1993-07-21 | Ascii Corporation | Video display control system |
| JPS60245062A (en) * | 1984-05-18 | 1985-12-04 | Matsushita Electric Ind Co Ltd | Data transfer device |
| JPS61124984A (en) * | 1984-11-22 | 1986-06-12 | 松下電器産業株式会社 | Data transfer apparatus |
| EP0192139A3 (en) * | 1985-02-19 | 1990-04-25 | Tektronix, Inc. | Frame buffer memory controller |
-
1987
- 1987-04-02 GB GB8707851A patent/GB2203317B/en not_active Expired - Lifetime
-
1988
- 1988-03-01 JP JP4598888A patent/JPS63251864A/en active Pending
- 1988-03-17 EP EP19880104228 patent/EP0284905B1/en not_active Expired - Lifetime
- 1988-03-17 DE DE19883885926 patent/DE3885926T2/en not_active Expired - Fee Related
- 1988-03-31 CA CA000563038A patent/CA1294380C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0284905A2 (en) | 1988-10-05 |
| GB2203317A (en) | 1988-10-12 |
| DE3885926T2 (en) | 1994-05-19 |
| EP0284905A3 (en) | 1990-09-19 |
| GB8707851D0 (en) | 1987-05-07 |
| EP0284905B1 (en) | 1993-12-01 |
| DE3885926D1 (en) | 1994-01-13 |
| JPS63251864A (en) | 1988-10-19 |
| GB2203317B (en) | 1991-04-03 |
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