CA1254683A - On-line verification of video display generator - Google Patents
On-line verification of video display generatorInfo
- Publication number
- CA1254683A CA1254683A CA000504431A CA504431A CA1254683A CA 1254683 A CA1254683 A CA 1254683A CA 000504431 A CA000504431 A CA 000504431A CA 504431 A CA504431 A CA 504431A CA 1254683 A CA1254683 A CA 1254683A
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- Canada
- Prior art keywords
- display
- monitor
- memory
- information
- test data
- Prior art date
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
- Digital Computer Display Output (AREA)
- Closed-Circuit Television Systems (AREA)
- Traffic Control Systems (AREA)
Abstract
ABSTRACT OF THE INVENTION
On-line verification apparatus of a display generation system comprises a memory which has a display portion and an inactive display portion, the display portion storing display information, and the inactive display portion storing test data. Scan logic controls a monitor, the scan logic accessing the memory at a predetermined location corresponding to a predetermined position of a scan beam of the monitor.
A generator, generates display control information to provide information control signals to the scan beam thereby providing the visual display corresponding to the display information stored in the display portion of the memory. A register stores display control information generated from the test data stored in the inactive display portion of the memory, the register being enabled by a control signal generated from the scan logic indicating the end of a display frame, the control signal corresponding in time to when the test data is being accessed by the scan logic. The scan logic is operative during a period of time that the monitor is blanked, the monitor being blanked allowing the scan beam of the monitor to be positioned to a beginning point of the display. An element compares the display control information stored in the register corresponding to the test data, to an expected result, the comparison being performed during the period of time the monitor is blanked, thereby verifying on-line that the display generation system is functioning correctly.
On-line verification apparatus of a display generation system comprises a memory which has a display portion and an inactive display portion, the display portion storing display information, and the inactive display portion storing test data. Scan logic controls a monitor, the scan logic accessing the memory at a predetermined location corresponding to a predetermined position of a scan beam of the monitor.
A generator, generates display control information to provide information control signals to the scan beam thereby providing the visual display corresponding to the display information stored in the display portion of the memory. A register stores display control information generated from the test data stored in the inactive display portion of the memory, the register being enabled by a control signal generated from the scan logic indicating the end of a display frame, the control signal corresponding in time to when the test data is being accessed by the scan logic. The scan logic is operative during a period of time that the monitor is blanked, the monitor being blanked allowing the scan beam of the monitor to be positioned to a beginning point of the display. An element compares the display control information stored in the register corresponding to the test data, to an expected result, the comparison being performed during the period of time the monitor is blanked, thereby verifying on-line that the display generation system is functioning correctly.
Description
ON-LINE VERIFICATION OF VIDEO DISPLAY GENER~TOR
RELATED PATENT APPLICATIONS
-This invention may be employed in a Video Display Generator such as that disclosed in Canadian Patent Application Serial No. 502,582, filed February 24, 1986, entitled "Memory Access Modes for a Video Display Generator", by K. Staggs and C. Clarke, and U.S. Patent Application Serial No. 340,141 filed January 18, 1982, now U.S. Patent No. 4,490,797, entitled, "Method and Appaxatus for Controlling the Display of a Computer Generated Raster Graphic System", both applications assigned to the same assignee as the present application.
BACKGROUND OF_THE INVENTION
This invention relates to video display systems, and more particularly to an apparatus for the on-line verification of the functionality of the various subsystems within the video dis-play system.
I20nO~38 9 May 1985 "PA~ENT~
In exis~ing video display systems which include logic such as raster scan logic, counters, video memories, and shift registers, verification of the system while still on-line is accomplished by displaying a test pattern for the user to examine and left for the user to observe the test pattern and conclude that everything is functioning peoperly if the test pattern conforms to the expected display.
This technique has worked whenever the user is looking for something wrong, but the first drawback is that the user has to think something is wrong. The present invention takes the user out of the loop for determining if something is wrong and verifies that the system is functioning properly on-line without interfering with the information being displayed, and without intervention by the user.
S~MMARY OF T~ INVENTION
Therefore, there i8 supplied by the present invention an apparatus for the on-line verification of the functionality of a video display system. In a display generation system, having a monitor for providing a visual display, the visual display being I20^~038 9 May 1985 nPATENTU
projected on a display surface by a scan beam associated with the monitor in response to position control signals and information control signals, an apparatus for on-line verification of the display generation system, comprising a memory. The memory has a display portion and an inactive display portion, the display portion of the memory being utilized for storing display information to be displayed on the monitor, and the inactive display portion being utilized for storing test data. Scan logic, operatively connected to the memory, controls the monitor, including providing the position control signals to the monitor. The scan logic accesses the memory at a predetermined location corresponding to a predetermined position of the scan beam of the monitor. A generator, operatively connected to the memory, generates display control information from the display information, the display control information being operatively coupled to the monitor to provide the information control signals to the scan beam thereby providing the visual display corresponding to the display information stored in the display portion of the memory. A register, operatively connected to 20~n038 9 May 1985 nPATENT~
generator, stores display control information generated from the test data stored in the inactive display portion of the memory, the register being enabled by a control signal qenerated from the scan logic indicating the end of a display frame. The control signal corresponds in time to when the test data is being accessed by the scan logic. The scan logic is operative during a period of time that the monitor is blanked, the monitor being blanked thereby allowing the scan beam of the monitor to be positioned to a beginning point of the visual display. An element, operatively connected to the register, compares the display control information stored in the register corresponding to test data, to an expected result, the comparison being performed during the period of time the monitor i8 blanked, thereby verifying on-line that the display generation system is functioning correctly and to indicate an error when no comparison exists.
Accordingly, it is an object of the present invention to provlde an apparatus for on-line verification of a display system.
I20~038 9 Ma~ 1985 i'PATENT"
It is ano~her object o~ the present in~en~ion to provide an apparatus for on-line verification of a display EySt2m without involving a human operator.
It is still another object of the present invention to provide an apparatus for on-line verification of a display system without interfering with the normal display operation of the display system.
These and other objects of the present invention will become more apparent when taken in conjunction with the following description and attached drawings, wherein like characters indicate like parts, and which drawings form a part of the present application.
BRIE~ D~SCRIPTION OF T~ DRAWIN~S
Figure 1 shows an apparatus for a display generation system;
Figure 2 shows an organization of a pixel memory of the display generation system;
Figure 3 shows a layo~t of a CRT display for the display generation system as it corresponds to the pixel memory organization;
I20~038 g May 1985 ~PATENT"
Fi~ure 4 show6 some of the logic of the display generation system utilized for displaying the information stored in the display memories;
Figure 5 shows a partial functional logic block dia~ram of the raster scan logic o the display generation sy~tem; and Figure 6 shows a block diagram of the apparatus added to the display generation system to provide the on-line verification function.
D~TAILED D~SCRIPTION
Referring to Figure 1, there is shown an apparatus for a display generation system. A graphics processor 10 of the preferred embodiment includes a Motorola 68000 microprocessor (not shown) and an associated R~M
tnot shown). The graphics processor 10 interfaces with a video display generator 11. The video display generator 11 provides the necessary signals to generate displays on and control of a raster scan CRT
monitor tnot shown). The video di~play generator 11 include~ various display and control memories 22, 16, a cursor display logic 18, raster scan logic 20, color look-up address generation logic 28~ and a D/A
I 20 r ~ 038 9 May 1985 R PATENT n ~ 7 ~
conver~er 32. A pixel clock 24 is includea to produce the required clocking signals for the video display generator. Latches and shift registers 26f 30 are operatively coupled to the display memory 22, and along with the clocking signals f rom the pixel clock 24, are shifted in a synchronous fashion to correspond to the scanning of the beam of the CRT monitor in order to produce the desired display.
In the preferred embodiment of the present 0 inventionS a loopback register 34 and a snapshot register 36 are added. The loopback register 34 provides the capability for the graphics processor 10 to write various data patterns into the loopback register 34 and read the data back which accomplishes the verification of the data paths to and from the graphics processor 10. The snapshot register 36 stores an 8-bit output generated by the color lookup address generator 28 based on a predetermined input, the predetermined input being known information stored in display memories 22 by the graphics proces90r 10.
The 8-bit output stored in snapshot register 36 is checked by the graphics processor 10 to determine if the correct output has been generated, thereby I2Q~038 9 May 1 ~ 5 "PATENT"
verifying several of the logic blocks within the video display generator 11. These added registers permit the video display generator 11 to be tested while continuing to provide operational displays on the CRT
monitor, i.e., the testing is being performed in an on-line modeO
The raster scan logic 20 generates all of the timing and sync signals for the raster scan CRT
monitor (not shown) and the necessary timing and control signals for all accesses of the display memories 22. Counters (not shown) in the raster scan logic 20 determine which displayable element on the raster scan CRT monitor is currently being displayed and which address to access in the display memories The display memories 22 are crganized in two different forms referred to as the picture element (pixel) memory 12 and the alphagraphic memory (also referred to as the graphic memory) 14. A more detailed description of the format of the pixel memory 12 and the graphic memory 14 will be described in detail hereinunder.
The cursor display logic 18 generates a visible cursor which can be positioned anywhere on the display under control of the graphic controller 10. A more detailed description of the generation of cursors for a raster graphic display can be had by referring to Canadian Application, Serial Number 460,312 filed August 3, 1984, enti.tled "Method and Appara-tus for Generating Cursors for a Raster Graphic Display", assigned to the same assignee as the present application.
The color lookup address generation logic 28 determines if the current displayable element is a pixel, alphagraphic, or cursor element (based on the display priority) and uses this determination along with the proper index bits !Pixel or alpha-graphic) to access a location in the color lookup memory 16. The color lookup memory 16, a-t locations having addresses correspon-ding to the color addresses applied by the color lookup address generator logic 28, has stored color control signals which are used to control -the intensity of the elec-tron beams of the color guns of a conventional color CRT monitor (not shown) and which determine the color and intensity of each picture element of the display array as it is scanned. An I2~ '038 9 May 198~ ~PATENT~
eight-bit byte is s~ored in the color lookup memory 16 a~ locations corresponding ~o the color addresses applied. In synchronism wi~h the scanning of each pixel of the display, the color rontrol signal is read out of color lookup memory 16 and applied to D to A
converters 32. D to A converters 32 convert 6 of the 8 binary signals into analoq signals for controlling intensity of the red, green, and blue electron beam yuns of the conventional CRT monitor~ In addition, in the preferred embodiment, two bits of the color control signal are applied to a fourth D to A
converter which converts these two bits into a monochrome analog signal which can be used to produce a permanent record of the raster display using conventional equipment, as is well known in the art.
A more complete description of the color lookup address generation logic 28 and the associated color lookup memory 16 can be had by referring to ~.S.
Patent No. 4,490,797 entitled "Method and Apparatus for Con~rolling the Display of a Computer Generated Raster Graphic System,~ assigned to the same assignee as the present application.
I2~ 3 8 9 May ~ g~ 3 nP~l'E
Before proceeding with describing the on-line verification of the present invention, an understanding of the operation of some of the components o the video display general:or 11 is in order.
Figure 2 shown an organization of the pixel memory 12 and Figure 3 shows a layout of the CRT monitor display. Referring to Figures 2 and 3, the relationship of the organization of the display memory 22 (although l:he discussion with respect to Figure 2 will be specifically directed to the pixel memory 12, there is a similar organization for graphic memory 14) will now be described. The active display area of the CRT monitor of the preferred embodimen~ of the present invention is divided into 640 horizontal elements and 448 vertica~l elementsO A character size chosen for the display of the preferred embodiment is a 5X3 character in an 8X16 character cell ~ i . e., 8 horizontal pixels by 16 vertical pixels). The pixel memory 12 contains five planes, p(), Pl, P~2r p3, and p4. Each plane is an 8 bit wide by 64K memory. Each location of each plane contains 8 bits of information relating to 8 corresponding picture I2onoa38 9 May 19~5 ~ ~ ~PATENT~
~2-elements. ~lence, location 0 of the pixel memory 12 contains information relating to picture elements 0,0 through 0,7 of the display~ The first bit of location 0 of pi~el memory 12 contains information relating to picture element 0,0 of the di~play, the second bit of location 0 of pixel memory 12 contains information relating to picture element 0,1 of the display, In order to display the information of the display memory 22~ it is necessary that the information in display memory 22 correspond to the position of the sweep of the CRT monitor (not shown), In raster scan CRT monitors, generally the sweep is a horizontal sweep from left to right, top to bottom, in which the sweep starts at location 0,0 and moves horizontally lS across thle display to location 0,639. Thus, the information fetched from display memory 22 for display must correspond to the positioning of the sweep of the CRT monitor. Namely, location 0 of display memory 2~
is fetched which corresponds to picture elements 0,0 through 0,7, then location ~12 oE display memory 22 i5 fetched which corresponds to the picture elements 0,8 through 0,15, then location 1024 is fetched... up to location 40448 which corresponds to picture element I20000~ 9 May 1985 ~PATENT"
~13~
0,632 through 0~639r The next line of the display (picture element 1, 0 through 1, 639 is scanned and the corresponding information is fetched from the display memory 22 at locatio~ 1, 513, 1025~... When line 447 is completed, the display has been completed and the scanning is restarted at line 0. The hole area in memory corresponds to the display area 448 -511. Hence, locations 448 through 511, 960 through 1023, 1472 through 1535,... of display memory 22 have no corresponding active display area. The fetch of the information from display memory 22 is performed by logic in the raster scan logic 20. By adding 1 to bit 9 (i.e., to the 512 bit position) of an address counter, the correct addressing scheme is generated corresponding to the CRT beam as it is swept across a horizontal line. By allowing the hole area in memory, the implementation of incrementirlg the counter of the raster scan logic is simplified. The area of the display from 640 to 1023 also corresponds to a memory hole area from locations 40960 to 64~ (i.e., 65535).
The apparent inefficient use of memor~ is more than negated by the ease of implementing an addressing scheme corresponding ~o the display layout.
I2000038 9 May l~B5 "PATENT"
~ 3 Although a line by line scanning of the display area has been described, alternative vertical scanning techniques are well known. In the preferred embodiment of the present invention interlace scanning is implemented with the organization of the display memory 22 just described. The raster scan logic is implemented such that the low order bit position of the counter for accessing the display memory 22 i~
alternately set between a 1 and a O on alternate vertical scans as will be described hereinunder.
The alphagraphic memory 14 also corresponds to a display which is 640 horizontal elements and 448 vertical elements. The graphic memory 14 consists of
RELATED PATENT APPLICATIONS
-This invention may be employed in a Video Display Generator such as that disclosed in Canadian Patent Application Serial No. 502,582, filed February 24, 1986, entitled "Memory Access Modes for a Video Display Generator", by K. Staggs and C. Clarke, and U.S. Patent Application Serial No. 340,141 filed January 18, 1982, now U.S. Patent No. 4,490,797, entitled, "Method and Appaxatus for Controlling the Display of a Computer Generated Raster Graphic System", both applications assigned to the same assignee as the present application.
BACKGROUND OF_THE INVENTION
This invention relates to video display systems, and more particularly to an apparatus for the on-line verification of the functionality of the various subsystems within the video dis-play system.
I20nO~38 9 May 1985 "PA~ENT~
In exis~ing video display systems which include logic such as raster scan logic, counters, video memories, and shift registers, verification of the system while still on-line is accomplished by displaying a test pattern for the user to examine and left for the user to observe the test pattern and conclude that everything is functioning peoperly if the test pattern conforms to the expected display.
This technique has worked whenever the user is looking for something wrong, but the first drawback is that the user has to think something is wrong. The present invention takes the user out of the loop for determining if something is wrong and verifies that the system is functioning properly on-line without interfering with the information being displayed, and without intervention by the user.
S~MMARY OF T~ INVENTION
Therefore, there i8 supplied by the present invention an apparatus for the on-line verification of the functionality of a video display system. In a display generation system, having a monitor for providing a visual display, the visual display being I20^~038 9 May 1985 nPATENTU
projected on a display surface by a scan beam associated with the monitor in response to position control signals and information control signals, an apparatus for on-line verification of the display generation system, comprising a memory. The memory has a display portion and an inactive display portion, the display portion of the memory being utilized for storing display information to be displayed on the monitor, and the inactive display portion being utilized for storing test data. Scan logic, operatively connected to the memory, controls the monitor, including providing the position control signals to the monitor. The scan logic accesses the memory at a predetermined location corresponding to a predetermined position of the scan beam of the monitor. A generator, operatively connected to the memory, generates display control information from the display information, the display control information being operatively coupled to the monitor to provide the information control signals to the scan beam thereby providing the visual display corresponding to the display information stored in the display portion of the memory. A register, operatively connected to 20~n038 9 May 1985 nPATENT~
generator, stores display control information generated from the test data stored in the inactive display portion of the memory, the register being enabled by a control signal qenerated from the scan logic indicating the end of a display frame. The control signal corresponds in time to when the test data is being accessed by the scan logic. The scan logic is operative during a period of time that the monitor is blanked, the monitor being blanked thereby allowing the scan beam of the monitor to be positioned to a beginning point of the visual display. An element, operatively connected to the register, compares the display control information stored in the register corresponding to test data, to an expected result, the comparison being performed during the period of time the monitor i8 blanked, thereby verifying on-line that the display generation system is functioning correctly and to indicate an error when no comparison exists.
Accordingly, it is an object of the present invention to provlde an apparatus for on-line verification of a display system.
I20~038 9 Ma~ 1985 i'PATENT"
It is ano~her object o~ the present in~en~ion to provide an apparatus for on-line verification of a display EySt2m without involving a human operator.
It is still another object of the present invention to provide an apparatus for on-line verification of a display system without interfering with the normal display operation of the display system.
These and other objects of the present invention will become more apparent when taken in conjunction with the following description and attached drawings, wherein like characters indicate like parts, and which drawings form a part of the present application.
BRIE~ D~SCRIPTION OF T~ DRAWIN~S
Figure 1 shows an apparatus for a display generation system;
Figure 2 shows an organization of a pixel memory of the display generation system;
Figure 3 shows a layo~t of a CRT display for the display generation system as it corresponds to the pixel memory organization;
I20~038 g May 1985 ~PATENT"
Fi~ure 4 show6 some of the logic of the display generation system utilized for displaying the information stored in the display memories;
Figure 5 shows a partial functional logic block dia~ram of the raster scan logic o the display generation sy~tem; and Figure 6 shows a block diagram of the apparatus added to the display generation system to provide the on-line verification function.
D~TAILED D~SCRIPTION
Referring to Figure 1, there is shown an apparatus for a display generation system. A graphics processor 10 of the preferred embodiment includes a Motorola 68000 microprocessor (not shown) and an associated R~M
tnot shown). The graphics processor 10 interfaces with a video display generator 11. The video display generator 11 provides the necessary signals to generate displays on and control of a raster scan CRT
monitor tnot shown). The video di~play generator 11 include~ various display and control memories 22, 16, a cursor display logic 18, raster scan logic 20, color look-up address generation logic 28~ and a D/A
I 20 r ~ 038 9 May 1985 R PATENT n ~ 7 ~
conver~er 32. A pixel clock 24 is includea to produce the required clocking signals for the video display generator. Latches and shift registers 26f 30 are operatively coupled to the display memory 22, and along with the clocking signals f rom the pixel clock 24, are shifted in a synchronous fashion to correspond to the scanning of the beam of the CRT monitor in order to produce the desired display.
In the preferred embodiment of the present 0 inventionS a loopback register 34 and a snapshot register 36 are added. The loopback register 34 provides the capability for the graphics processor 10 to write various data patterns into the loopback register 34 and read the data back which accomplishes the verification of the data paths to and from the graphics processor 10. The snapshot register 36 stores an 8-bit output generated by the color lookup address generator 28 based on a predetermined input, the predetermined input being known information stored in display memories 22 by the graphics proces90r 10.
The 8-bit output stored in snapshot register 36 is checked by the graphics processor 10 to determine if the correct output has been generated, thereby I2Q~038 9 May 1 ~ 5 "PATENT"
verifying several of the logic blocks within the video display generator 11. These added registers permit the video display generator 11 to be tested while continuing to provide operational displays on the CRT
monitor, i.e., the testing is being performed in an on-line modeO
The raster scan logic 20 generates all of the timing and sync signals for the raster scan CRT
monitor (not shown) and the necessary timing and control signals for all accesses of the display memories 22. Counters (not shown) in the raster scan logic 20 determine which displayable element on the raster scan CRT monitor is currently being displayed and which address to access in the display memories The display memories 22 are crganized in two different forms referred to as the picture element (pixel) memory 12 and the alphagraphic memory (also referred to as the graphic memory) 14. A more detailed description of the format of the pixel memory 12 and the graphic memory 14 will be described in detail hereinunder.
The cursor display logic 18 generates a visible cursor which can be positioned anywhere on the display under control of the graphic controller 10. A more detailed description of the generation of cursors for a raster graphic display can be had by referring to Canadian Application, Serial Number 460,312 filed August 3, 1984, enti.tled "Method and Appara-tus for Generating Cursors for a Raster Graphic Display", assigned to the same assignee as the present application.
The color lookup address generation logic 28 determines if the current displayable element is a pixel, alphagraphic, or cursor element (based on the display priority) and uses this determination along with the proper index bits !Pixel or alpha-graphic) to access a location in the color lookup memory 16. The color lookup memory 16, a-t locations having addresses correspon-ding to the color addresses applied by the color lookup address generator logic 28, has stored color control signals which are used to control -the intensity of the elec-tron beams of the color guns of a conventional color CRT monitor (not shown) and which determine the color and intensity of each picture element of the display array as it is scanned. An I2~ '038 9 May 198~ ~PATENT~
eight-bit byte is s~ored in the color lookup memory 16 a~ locations corresponding ~o the color addresses applied. In synchronism wi~h the scanning of each pixel of the display, the color rontrol signal is read out of color lookup memory 16 and applied to D to A
converters 32. D to A converters 32 convert 6 of the 8 binary signals into analoq signals for controlling intensity of the red, green, and blue electron beam yuns of the conventional CRT monitor~ In addition, in the preferred embodiment, two bits of the color control signal are applied to a fourth D to A
converter which converts these two bits into a monochrome analog signal which can be used to produce a permanent record of the raster display using conventional equipment, as is well known in the art.
A more complete description of the color lookup address generation logic 28 and the associated color lookup memory 16 can be had by referring to ~.S.
Patent No. 4,490,797 entitled "Method and Apparatus for Con~rolling the Display of a Computer Generated Raster Graphic System,~ assigned to the same assignee as the present application.
I2~ 3 8 9 May ~ g~ 3 nP~l'E
Before proceeding with describing the on-line verification of the present invention, an understanding of the operation of some of the components o the video display general:or 11 is in order.
Figure 2 shown an organization of the pixel memory 12 and Figure 3 shows a layout of the CRT monitor display. Referring to Figures 2 and 3, the relationship of the organization of the display memory 22 (although l:he discussion with respect to Figure 2 will be specifically directed to the pixel memory 12, there is a similar organization for graphic memory 14) will now be described. The active display area of the CRT monitor of the preferred embodimen~ of the present invention is divided into 640 horizontal elements and 448 vertica~l elementsO A character size chosen for the display of the preferred embodiment is a 5X3 character in an 8X16 character cell ~ i . e., 8 horizontal pixels by 16 vertical pixels). The pixel memory 12 contains five planes, p(), Pl, P~2r p3, and p4. Each plane is an 8 bit wide by 64K memory. Each location of each plane contains 8 bits of information relating to 8 corresponding picture I2onoa38 9 May 19~5 ~ ~ ~PATENT~
~2-elements. ~lence, location 0 of the pixel memory 12 contains information relating to picture elements 0,0 through 0,7 of the display~ The first bit of location 0 of pi~el memory 12 contains information relating to picture element 0,0 of the di~play, the second bit of location 0 of pixel memory 12 contains information relating to picture element 0,1 of the display, In order to display the information of the display memory 22~ it is necessary that the information in display memory 22 correspond to the position of the sweep of the CRT monitor (not shown), In raster scan CRT monitors, generally the sweep is a horizontal sweep from left to right, top to bottom, in which the sweep starts at location 0,0 and moves horizontally lS across thle display to location 0,639. Thus, the information fetched from display memory 22 for display must correspond to the positioning of the sweep of the CRT monitor. Namely, location 0 of display memory 2~
is fetched which corresponds to picture elements 0,0 through 0,7, then location ~12 oE display memory 22 i5 fetched which corresponds to the picture elements 0,8 through 0,15, then location 1024 is fetched... up to location 40448 which corresponds to picture element I20000~ 9 May 1985 ~PATENT"
~13~
0,632 through 0~639r The next line of the display (picture element 1, 0 through 1, 639 is scanned and the corresponding information is fetched from the display memory 22 at locatio~ 1, 513, 1025~... When line 447 is completed, the display has been completed and the scanning is restarted at line 0. The hole area in memory corresponds to the display area 448 -511. Hence, locations 448 through 511, 960 through 1023, 1472 through 1535,... of display memory 22 have no corresponding active display area. The fetch of the information from display memory 22 is performed by logic in the raster scan logic 20. By adding 1 to bit 9 (i.e., to the 512 bit position) of an address counter, the correct addressing scheme is generated corresponding to the CRT beam as it is swept across a horizontal line. By allowing the hole area in memory, the implementation of incrementirlg the counter of the raster scan logic is simplified. The area of the display from 640 to 1023 also corresponds to a memory hole area from locations 40960 to 64~ (i.e., 65535).
The apparent inefficient use of memor~ is more than negated by the ease of implementing an addressing scheme corresponding ~o the display layout.
I2000038 9 May l~B5 "PATENT"
~ 3 Although a line by line scanning of the display area has been described, alternative vertical scanning techniques are well known. In the preferred embodiment of the present invention interlace scanning is implemented with the organization of the display memory 22 just described. The raster scan logic is implemented such that the low order bit position of the counter for accessing the display memory 22 i~
alternately set between a 1 and a O on alternate vertical scans as will be described hereinunder.
The alphagraphic memory 14 also corresponds to a display which is 640 horizontal elements and 448 vertical elements. The graphic memory 14 consists of
2 memory planes with each plane organized such that each 8-bit byte corresponds to 8 horizontal elements by 1 vertical element. In a first plane, denoted a dot memory, each bi.t determines if the picture element is a foreground or background color. In a second plane, denoted the behavior memory, each 8 bit location determines the behavior index of an entire associated location in the dot memory, and the display priority between the pixel memory 12 and the alphagraphic memory 14O Of the 8 bits, a behavior I20~nO38 9 May 1985 nPATENT"
-1 5~ ~ ~ P f ~
index is 6 bits and a di~play priority i 2 bits. The 6 bits representing the behavior index and the 1 bit identification of each foreground or background color results in a 7 bit val~e used as an index into the color lookup memory 16. The 2 priority bits determine the priority of the pixel display with respect to the alphagraphic display~ The priority is one of three levels which are more fully described in the aforementioned references. The pixel memory 12 stores characteri~tic information for each pixel element;
namely, planes 0-2 contains color information, plane 3 contains intensity information, and plane 4 contains blink information.
Referring to Figure 4, there is shown some of the lS logic of the video display generator 11 utilized for displaying the information stored in the display memories 22. The raster scan logic 20 reads the alphagraphic memory 14 and the pixel memory 12 at the same location, in the example shown in Fi.gure 5 location 0 is being read. The 8 bits from the dot memory 14' are loaded into a ~hift register 26B and the 6 bits from location 0 of the behavior memory 14'' are being loaded into a latch 26A. Likewise, the I2o~no38 9 May 1~85 "PATENT"
16 3L l~d ~
contents of location 0 of each plane of the pixel memory 12 is loaded into a corresponding shift regis~er. Thus, the B bits of location 0 rom plane 0 is loaded into shift register SR-0, the 8 hits from location 0 of plane 1 is loaded into SR-l,....... , and the 8 bits from location 0 of plane 4 is loaded into SR-4. All of the shift registers are shifted such that the color lookup address generation logic 28 processes the information related to picture element 0,0 from both ~he pixel memory 12 and the dot memory 14'. Processing is performed to correspond to the information contained in latch 26A. At this point in time the sweep of the CRT monitor is at location 0,0 of the display. Synchronized by the clocking signal, the display moves to the next position, i.e., picture element 0,1 of the display and likewise the information corresponding to location 0,1 is shifted into the color lookup address ~eneration logic 2B from the shift registers 30 and the shift register 26B.
Again, this information is processed by the color lookup address generation logic 28 as defined by the information latched in latch 26A, which is valid for the 8 bits of location 0~ The process continues until I2(1nOO38 9 May 19~5 ~P~TENT"
1~ r - ~f ~
the sweep of the C~T monitor has displayed the 8 picture elements of a horizontal line. The next element to be displayed is location 0,8 which corre~pond~ to address 51~ The raster scan logic 20 causes a read of location 512 from the graphic memory 14 and the pixel memory 12 into the shift registers and latch and the above process continues until the entire line is displayed, and then continues as described above until the entire display area has been processed for display.
Referring to Figure 5, there is shown a partial functional logic block diagram of the raster scan logic 20. The counters shown in Figure 5 are part of the raster scan logic 20 which are verified by the verification apparatus of the present invention and include a divide-by-eight ~ircuit 42 of the pixel clock signal, horizontal address counter 44, vertical address counter 46, an odd/even frame counter 48, an end-of-line detector 50, and an end-of-frame detector 52. The outputs of the horizontal address counter 44, vertical addres~ counter 46, and odd/even f rame counter 48 are coupled to the display memory 22 for addressing the display memory. The outputs of the 20nO038 9 May 1985 nPATENT~
-18~
horizon~al address counter 44l the vertical address counter 46, and the odd/even frame coun~er 48, make up the display memory address. The output of the odd/even frame counter 48 makes up the least significant bit portion, the 8-bits outputted from the vertical address counter 46 make up the next least significant bits of the memory address, and the 7-bits outputted from the horizontal address counter make up the most significant bit portion of the display memory address. The pixels are read from the display memory 22 in groups of eight pixels at a time and loaded into shift registers and latches 26, 30 as described above therefore requiring the pixel clock signal to be divided by eiqht when clocking the horizontal address counter 44. The horizontal address counter 44 is allowed to continue to count during horizontal retrace, the count being used for generating synchronizing signals. The retrace count for the horizontal address counter 44 of the preferred em~odiment of the present invention is 16 cells which result in a total count of 768 for each horizontal line. When the end of-line detector 50 de~ermines that the horizontal address counter 44 is at the end I20 `038 9 May 1985 ~PATENT"
-19~ 3 of a current scan line, the end-of-line detector 50 as~erts an end-of-line signal back to the horizontal address counter 44 which resets the counters to a value of -14. While the counters are incrementing from -14 to 0 the display is blanked and the video di~play generator 11 is generating horizontal synchronization signals to the CRT monitor (not shown). Also, when the end-of-line detector 50 sends the end-of-line signal, the vertical address counter 4b is incremented. In the preferred embodiment of the present invention, the video display generator 11 is an interlace system, two frames of the display comprising a single complete display. One frame is all of the even horizontal lines of the display and the other frame is all of the odd horizontal lines of the display. During each vertical scan of the CRT
monitor, the frames are alternated as a re~ult of the odd~even frame counter 48. The vertical address counter 46 is similar in operation to the horizontal address counter 44 except that the vertical address counter 46 is only incremented at the end of each horizontal scan line. When the end-of-frame detector 52 senses that the display is at the end of the frame I20t)003E3 9 M~y 1985 ~ ~r ~ "PATENT"
~2(~--an end-of-frame signal i5 gençrated, the vertical address counter 46 i~ reset to -16, and the odd/even frame counter 48 i5 toggled. While the vertical address counter 46 is counting from the count of -16 to 0, the CRT display is blanked and the video display generator 11 is generatin~ the synchronization signals to the CRT monitor.
What has been described thus far is the normal operation of the video display generator 11.
Referring to Figure 6, there is shown a block diagram of the apparatus added to the video display generator 11 to provide the on-line verification function. In order to permit the on-line verification of the video display generator 11, the end-of-frame signal is utilized a6 a vertical retrace interrupt ~ignal back to the microprocessor of the graphics processor 10.
Referring back to Figures 2 and 3, when the video sweep has reached the point 447, 639, the odd frame is completed and the vertical retrace signal is generated (point 446, 639 is the last point for the even frame~. Since the horizontal address counter 44 and the vertical address counter 46 continue to count during retrace, the logic will address location 449 of I20 `038 9 May 1985 ~ PATENT"
the display memories 22 which corresponds to the points 449,0 through 449,7 (for the even frame the location to be addressed and accessed is location 448 which corresponds to points 448,0 through 448,7).
Although locations 448,0-7 and 449,0-7 are in the ~hole" area of display memory 22 (i.e., there is no corresponding active display area for these locations) test data is prestored into locations 448 and 449.
Since the logic of the video display generator ll is active, the counters of raster scan 20 are counting during the retrace period, and the locations in the hole area are being accessed.
Referring back to Figure 6, the end-of-frame signal (or vertical retrace interrupt which is active for eight pixel times or eight bits) enable a serial-to-parallel shift register 39 d~ring a portion of the retrace period while location 449 is being addressed (location 44~ for the even frame). The address information contained on the data lines from color lookup address generator 28 correspond to the eight bits of address information generated by the counters and shift registers of the logic of video display generator ll based on the test data stored in I2Qr~038 9 May 1385 ~PATENT"
~2~
location 449 (location 448 for the even frame retrace). An interrupt routine in ~he graphics processor 10 sets up the loopback register 34 such that a MUX 37 se~uentially inputs the generated S address information from the ~olor lookup address generator 28 i~to the serial-to-parallel shift register 39. When the shift register 39 is full the data is read by the graphics ~rocessor 10 and compared to an expected result. The test data stored in the display memory 22 is varied by the graphics processor 10 to different patterns to ensure all the logic of the video display generator 11 is adequately tested.
Since the color lookup memory is a RAM the color lookup memory 16 can be tested by reading and writing into the RAM. The loopback register 34 is utilized to verify the data paths from the graphics processor 10 to the video display generator 11 and can be done in an off-line as well as an on-line mode. Thus, all the logic of the video display generator 11 can be verified on-line up to the inputs to the D to converters 32. If the data read from the shift register 39 does not contain the expec~ed result an error signal can be raised, or a number of retries can I2000038 9 May 1~85 nPATENT~
-- 2 3 ~ e~.~
be executed until a hard failure is signalled, the determination of the hard failure being a design choice D
In the preferred embodiment of the present invention, ei~ht vertical frames are necessary to verify the test word addresses generated by the color lookup address generator 28. The choice to capture the generated addresses in the above described manner results in less hardware and is a matter of design choice. Thus, for example, in the preferred embodiment of the present inventionl during the first retrace loopback register 34 is set up to select bit. 0 of the output of color lookup address generator 28, and the results stored in the shift register 39 are for the first pixel-bit 0, second pixel-bit 0, eighth pixel-bit 0. For the next vertical retrace, loopback register is set up by graphic controller lO
to read bit 1, . DD until the eighth retrace when bi.t 7 for all eight pixels of the test word are read.
While there has been shown what is corlsidered the preferred embodiment of the present invention, it will be manifest that many changes and modifications can be made therein without departing from the essential I200nO38 9 May 1985 "PATENT"
~24~
~pirit and scope of the invention. It is intended, therefore, in the annexed claims to cover all such changes and modificatiorls which f~ll wi'chin the true ~cope of the inventi~n.
-1 5~ ~ ~ P f ~
index is 6 bits and a di~play priority i 2 bits. The 6 bits representing the behavior index and the 1 bit identification of each foreground or background color results in a 7 bit val~e used as an index into the color lookup memory 16. The 2 priority bits determine the priority of the pixel display with respect to the alphagraphic display~ The priority is one of three levels which are more fully described in the aforementioned references. The pixel memory 12 stores characteri~tic information for each pixel element;
namely, planes 0-2 contains color information, plane 3 contains intensity information, and plane 4 contains blink information.
Referring to Figure 4, there is shown some of the lS logic of the video display generator 11 utilized for displaying the information stored in the display memories 22. The raster scan logic 20 reads the alphagraphic memory 14 and the pixel memory 12 at the same location, in the example shown in Fi.gure 5 location 0 is being read. The 8 bits from the dot memory 14' are loaded into a ~hift register 26B and the 6 bits from location 0 of the behavior memory 14'' are being loaded into a latch 26A. Likewise, the I2o~no38 9 May 1~85 "PATENT"
16 3L l~d ~
contents of location 0 of each plane of the pixel memory 12 is loaded into a corresponding shift regis~er. Thus, the B bits of location 0 rom plane 0 is loaded into shift register SR-0, the 8 hits from location 0 of plane 1 is loaded into SR-l,....... , and the 8 bits from location 0 of plane 4 is loaded into SR-4. All of the shift registers are shifted such that the color lookup address generation logic 28 processes the information related to picture element 0,0 from both ~he pixel memory 12 and the dot memory 14'. Processing is performed to correspond to the information contained in latch 26A. At this point in time the sweep of the CRT monitor is at location 0,0 of the display. Synchronized by the clocking signal, the display moves to the next position, i.e., picture element 0,1 of the display and likewise the information corresponding to location 0,1 is shifted into the color lookup address ~eneration logic 2B from the shift registers 30 and the shift register 26B.
Again, this information is processed by the color lookup address generation logic 28 as defined by the information latched in latch 26A, which is valid for the 8 bits of location 0~ The process continues until I2(1nOO38 9 May 19~5 ~P~TENT"
1~ r - ~f ~
the sweep of the C~T monitor has displayed the 8 picture elements of a horizontal line. The next element to be displayed is location 0,8 which corre~pond~ to address 51~ The raster scan logic 20 causes a read of location 512 from the graphic memory 14 and the pixel memory 12 into the shift registers and latch and the above process continues until the entire line is displayed, and then continues as described above until the entire display area has been processed for display.
Referring to Figure 5, there is shown a partial functional logic block diagram of the raster scan logic 20. The counters shown in Figure 5 are part of the raster scan logic 20 which are verified by the verification apparatus of the present invention and include a divide-by-eight ~ircuit 42 of the pixel clock signal, horizontal address counter 44, vertical address counter 46, an odd/even frame counter 48, an end-of-line detector 50, and an end-of-frame detector 52. The outputs of the horizontal address counter 44, vertical addres~ counter 46, and odd/even f rame counter 48 are coupled to the display memory 22 for addressing the display memory. The outputs of the 20nO038 9 May 1985 nPATENT~
-18~
horizon~al address counter 44l the vertical address counter 46, and the odd/even frame coun~er 48, make up the display memory address. The output of the odd/even frame counter 48 makes up the least significant bit portion, the 8-bits outputted from the vertical address counter 46 make up the next least significant bits of the memory address, and the 7-bits outputted from the horizontal address counter make up the most significant bit portion of the display memory address. The pixels are read from the display memory 22 in groups of eight pixels at a time and loaded into shift registers and latches 26, 30 as described above therefore requiring the pixel clock signal to be divided by eiqht when clocking the horizontal address counter 44. The horizontal address counter 44 is allowed to continue to count during horizontal retrace, the count being used for generating synchronizing signals. The retrace count for the horizontal address counter 44 of the preferred em~odiment of the present invention is 16 cells which result in a total count of 768 for each horizontal line. When the end of-line detector 50 de~ermines that the horizontal address counter 44 is at the end I20 `038 9 May 1985 ~PATENT"
-19~ 3 of a current scan line, the end-of-line detector 50 as~erts an end-of-line signal back to the horizontal address counter 44 which resets the counters to a value of -14. While the counters are incrementing from -14 to 0 the display is blanked and the video di~play generator 11 is generating horizontal synchronization signals to the CRT monitor (not shown). Also, when the end-of-line detector 50 sends the end-of-line signal, the vertical address counter 4b is incremented. In the preferred embodiment of the present invention, the video display generator 11 is an interlace system, two frames of the display comprising a single complete display. One frame is all of the even horizontal lines of the display and the other frame is all of the odd horizontal lines of the display. During each vertical scan of the CRT
monitor, the frames are alternated as a re~ult of the odd~even frame counter 48. The vertical address counter 46 is similar in operation to the horizontal address counter 44 except that the vertical address counter 46 is only incremented at the end of each horizontal scan line. When the end-of-frame detector 52 senses that the display is at the end of the frame I20t)003E3 9 M~y 1985 ~ ~r ~ "PATENT"
~2(~--an end-of-frame signal i5 gençrated, the vertical address counter 46 i~ reset to -16, and the odd/even frame counter 48 i5 toggled. While the vertical address counter 46 is counting from the count of -16 to 0, the CRT display is blanked and the video display generator 11 is generatin~ the synchronization signals to the CRT monitor.
What has been described thus far is the normal operation of the video display generator 11.
Referring to Figure 6, there is shown a block diagram of the apparatus added to the video display generator 11 to provide the on-line verification function. In order to permit the on-line verification of the video display generator 11, the end-of-frame signal is utilized a6 a vertical retrace interrupt ~ignal back to the microprocessor of the graphics processor 10.
Referring back to Figures 2 and 3, when the video sweep has reached the point 447, 639, the odd frame is completed and the vertical retrace signal is generated (point 446, 639 is the last point for the even frame~. Since the horizontal address counter 44 and the vertical address counter 46 continue to count during retrace, the logic will address location 449 of I20 `038 9 May 1985 ~ PATENT"
the display memories 22 which corresponds to the points 449,0 through 449,7 (for the even frame the location to be addressed and accessed is location 448 which corresponds to points 448,0 through 448,7).
Although locations 448,0-7 and 449,0-7 are in the ~hole" area of display memory 22 (i.e., there is no corresponding active display area for these locations) test data is prestored into locations 448 and 449.
Since the logic of the video display generator ll is active, the counters of raster scan 20 are counting during the retrace period, and the locations in the hole area are being accessed.
Referring back to Figure 6, the end-of-frame signal (or vertical retrace interrupt which is active for eight pixel times or eight bits) enable a serial-to-parallel shift register 39 d~ring a portion of the retrace period while location 449 is being addressed (location 44~ for the even frame). The address information contained on the data lines from color lookup address generator 28 correspond to the eight bits of address information generated by the counters and shift registers of the logic of video display generator ll based on the test data stored in I2Qr~038 9 May 1385 ~PATENT"
~2~
location 449 (location 448 for the even frame retrace). An interrupt routine in ~he graphics processor 10 sets up the loopback register 34 such that a MUX 37 se~uentially inputs the generated S address information from the ~olor lookup address generator 28 i~to the serial-to-parallel shift register 39. When the shift register 39 is full the data is read by the graphics ~rocessor 10 and compared to an expected result. The test data stored in the display memory 22 is varied by the graphics processor 10 to different patterns to ensure all the logic of the video display generator 11 is adequately tested.
Since the color lookup memory is a RAM the color lookup memory 16 can be tested by reading and writing into the RAM. The loopback register 34 is utilized to verify the data paths from the graphics processor 10 to the video display generator 11 and can be done in an off-line as well as an on-line mode. Thus, all the logic of the video display generator 11 can be verified on-line up to the inputs to the D to converters 32. If the data read from the shift register 39 does not contain the expec~ed result an error signal can be raised, or a number of retries can I2000038 9 May 1~85 nPATENT~
-- 2 3 ~ e~.~
be executed until a hard failure is signalled, the determination of the hard failure being a design choice D
In the preferred embodiment of the present invention, ei~ht vertical frames are necessary to verify the test word addresses generated by the color lookup address generator 28. The choice to capture the generated addresses in the above described manner results in less hardware and is a matter of design choice. Thus, for example, in the preferred embodiment of the present inventionl during the first retrace loopback register 34 is set up to select bit. 0 of the output of color lookup address generator 28, and the results stored in the shift register 39 are for the first pixel-bit 0, second pixel-bit 0, eighth pixel-bit 0. For the next vertical retrace, loopback register is set up by graphic controller lO
to read bit 1, . DD until the eighth retrace when bi.t 7 for all eight pixels of the test word are read.
While there has been shown what is corlsidered the preferred embodiment of the present invention, it will be manifest that many changes and modifications can be made therein without departing from the essential I200nO38 9 May 1985 "PATENT"
~24~
~pirit and scope of the invention. It is intended, therefore, in the annexed claims to cover all such changes and modificatiorls which f~ll wi'chin the true ~cope of the inventi~n.
Claims (4)
- Claim 1 (concluded) blanked, the monitor being blanked thereby allowing the scan beam of the monitor to be positioned to a beginning point of the visual display; and e) means, operatively connected to said register means, for comparing the display control information stored in said register means corresponding to said test data, to an expected result, the comparison being performed during the period of time the monitor is blanked, thereby verifying on-line that the display generation system is functioning correctly and to indicate an error when no comparison exists.
Claim 2. In a display generation system, having a memory which includes a display portion and an inactive display portion, the display portion of the memory utilized for storing display information to be displayed on a monitor and the inactive display portion utilized for storing test data, the memory being accessed at a predetermined location by scan logic corresponding to a predetermined position of a scan beam of the monitor, the display information being coupled to a generator and being utilized by the generator for generating display control information from said display information, the display control information being operatively coupled to the monitor, the display generation system further having apparatus for on-line verification of the display generation system, said apparatus comprising:
a) register means, operatively connected to said generator, for storing display control information generated from the test data stored in the inactive display portion of the memory, the register means being enabled by a control signal generated from said scan logic indicating the end of a display frame, - Claim 2 (continued) the control signal corresponding in time to when said test data is being accessed, and the monitor being blanked thereby allowing the scan beam of the monitor to be positioned to a beginning point of the display; and b) means, operatively connected to said register means, for comparing the display control information stored in said register means corresponding to said test data, to an expected result thereby verifying on-line that the display generation system is functioning correctly and to indicate an error when no comparison exists.
Claim 3. In a display generation system, having a memory which includes a display portion and an inactive display portion, the display portion of the memory utilized for storing display information to be displayed on a monitor, the memory being accessed at a predetermined location by scan logic corresponding to a predetermined position of a scan beam of the monitor, the display information being coupled to a generator and being utilized by the generator for generating display control information from said display information, the display control information being operatively coupled to the monitor, the display generation system further having apparatus for on-line verification of the display generation system, said apparatus comprising:
a) register means, operatively connected to said generator, for storing display control information generated from test data, wherein said test data is stored in the inactive display portion of the memory, the register means being enabled by a control signal generated from said scan logic indicating the end of a display frame, the - Claim 3 (continued) control signal corresponding in time to when said test data is being accessed by said scan logic, the scan logic being operative during a period of time that the monitor is blanked, the monitor being blanked at this time thereby allowing the scan beam of the monitor to be positioned to a beginning point of the display; and b) means, operatively connected to said register means, for comparing the display control information stored in said register means corresponding to said test data, to an expected result, the comparison being performed during the period of time the monitor is blanked, thereby verifying on-line that the display generation system is functioning correctly and to indicate an error when no comparison exists.
- 4. In a CRT display controller of the type wherein an addressable store holds display information representing images to be displayed on a CRT screen in a first portion of said store, wherein during a first period in which said images are being displayed on said CRT screen the locations of said first portion are addressed sequentially in predetermined order for reading out the contents of said locations, and wherein a logic unit is coupled to said store to receive the contents of locations in said store as they are read out and responsive to said contents for generating corresponding control signals, said control signals being used for causing said images to be displayed on said screen during said first period; apparatus for verifying the proper operation of said controller, characterized by:
said store holding test display information ("holes") in a second portion thereof;
addressing means for accessing in predetermined order locations of said second portion during a second period in which said CRT screen is blanked for allowing the CRT scanning beam to return to the starting point of the CRT screen display area;
a register unit for receiving the control signals generated by said logic unit during said second period; and means coupled to said register unit for determining whether the contents thereof represent the proper operation of said controller.
a) memory means, having a display portion and an inactive display portion, the display portion of said memory means being utilized for storing display information to be displayed on said monitor, and the inactive display portion being utilized for storing test data;
b) scan logic means, operatively connected to said memory means, for controlling the monitor, including providing the position control signals to the monitor, said scan logic means accessing said memory means at a predetermined location corresponding to predetermined position of the scan beam of the monitor;
Claim 1 (continued) c) generator means, operatively connected to said memory means, for generating display control information from said display information, the display control information being operatively coupled to the monitor to provide the information control signals to the scan beam thereby providing the visual display corresponding to the display information stored in the display portion of the memory means;
d) register means, operatively connected to said generator means, for storing display control information generated from the test data stored in the inactive display portion of the memory means, the register means being enabled by a control signal generated from said scan logic means indicating the end of a display frame, the control signal corresponding in time to when said test data is being accessed by said scan logic means, the scan logic means being operative during a period of time that the monitor is
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US73524185A | 1985-05-17 | 1985-05-17 | |
| US735,241 | 1991-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1254683A true CA1254683A (en) | 1989-05-23 |
Family
ID=24954934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000504431A Expired CA1254683A (en) | 1985-05-17 | 1986-03-18 | On-line verification of video display generator |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0202865B1 (en) |
| JP (1) | JPH0642132B2 (en) |
| AU (1) | AU579928B2 (en) |
| CA (1) | CA1254683A (en) |
| DE (1) | DE3682322D1 (en) |
| NO (1) | NO169926C (en) |
| SG (1) | SG2392G (en) |
| ZA (1) | ZA862964B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149124A (en) * | 1987-12-07 | 1989-06-12 | Yokogawa Electric Corp | Graphic display device |
| CA2100322C (en) * | 1992-08-06 | 2004-06-22 | Christoph Eisenbarth | Method and apparatus for monitoring image processing operations |
| US5825786A (en) * | 1993-07-22 | 1998-10-20 | Texas Instruments Incorporated | Undersampling digital testability circuit |
| KR100513793B1 (en) * | 1998-03-30 | 2005-12-08 | 삼성전자주식회사 | Apparatus for making monitor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0009828B1 (en) * | 1978-10-11 | 1982-09-15 | Westinghouse Electric Corporation | Digital display exerciser |
| US4513318A (en) * | 1982-09-30 | 1985-04-23 | Allied Corporation | Programmable video test pattern generator for display systems |
| US4569049A (en) * | 1983-05-09 | 1986-02-04 | Digital Equipment Corp. | Diagnostic system for a digital computer |
| EP0132925B1 (en) * | 1983-06-30 | 1988-01-07 | Tektronix, Inc. | Diagnostic system for a raster scan type display device |
| US4663619A (en) * | 1985-04-08 | 1987-05-05 | Honeywell Inc. | Memory access modes for a video display generator |
-
1986
- 1986-03-18 CA CA000504431A patent/CA1254683A/en not_active Expired
- 1986-03-19 NO NO861057A patent/NO169926C/en not_active IP Right Cessation
- 1986-04-21 ZA ZA862964A patent/ZA862964B/en unknown
- 1986-05-05 AU AU57121/86A patent/AU579928B2/en not_active Ceased
- 1986-05-15 DE DE8686303691T patent/DE3682322D1/en not_active Expired - Fee Related
- 1986-05-15 EP EP86303691A patent/EP0202865B1/en not_active Expired - Lifetime
- 1986-05-16 JP JP61112458A patent/JPH0642132B2/en not_active Expired - Lifetime
-
1992
- 1992-01-09 SG SG23/92A patent/SG2392G/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| SG2392G (en) | 1992-03-20 |
| DE3682322D1 (en) | 1991-12-12 |
| ZA862964B (en) | 1986-12-30 |
| NO169926B (en) | 1992-05-11 |
| JPS61267087A (en) | 1986-11-26 |
| EP0202865A2 (en) | 1986-11-26 |
| NO861057L (en) | 1986-11-18 |
| AU579928B2 (en) | 1988-12-15 |
| EP0202865B1 (en) | 1991-11-06 |
| AU5712186A (en) | 1986-11-20 |
| JPH0642132B2 (en) | 1994-06-01 |
| NO169926C (en) | 1992-08-19 |
| EP0202865A3 (en) | 1988-09-14 |
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