CA1226954A - Control sequencer with dual microprogram counters for microdiagnostics - Google Patents
Control sequencer with dual microprogram counters for microdiagnosticsInfo
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- CA1226954A CA1226954A CA000479667A CA479667A CA1226954A CA 1226954 A CA1226954 A CA 1226954A CA 000479667 A CA000479667 A CA 000479667A CA 479667 A CA479667 A CA 479667A CA 1226954 A CA1226954 A CA 1226954A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Abstract of the Disclosure A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The micro-diagnostics comprise background and operability tests, the background tests being interleaved with macroinstruction operations under the control of the two independent micro-program counters. The background tests are run during processor idle time and the operability tests are executed at processor or turn-on. The organization of the micro-diagnostics into a hierarchical structure allows the use of the same microprogrammed test module for both the background and operability microdiagnostic tests. A prediction/residual coding technique provides fault detection for address and data information within the control sequencer.
Description
US
CONTROL SEQUENCER WITH DUAL MICROPROGRAM
COUNTERS FOR MICRO DIAGNOSTICS
"The Government has rights in this invention pursuant to Contract No. DAAK80-81-C-005~ awarded by the Department of the Army.
Background of the Invention This invention relates Jo an information processing system having self-test capability. More particularly, it relates to a digital computer system having micro diagnostic test routines that test hardware portions of a computer system in conjunction with Built-in Test BIT) hardware and macro-operability tests to provide detection and assist in isolation of a fault to a hardware module level.
Any information processing system and especially a digital computer system requires several levels of tests or diagnostics to ensure operability. Typical software tests exercise only a small fraction of a computer system during a given time period. Hardware supported test capability, otherwise referred to as BIT, provides an added measure of system lo tinge however, cost impact prohibits this from being the complete diagnostic solution.
BIT has teen achieved through three levels of activity, such as initial diagnQsti~st on-line KIT and off-line BIT.
Initial diagnostic programs may comprise microdiagnosti~s and operability test routines that are performed when a computer system is initially turned-on or is engaged in an initial program load. On-line BIT includes all of those areas of fault monitoring activity that take place while a computer is operating, such as self-checking hardware fault monitors which continuously monitor critical punk within a computer. Off-line BIT becomes necessary when an initial attempt at isolating a computer fault has failed requiring a more thorough testing procedure. By interfacing the computer under test to an external diagnostic exerciser via a maintenance port, off-line techniques such as Logic Scan Design (LSD), and Signature Analysis may be performed.
Logic Scan Design is a method of serially linXins internal hardware resulting in improved testability particularly of Large Scale Integration ELSIE logic design. The method arranges for all internal logic states to be held in registers that can be serially accessed, allowing the internal states to be observed and controlled After a repair is made, signature analysis involves the accumulation of thousands of internal test point sequences into one signature word which is read serially by the external diagnostic exerciser and checked for validity. The external diagnostic exerciser attempts to isolate a faulty module in a computer system by executing diagnostic routines while maintaining precise control over the internal state of the computer under test.
On-line BIT comprises the use of micro diagnostic test routines, 35~
stored in a microprogrammed control unit, not only at power turn-on but also during normal computer operations, thereby providing a means for detecting a failure much earlier than would be otherwise possible. However, prior art attempts to S employ micro diagnostics in a microprogrammed control unit have relied on forcing a computer or data processing system into an idle state of the system thereby terminating normal processing operations and have required significant amounts of additional dedicated hardware.
: .
it Summary of the Invention This invention discloses an information processing system having a microprogrammed control Uric which performs a background micro diagnostic microprogram during the operation of a foreground program. A memory stores a plurality of microinstruction for performing both the background microprogram and the foreground program. The microprogrammed control unit includes a control sequencer for independently controlling the foreground program operation and the background microprogram by using two micro-program counters wherein a first microprogram counter participates in performing the foreground program and a second microprogram counter controls the background micro-diagnostic microprogram without affecting the foreground lo program operation. The control sequencer further comprises a prediction/residual coding method for detecting micro-instruction address and data errors. In addition/ the background micro diagnostic microprogram comprises a plurality of test modules stored in the memory wherein each of the test modules test a particular portion of the information processing system and each of the test modules comprises a short cycle code for verification of the performance of each test module The invention further discloses a method for performing a background microprogram during the operation ox a I
foreground program in an information processing system having a microprogrammed control unit comprising the steps of storing a plurality of microinstruction for performing the back-ground microprogram and the foreground program and controlling independently the foreground program operation and the background microprogram with at least two micro-program counters wherein a first microprogram counter participates in performing the foreground program and a second microprogram counter controls the background micro-program.
The invention further discloses a method of performing failure detection in an information processing system having a microprogrammed control unit which performs a background microprogram during the operation of a foreground program comprising the steps of storing a plurality of micro-instructions for performing the background microprogram and the foreground program, each of said microins~ructions having a first code for verification of an address of each one of said microinstruction and the content of said address, controlling the foreground program and the back-ground microprogram with at least two microprogram counters, venerating a residual code from said first code represent Tut of a code for a current microinstruction address, generating and storing a second code for a next micro-instruction address during an immediate previously executed Jo I
microinstruction operation and comparing the residual code to the stored second code for detecting a failure.
I
. - 6 Brief Description of thy Drawings Other and further features and advantages of the invention will become apparent in connection with the . accompanying drawings wherein:
FIG 1 is a block diagram of a microprogrammed control unit having a control sequencer comprising two microprogram counters according to the present invention;
FIG 2 is a block diagram of an information processing system showing the control sequencer of FIG. 1 as part of a microprogrammed control unit;
Fig 3 is a block diagram of the hardware construction for implementing the two microprogram counters;
FIG. 4 is a functional block diagram showing the failure detection circuitry within the control sequencer for detecting lo microinstruction address and data errors.
FIG. 5 is a logic diagram of top control switch as shown in FIG. 1 for controlling the switching between the two microprogram counters shown in FIG. l;
FIG. 6 is a hierarchy chart of the micro diagnostic essay modules making up the operability micro diagnostic and the background micro diagnostics and showing the microprogrammed test modules shared by etch;
FIX;. 7 shows a sequence of test modules }or background micro diagnostic test and further shows a short cycle code which is generated by each test module and checked by a 7 _ I
succeeding test module;
FIG. 8 illustrates the switching from a foreground microprogram to a background micro diagnostic microprogram in order to execute three microinstruction prior to S returning to the foreground microprogram;
FIG. 9 shows a microinstruction address and the filets of a microinstruction word stored in the microinstruction address; and FIG. 10 illustrates a parity tree for the generation of a prediction/residual code utilized in the failure detection circuitry as shown in FIG, 4.
Description of the Preferred Embodiment , A significant improvement in information processing built-in-test (BIT) capability is achieved according to the present invention, as shown in FIG. l. This invention provides or the performance of on-line BIT micro diagnostic tests without interrupting a normally operating information processing system by the use of two independent microprogram counters, A first microprogram counter 24 participates in the operation of an operating foreground program that typically would be implementing a machine microinstruction and a second micro diagnostic microprogram counter I controls the performance of background microdia~nostic tests being performed simultaneously during idle time intervals of the microinstruction implementing the foreground program.
lo Macro programs are performed using standard machine macro instructions for performing a specific applications oriented task. A microprogram is controlled by a macro-program counter 81 according to the macro instructions stored in a memory unit 66. An operation code from a micron-struction obtained from memory unit 66 is coupled to mapping PROM 74 which determines a starting microinstruction address in control store 70 for the microprogram that will implement the microinstruction specified by said operation code The microprogram read from control store 70 is fed to control sequencer 76. Control sequencer 76 includes the two it microprogram counters 24 and 26 mentioned above. Thus, microprogram counter 24 generates the address of the next micro-instruction for the macro-instruction being performed by a foreground program of the information processing system 60 shown in FIG. 2.
Referring to FIG. 1, micro diagnostic microprogram counter 26 generates an address of a next micro diagnostic microinstruction during the performance of background micro-diagnostics which are run simultaneously with foreground macro programs during the processing system 60 idle machine times or during operability micro diagnostic testing which is executed at power turn on Operability micro diagnostics are executed in a sequential manner under the control of microprogram counter 24 with no foreground programs in 15. operation. Multiplexer 28 selects an output from either microprogram counter (MPC) 24 or micro diagnostic microprogram counter 26 in accordance with an address select 148 signal venerated by control switch 161 logic based on speci1c control bits of a microinstruction coupled to the control switch 161 from the control register 71 coupled to control Tory 70. The output of multiplexer 28 connect to an output address multiplexer 32~ The control witch 161 also generates the microprogram counter ~MPC) source select lS2 signal coupled to microprogram counter 24 and a background branch select 160 signal coupled to microdiagnosti microprogram counter 26 for switching between said micro-program counters 24 and 26 when the address of a next micro-instruction is being selected.
The output of microprogram counter 24 is also coupled to a microprogram stack 30. The microprogram stack 30 comprises a stack and associated stack pointer logic for handling microprogram interrupt subroutines The micro-program stack is an eighteen bit wide six level last-in/
first-out tLIFO) register used during stack PUSH and POP
operations. The stack pointer controls the stack operations by implementing a six state UP/DOWN counter with parity predict logic. Parity predict logic, normally used in con-junction with a counter, predicts the next state of parity after a clocked counter operation. The six level stack stores the current microprogram counter location and core-sponging code into a LIFO as determined by the stack pointer logic. PUSH operations store the microprogram counter; POP
operations move the selected LIFO location onto the stack output. The embodiment and operation of a microprogram stack is known to one skilled in the art.
The eighteen it output of the microprogram stack 30 connects to output address multiplexer 32 and microprogram counter 24. The other inputs to output address multiplexer 32 include an eighteen-bit word directly coupled from multi-plexer 28, an address jam 48 signal which causes the termination of the current microprogram flow by transferring control to a predetermined address in control store 70, source select 55 signals from a microinstruction read-out of control store 70 via control register 71 and an eighteen-bit word comprising a 13 bit address and a 5 bit code from a branch condition multiplexer 22. An address jam 48 signal immediately suspends the current micro diagnostic microprogram being performed, places the content of the foreground micro-program counter onto the stack 30 and forces the address of the control store 70 to a predetermined state. If a back-ground micro diagnostic is being executed, it is terminated, the background microprogram counter 26 is initialized to (0001)16, the mode is switched to foreground and the fore-ground microprogram counter 24 content is placid onto the top of the microprogram stack 30~ The output address multi plexer 32 selects a microinstruction address 50 for an entry point into a control store 70 from its various address inputs. A map enable 52 signal is also generated by the output address multiplexer I When a microinstruction address is generated by a mapping PROM 74, said address determines a microprogram entry address in control store 70.
A microinstruction word from control store 70 provides two control signals to the input of the control switch 161 which are switch 163 and INHIBIT 164, as shown in FIG. 5 and described hereinafter.
Still referring Jo FIG. 1, a controller 20 receives inputs from an internal data bus 40, the branch condition multiplexer 22 and function select 19 signals from the . control register 71. Controller 20 performs several logic functions for the control sequencer 76, such as decoding function select 19 codes and combining internal fault conditions into a single fault indication called fail 54.
The output of controller 20 connects to branch condition multiplexer 22 and microprogram stack 30 and provides decoded functions by specifying operations to be performed. The branch condition multiplexer 22 receives signals from controller 20, control register 71, branch conditions 42 and code checker 56 and proceeds to generate a branch address which is coupled to microprogram counter 24, micro diagnostic microprogram counter 26 and output address multiplexer 32.
Therefore, the source of a microinstruction address 50 may be from a branch condition, one of the microprogram counters 24 and 26l the microprogram stack 30 or an address jam 48 in addition to mapping PROM 74.
only one of the two microprogram count I 24 and 26 is available to the output address multiplexer 32 a a time, depending on which executive mode is in effect, background or foreground. In either case, the available micropr~ram counter it loaded at the end of a microoycle with the value of the microprogram address incremented by l, unless the executing micro cycle is in the process of switching execution modes. In this situation, the output address multiplexer 32 is forced to supply a microinstruction address to control store 70 from the microprogram counter about to take control, while the currently available but outgoing microprogram counter it loaded with the address that it had intended to supply to the output address multiplexer 32. This will be the address to which the microprogram will return when execution control is returned to the outgoing microprogram counter. The control sequencer 76 is told to switch between the microprogram counters 24 and 26 from the microprogram itself as a result of preprogramming. The address of the microinstruction to be executed next is soured prom the microprogram counter taking control, and the address 15- specified by a microinstruction source select field is routed into the outgoing microprogram counter Referring now to FIG. 2, there is shown a block diagram of the information processing system 60 comprising a control unit 62, an arithmetic unit 64, a memory unit Ç6 and an input/output unit 90. The control unit I and the arithmetic unit 64 combined form a central processor which interfaces with the memory unit 66 and input/output unit I via a system bus 89 comprising a system address bus 85 and a system data bus 87 .
Control unit 62 comprises control sequencer 76, as shown in FIG. 1 which provides a microinstruction address 50 to a memory or control store 70 as determined by inspection of microinstruction data, processor bus data, or several pro-determined status conditions within the central processor.
A next address decision is made once during each control sequencer system clock 106 cycle Each microinstruction or a microprogram specifies the source of the address of the next step of the microprogram. The output of control store 70 includes a control register 71 having i36 bits which make up a microinstruction word. An I x 24 bit mapping PROM 74, which i one of the several sources for a microinstruction address 50, translates operand codes and operand specifiers in the instruction stream from control register 71 or the internal data bus 40 into microinstruction addresses. A
built-in test/Maintenance Controller (MCKEE) 72 is provided in each module of Tao information processing system 60 for gathering built-in test BIT) data status information. Each MCKEE 72 reports the system BIT 73 status information to a system level bit maintenance device which although not shown could reside in the inpu~/output unit 90. Such a system level device determines which module or modules caused a fault eased on an analysis of all failure report an provides a fault indication.
Still referring to FIG. I arithmetic unit 64 comprises a register arithmetic logic unit ROWLEY) I which comprises a register array, including microprogram counter 81, (as shown in FIG. 1) a multifunction ALUM shift and sign extension logic and a variety of data paths. The function performed by the ROWLEY 80 are primarily determined by the MicroPro trammed control unit 62. The ROWLEY 80 is coupled to internal data bus 40 which is coupled to a system bus interface 88.
The ROWLEY is also coupled to a multiplier 78 which is used for extended prevision multiplications and for floating point operations. The embodiment of both an ROWLEY 80 and a multiplier 78 is readily known to one having ordinary skill in the art. The ROWLEY is also coupled to an Associative Registered Arithmetic Logic Unit (AUREOLE) 82 which functions as a memory management unit by associating a virtual address with virtual address bounds and then adding the appropriate relocation amount to the virtual address The AUREOLE 82 may be embodied with two discrete Aurelius wherein one AUREOLE stores the virtual address bounds and the relocation amounts are stored in the register of a second AUREOLE The first AUREOLE
subtracts the incoming virtual address from each of 16 virtual address bounds. While this subtraction is occurring, the second AUREOLE adds the incoming virtual address with each of the 16 relocation amounts. When the first AUREOLE
identifies the first virtual address bound, that is greater than or equal to the incoming virtual address, the entry position is sent to the second AUREOLE which then outputs the 6J' I
appropriate address to the system address bus 85.
Memory unit 66 comprises two 16K x 48 bit random access memories 100 and 102, but can be easily expanded. A memory address controller 96 connects between a system address bus S 85 and the memories 100 and 102; it performs all functions necessary for control of the memories 100 and 102. A first Rippler/Byte Aligned (RIB) 94 connects between the system data bus 87 and memory 100 and a second Rippler/Byte Aligned (ROB I connects between the system data bus 87 and memory 102. The RIB So and 9B are multifunction elements performing data alignment, byte and half word transfers, error detection and correction, Rippler error correction and bus interfacing.
c The Rippler error correction is performed by replacing with its nearest neighbor any defective memory devices in a linear lo array of identical devices, then, replacing that device with its nearest neighbor, etc. The whole process aripplesn down the array of sub elements until the last active device is replaced by the first available space The advantage of this switching method o'er the more conventional direct substitution approach is in its amenability to relatively simple and reliably implemented control algorithms. Dow-tonal details of a Rippler are disclosed in U. S. Patent No. 3l805,039 issued April 16, 1974 and assigned to the same assignee as the present invention.
An input output unit 90 comprises an I/O controller 91 ~%~ I
and an I/0 interface 92. The I/O controller 91 executes I/O instructions and generates appropriate interrupts for controlling various I/O ports. The I/O interface 92 comprises specific interfaces such as standard peripheral equipment, parallel or serial interfaces. In addition, the input/output unit 90 includes a priority interrupt network 84 for handling interrupts, a processor control register 86 for holding information relevant to the current state of the information processing system and a system bus interface 88 for providing system bus control, system bus arbitration in-struction prefetch control and storage and clock distribution and control.
Referring now to FIG. 3, a logic embodiment for the background microprogram counter 24 and the background micro-diagnostic microprogram counter 25 is shown. microprogram counter 24 comprises a 4/1 multiplexer 120 connected to a 13 bit register 124 which stores a microinstruction address.
Al o, a 4~1 multiplexer 122 is kinked to a 3 bit register 12~ for storing a microprogram counter code for detecting addressing error The 5 bit microprogram counter code is generated by code generator 142 as a function of the 13 bit microinstruction address The generated cod it compared in code checker 56, as shown in FIG.. 1 and FIG 4, TV an equivalent code extracted from microcode bit which come into the control sequencer 76 from the control resister 71 in order to check the control store 70 to the control sequencer 76 address patio Microprogram counter 24 also receives an address from the stack address 154 lines and an associated stack code 158 is provided for the microprogram counter code register 126.
The background micro diagnostic microprogram counter 26 comprises a 2/1 multiplexer 132 connected to a 13 bit register 136 for storing a microinstruction address and a 2/1 multi-plexer 134 connected to a 5 bit register 138 for storing a S
bit microprogram counter code. A microinstruction address 50 is incremented by address incremented 140 prior to being stored in register 124 or register 13~. Code generator 142 generates a microprogram counter code associated with a microinstruction address and described hereinafter in regard to FIG. 4, The foreground microprogram counter 24 receives an address via the multi-way branch address lS0 lines, the stack 154 lines or the microinstruction address So lines when grated by an MPC source select 152 signal. The back-ground micro diagnostic microprogram counter 26 receives an address via the microinstruction address 50 lines or the multi-way branch address 150 line when grated by a background branch select 160 signal. When a micro diagnostic abort condition occurs, a DIAGABO~T 44 signal generated by an address jam 48, as shown in FIG. 5, causing control to be transpired to the foreground microprogram counts 24. The go address select 148 signal selects whether a program counter address 144 and its associated program counter code 143 comes from the foreground microprogram counter 24 or the background micro diagnostic microprogram counter 26. The integrated circuits required to implement the logical functions shown in FIG. 3 are known to one of ordinary skill in the art.
Referring now to FIGS. 4, 3 and 10, the failure detection circuits for detecting microinstruction address and data errors in the control sequencer 76 by a prediction/residual code method are shown. A cyclic pen y code it generated by exclusive Owing the data bits within a particular micro-instruction address, in the next address 103 field, the control field 104 and the microinstruction address itself, as shown in FIGS. 9 and 10, and the resulting cyclic parity code is placed in the code 105 field of the microinstruction.
Logic within code checker 56 removes the contributions to this code of the next address 103 and control field 104.
Encoder 107 connected to exclusive OR 10~ removes the next address 1~3 field contribution and encoder 10~ connected to exclusive OR 110 removes the control field 104 contribution, thereby presenting at the output of exclusive OR 110 a residual code which is a check on the current micron-struction address A predicted code for the current micro-instruction address was previously stored in code register 113. Therefore, exclusive OR 111 essentially performs a comparison between the predicted code and the residual code at its inputs and if the outputs of exclusive ox 111 which is connected to zero detector 112 is other than zero, FAIL
54 signal is generated. The previous microinstruction loaded code register 113 with the predicted code for the next address which by definition has to be identical Jo the residual code generated at the output of exclusive OR 110.
The proper loading of code register 113 is controlled by a control sequencer clock 106 signal.
The branch condition multiplexer 22 receives a 13 bit next address 103 from control register 71 and an associated 5 bit code from encoder 107 for properly handling branching situations when the next microinstruction address 50 is not to be soured from one of the microprogram counters 24 and 26. The output address multiplexer 32, as previously described selects the source for the next microinstruction 50 and the associated predicted code is sent to cod register 113.
The prediction/residual code failure detection method verifies that data from the control store pa via control register 71 was read correctly, that no failure occurred in any address lines of the control store 70, thaw there was no single data error in the control store output and that no data path error occurred between the control store 70 and the control sequencer 76~
Referring now to FIG. 5, the micro diagnostic control switch 161 is crown. Two microinstruction signals called switch 163 and INHIBIT 164 from the control store 70-control S the operation of the control switch 161. Both signals have to be asserted to affect a switching operation. One of the signals INHIBIT 164 is used to inhibit the switching of modes (background and foreground). The I2iHIBIT signal is used when executing background diagnostics via the foreground microprogram counter by off-line testing and operability micro diagnostics. The D flip flop 168 generates the micro-diagnostic enable 171 signal and thus initiates action for microprogram counter selection. AND gala 165 allows the toggling of D flip flop 168 if INHIBIT is a logic 0. NOR
gate 166 gates the control sequencer clock foe to the D flip flop 168 via AND gate 167. If an address jam 48 signal is activated when the background mode is enabled, flip flop 168 is set) the DIAGABORT 44 signal becomes active (logic 1) causing the flip flop 168 to be reset, a termination of the background microprogram (background microprogram counter 26 is initialized) and transfer of the control sequencer to the foreground mode prior to execution of an address jam sequence.
Further flexibility is provided by allowing the micro-diagnostic enable 171 to be used as a branch condition and identify whether background micro diagnostic or operability - I -micro diagnostic testing is in progress.
Still referring to FIG 5, this control switch 161 is automatically transferred to foreground operation if an address jam 48 occurs during execution of background micro-diagnostics. This condition generates the DIAGA80RT 44 signal which is used to initialize the background micro-program counter to (0001)16 and force a background micro-diagnostic routine to restart The AND gate 165 output, micro diagnostic enable 171 and the address jam 48 along with TRUE 21 from the branch condition multiplexer 22 and source select 55 from the control register 71 are inputs to a decoder 169 which develops four outputs to control the microprogram ! counters 24 and 26 and multiplexer 28. Background branch select 160 controls loading of the background microdiagno.tic microprogram counter 26, the MPC source select 152 controls the loading of the foreground microprogram counter, and the address select 14~ signal selects either the foreground micro-program counter or background micro diagnostic microprogram counter and associated microprogram counter cod via the multiplexer 28.
Micro diagnostic test microcode routines utilized in conjunction with BIT hardware and a macro-operability jests provide fault detection and assist in Allah ovation to a module hardware level The MicroPro try tests are performed after micro diagnostic tests are used to ascertain ~22~
the fundamental operability of an information processing system. Micro diagnostics can be subdivided into operability micro diagnostics and background micro diagnostics. The operability micro diagnostics support the macro-operability tests and are performed during initial power-up of a system by testing hardware circuitry that would prevent the execution of the first macro-operability instruction if faulty. Operability microdiaynostics and background micro-diagnostics work together towards attaining a high percentage of fault detection and to assist in fault isolation by testing circuitry which is either untestable or inefficient to test using BIT hardware exclusively.
Referring now to FIG. 6, the organization of the micro-diagnostics as a hierarchy structure is shown. Each box in Fig 6 represents a microprogrammed test module and may be either a control or a test module. Control modules consist of two or more call instructions and a return instruction.
A control module will call either a subordinate control module or a test module Test modules explicitly test functional hardware areas of the information processing system 60. Examples of control modules are the executive 178 operability micrsdiagnostics 180 and background micro-diagnostics 181. The background micro diagnostics 181 are comprised entirely of test modules such as OWE 186, control sequencer 187~ floating point 188, registered arithmetic 95~
logic unit 189 and register 190 modules. The micro diagnostics art designed so that operability micro diagnostics 180 and background micro diagnostics 181 share microprogrammed test modules or common microinstruction code as indicated in FIG.
6. A fault 182 module is called by the microprogram when a failure is detected. The object of the fault 182 module is to establish a stable system state (i.e. jump to self) and alert the BIT maintenance controller 72 of the failure.
Each functional test module has a short cycle code specified for that function The code is generated in one module and passed as a parameter to the next module The next module will, upon program entry, test the passed short cycle code value and if wrong, BIT hardware will be notified of a fault The short cycle code is generated by incrementing the passed code with a constant. Short cycle code is tested when performing background micro diagnostics 181 and operability micro diagnostics lay.
A complete operability micro diagnostic test sequence comprises performing all of the test modules shown in FIG. 6 comprising system bus interface 183, priority interrupt network 184, RAM lay, ROM 186, control sequencer 187, floating point 188, and registered arithmetic logic unit 189~ A complete sequence ox background micro diagnostics comprises performing the following test modules. TOM 186, control sequencer 187, Lang point 188 J registered I
arithmetic logic unit 189 and register 190. The ROM 186, control sequencer 187, floating point 188 and registered arithmetic logic unit 189 test modules are the same test modules for both operability micro diagnostics 180 and back-S ground micro diagnostics 181, which minimizes the amount of control swore 70 that is required.
The operability microdiagnos~ics 180 support assembly language macro-operability tests (software tests performed immediately following an initial program load and power-up of an information processing system by testing circuitry that would prevent the execution of the first macro-operability instruction. The operability micro diagnostics 180 will not preserve the previous state of an information processing system, and assumes that the hardware hard core (minimal amount of circuitry required to start the first micro diagnostic test) is operational. The operability micro diagnostic sly build on that hard core by testing additional circuitry until all required ~estinq is completed, they are performed under the control of the fo~egrQund micro-program counter 24. After completion ox the operability micro diagnostics, the assembly language macrQ-operability test is executed The background micro diagnostics 181 are performed during processor idle machine times, The control sequencer 76 of a US microprogrammed control unit 62 comprises two microprogram Jo ~2~4 counters 24 and 26, as previously described, which work simultaneously during execution of assembly language programs. Since the background micro diagnostic tests are executed during idle machine times employing the background microprogram counter 26, these tests are transparent (tummies) to any user programs. The background micro-diagnostics are executed three microinstruction at a time, as illustrated in FIG. 8, to allow more complete testing.
FIG. 8 shows a control store 70 comprising a foreground microprogram for implementing a microinstruction A and comprising micro diagnostic test modules B and C. During the execution of microinstruction An at time tnf two control signals from said microinstruction An cause program control to switch to the background microprogram counter 26 whereby, in this illustration, micro diagnostic test module B is executed three instructions at a time. At the conclusion of the third microinstruction (By) program control is switched back to the foreground microprogram counter 24 and the execution of microinstruction on is completed. The back-ground micro diagnostics 181, due to the nature of their execution, do not change the state of a computer system or an information processing system 60. The intent of background micro diagnostics 181 is to continually exercise functions not tested by on-line BIT and to alert a bit maintenance controller 72, as shown in FIG. 2, upon detection of a fault.
The idle times during which background micro diagnostics 181 are executed include periods where a memory access does not overlap micro code execution or when a processor must wait for another operation to be completed. Also, certain instructions have periods of inactivity (wait state) and additionally, a periodic time-out every millisecond may be used to ensure failsafe operation of background micro-diagnostics Referring now to FIGS. 1 and 2, the method of operation of micro diagnostics is as follows: assume that the foreground microprogram counter 24 is being used to execute a string of microinstruction to implement a machine eye rut or an instruction set architecture (IS) operation which requires a fetch from memory unit 66. The memory fetch is initiated and the processor comprising control unit 62 and arithmetic unit 64 begins waiting for the system data bus 87 to present valid data. Jointly with the initiation of the memory fetch, the IS operation Roy eye transfers control to the background microprogram counter 26 by means of the control switch 161. The control sequencer I is thereby switched to a background mode and a background micro-diagnostic test controlled by the microdiaqnostic microprogram mounter 26 execute three microinstruction Blue By and By, as shown in FIG 8, from one of the test modules shown in FIG. 6. At the conclusion of the execution of the third ~L~2Ç~
microinstruction, the micro diagnostic test generates control signals (SWITCH 163 and INHIBIT 164 to cause a swap micro-program counter action which transfers control back to the foreground microprogram counter 24. This procedure continues until all test modules making up a micro diagnostic test are completed.
Micro diagnostic tests in the background mode do not alter the operational state of the processor and avoid exercising any state which could effect IS execution such as general purpose flags, data registers or overflow). The foreground mode of operation is not aware of the execution of background mode micro diagnostics.
! Referring now to FIG. 7, a typical background micro-diagnostic program sequence is shown comprising control sequencer 187, registered arithmetic logic unit 1~9, floating point 188 and register 190 test modules. The name of a test module indicates the functional area of a system being tested.
Each test module generates a short cycle code SAC When background mode microdiagno tics are enabled and a new functional test module is entered, the short cycle code generated by the previous test module is passed as a parameter to the next module in the execution sequence and checked. If the passed code is determined to be wrong, BIT
hardware is notified of a fault. Short cycle code is tested in both operability end background micro diagnostic lo is.
I
This short cycle code guarantees that a complete micro-diagnostic sequence of test modules is executed and not just a subset of test modules due to a latency failure. The principal reason for performing background micro diagnostics is to reduce failure latency time or the time it takes to discover a failure condition.
This concludes the description of the preferred embodiment. However, many modifications and alterations will be obvious to one of ordinary skill in the art without departing from the spirit and scope of the inventive concept.
Therefore, it is intended that the scope of this invention be limited only by the appended claims.
CONTROL SEQUENCER WITH DUAL MICROPROGRAM
COUNTERS FOR MICRO DIAGNOSTICS
"The Government has rights in this invention pursuant to Contract No. DAAK80-81-C-005~ awarded by the Department of the Army.
Background of the Invention This invention relates Jo an information processing system having self-test capability. More particularly, it relates to a digital computer system having micro diagnostic test routines that test hardware portions of a computer system in conjunction with Built-in Test BIT) hardware and macro-operability tests to provide detection and assist in isolation of a fault to a hardware module level.
Any information processing system and especially a digital computer system requires several levels of tests or diagnostics to ensure operability. Typical software tests exercise only a small fraction of a computer system during a given time period. Hardware supported test capability, otherwise referred to as BIT, provides an added measure of system lo tinge however, cost impact prohibits this from being the complete diagnostic solution.
BIT has teen achieved through three levels of activity, such as initial diagnQsti~st on-line KIT and off-line BIT.
Initial diagnostic programs may comprise microdiagnosti~s and operability test routines that are performed when a computer system is initially turned-on or is engaged in an initial program load. On-line BIT includes all of those areas of fault monitoring activity that take place while a computer is operating, such as self-checking hardware fault monitors which continuously monitor critical punk within a computer. Off-line BIT becomes necessary when an initial attempt at isolating a computer fault has failed requiring a more thorough testing procedure. By interfacing the computer under test to an external diagnostic exerciser via a maintenance port, off-line techniques such as Logic Scan Design (LSD), and Signature Analysis may be performed.
Logic Scan Design is a method of serially linXins internal hardware resulting in improved testability particularly of Large Scale Integration ELSIE logic design. The method arranges for all internal logic states to be held in registers that can be serially accessed, allowing the internal states to be observed and controlled After a repair is made, signature analysis involves the accumulation of thousands of internal test point sequences into one signature word which is read serially by the external diagnostic exerciser and checked for validity. The external diagnostic exerciser attempts to isolate a faulty module in a computer system by executing diagnostic routines while maintaining precise control over the internal state of the computer under test.
On-line BIT comprises the use of micro diagnostic test routines, 35~
stored in a microprogrammed control unit, not only at power turn-on but also during normal computer operations, thereby providing a means for detecting a failure much earlier than would be otherwise possible. However, prior art attempts to S employ micro diagnostics in a microprogrammed control unit have relied on forcing a computer or data processing system into an idle state of the system thereby terminating normal processing operations and have required significant amounts of additional dedicated hardware.
: .
it Summary of the Invention This invention discloses an information processing system having a microprogrammed control Uric which performs a background micro diagnostic microprogram during the operation of a foreground program. A memory stores a plurality of microinstruction for performing both the background microprogram and the foreground program. The microprogrammed control unit includes a control sequencer for independently controlling the foreground program operation and the background microprogram by using two micro-program counters wherein a first microprogram counter participates in performing the foreground program and a second microprogram counter controls the background micro-diagnostic microprogram without affecting the foreground lo program operation. The control sequencer further comprises a prediction/residual coding method for detecting micro-instruction address and data errors. In addition/ the background micro diagnostic microprogram comprises a plurality of test modules stored in the memory wherein each of the test modules test a particular portion of the information processing system and each of the test modules comprises a short cycle code for verification of the performance of each test module The invention further discloses a method for performing a background microprogram during the operation ox a I
foreground program in an information processing system having a microprogrammed control unit comprising the steps of storing a plurality of microinstruction for performing the back-ground microprogram and the foreground program and controlling independently the foreground program operation and the background microprogram with at least two micro-program counters wherein a first microprogram counter participates in performing the foreground program and a second microprogram counter controls the background micro-program.
The invention further discloses a method of performing failure detection in an information processing system having a microprogrammed control unit which performs a background microprogram during the operation of a foreground program comprising the steps of storing a plurality of micro-instructions for performing the background microprogram and the foreground program, each of said microins~ructions having a first code for verification of an address of each one of said microinstruction and the content of said address, controlling the foreground program and the back-ground microprogram with at least two microprogram counters, venerating a residual code from said first code represent Tut of a code for a current microinstruction address, generating and storing a second code for a next micro-instruction address during an immediate previously executed Jo I
microinstruction operation and comparing the residual code to the stored second code for detecting a failure.
I
. - 6 Brief Description of thy Drawings Other and further features and advantages of the invention will become apparent in connection with the . accompanying drawings wherein:
FIG 1 is a block diagram of a microprogrammed control unit having a control sequencer comprising two microprogram counters according to the present invention;
FIG 2 is a block diagram of an information processing system showing the control sequencer of FIG. 1 as part of a microprogrammed control unit;
Fig 3 is a block diagram of the hardware construction for implementing the two microprogram counters;
FIG. 4 is a functional block diagram showing the failure detection circuitry within the control sequencer for detecting lo microinstruction address and data errors.
FIG. 5 is a logic diagram of top control switch as shown in FIG. 1 for controlling the switching between the two microprogram counters shown in FIG. l;
FIG. 6 is a hierarchy chart of the micro diagnostic essay modules making up the operability micro diagnostic and the background micro diagnostics and showing the microprogrammed test modules shared by etch;
FIX;. 7 shows a sequence of test modules }or background micro diagnostic test and further shows a short cycle code which is generated by each test module and checked by a 7 _ I
succeeding test module;
FIG. 8 illustrates the switching from a foreground microprogram to a background micro diagnostic microprogram in order to execute three microinstruction prior to S returning to the foreground microprogram;
FIG. 9 shows a microinstruction address and the filets of a microinstruction word stored in the microinstruction address; and FIG. 10 illustrates a parity tree for the generation of a prediction/residual code utilized in the failure detection circuitry as shown in FIG, 4.
Description of the Preferred Embodiment , A significant improvement in information processing built-in-test (BIT) capability is achieved according to the present invention, as shown in FIG. l. This invention provides or the performance of on-line BIT micro diagnostic tests without interrupting a normally operating information processing system by the use of two independent microprogram counters, A first microprogram counter 24 participates in the operation of an operating foreground program that typically would be implementing a machine microinstruction and a second micro diagnostic microprogram counter I controls the performance of background microdia~nostic tests being performed simultaneously during idle time intervals of the microinstruction implementing the foreground program.
lo Macro programs are performed using standard machine macro instructions for performing a specific applications oriented task. A microprogram is controlled by a macro-program counter 81 according to the macro instructions stored in a memory unit 66. An operation code from a micron-struction obtained from memory unit 66 is coupled to mapping PROM 74 which determines a starting microinstruction address in control store 70 for the microprogram that will implement the microinstruction specified by said operation code The microprogram read from control store 70 is fed to control sequencer 76. Control sequencer 76 includes the two it microprogram counters 24 and 26 mentioned above. Thus, microprogram counter 24 generates the address of the next micro-instruction for the macro-instruction being performed by a foreground program of the information processing system 60 shown in FIG. 2.
Referring to FIG. 1, micro diagnostic microprogram counter 26 generates an address of a next micro diagnostic microinstruction during the performance of background micro-diagnostics which are run simultaneously with foreground macro programs during the processing system 60 idle machine times or during operability micro diagnostic testing which is executed at power turn on Operability micro diagnostics are executed in a sequential manner under the control of microprogram counter 24 with no foreground programs in 15. operation. Multiplexer 28 selects an output from either microprogram counter (MPC) 24 or micro diagnostic microprogram counter 26 in accordance with an address select 148 signal venerated by control switch 161 logic based on speci1c control bits of a microinstruction coupled to the control switch 161 from the control register 71 coupled to control Tory 70. The output of multiplexer 28 connect to an output address multiplexer 32~ The control witch 161 also generates the microprogram counter ~MPC) source select lS2 signal coupled to microprogram counter 24 and a background branch select 160 signal coupled to microdiagnosti microprogram counter 26 for switching between said micro-program counters 24 and 26 when the address of a next micro-instruction is being selected.
The output of microprogram counter 24 is also coupled to a microprogram stack 30. The microprogram stack 30 comprises a stack and associated stack pointer logic for handling microprogram interrupt subroutines The micro-program stack is an eighteen bit wide six level last-in/
first-out tLIFO) register used during stack PUSH and POP
operations. The stack pointer controls the stack operations by implementing a six state UP/DOWN counter with parity predict logic. Parity predict logic, normally used in con-junction with a counter, predicts the next state of parity after a clocked counter operation. The six level stack stores the current microprogram counter location and core-sponging code into a LIFO as determined by the stack pointer logic. PUSH operations store the microprogram counter; POP
operations move the selected LIFO location onto the stack output. The embodiment and operation of a microprogram stack is known to one skilled in the art.
The eighteen it output of the microprogram stack 30 connects to output address multiplexer 32 and microprogram counter 24. The other inputs to output address multiplexer 32 include an eighteen-bit word directly coupled from multi-plexer 28, an address jam 48 signal which causes the termination of the current microprogram flow by transferring control to a predetermined address in control store 70, source select 55 signals from a microinstruction read-out of control store 70 via control register 71 and an eighteen-bit word comprising a 13 bit address and a 5 bit code from a branch condition multiplexer 22. An address jam 48 signal immediately suspends the current micro diagnostic microprogram being performed, places the content of the foreground micro-program counter onto the stack 30 and forces the address of the control store 70 to a predetermined state. If a back-ground micro diagnostic is being executed, it is terminated, the background microprogram counter 26 is initialized to (0001)16, the mode is switched to foreground and the fore-ground microprogram counter 24 content is placid onto the top of the microprogram stack 30~ The output address multi plexer 32 selects a microinstruction address 50 for an entry point into a control store 70 from its various address inputs. A map enable 52 signal is also generated by the output address multiplexer I When a microinstruction address is generated by a mapping PROM 74, said address determines a microprogram entry address in control store 70.
A microinstruction word from control store 70 provides two control signals to the input of the control switch 161 which are switch 163 and INHIBIT 164, as shown in FIG. 5 and described hereinafter.
Still referring Jo FIG. 1, a controller 20 receives inputs from an internal data bus 40, the branch condition multiplexer 22 and function select 19 signals from the . control register 71. Controller 20 performs several logic functions for the control sequencer 76, such as decoding function select 19 codes and combining internal fault conditions into a single fault indication called fail 54.
The output of controller 20 connects to branch condition multiplexer 22 and microprogram stack 30 and provides decoded functions by specifying operations to be performed. The branch condition multiplexer 22 receives signals from controller 20, control register 71, branch conditions 42 and code checker 56 and proceeds to generate a branch address which is coupled to microprogram counter 24, micro diagnostic microprogram counter 26 and output address multiplexer 32.
Therefore, the source of a microinstruction address 50 may be from a branch condition, one of the microprogram counters 24 and 26l the microprogram stack 30 or an address jam 48 in addition to mapping PROM 74.
only one of the two microprogram count I 24 and 26 is available to the output address multiplexer 32 a a time, depending on which executive mode is in effect, background or foreground. In either case, the available micropr~ram counter it loaded at the end of a microoycle with the value of the microprogram address incremented by l, unless the executing micro cycle is in the process of switching execution modes. In this situation, the output address multiplexer 32 is forced to supply a microinstruction address to control store 70 from the microprogram counter about to take control, while the currently available but outgoing microprogram counter it loaded with the address that it had intended to supply to the output address multiplexer 32. This will be the address to which the microprogram will return when execution control is returned to the outgoing microprogram counter. The control sequencer 76 is told to switch between the microprogram counters 24 and 26 from the microprogram itself as a result of preprogramming. The address of the microinstruction to be executed next is soured prom the microprogram counter taking control, and the address 15- specified by a microinstruction source select field is routed into the outgoing microprogram counter Referring now to FIG. 2, there is shown a block diagram of the information processing system 60 comprising a control unit 62, an arithmetic unit 64, a memory unit Ç6 and an input/output unit 90. The control unit I and the arithmetic unit 64 combined form a central processor which interfaces with the memory unit 66 and input/output unit I via a system bus 89 comprising a system address bus 85 and a system data bus 87 .
Control unit 62 comprises control sequencer 76, as shown in FIG. 1 which provides a microinstruction address 50 to a memory or control store 70 as determined by inspection of microinstruction data, processor bus data, or several pro-determined status conditions within the central processor.
A next address decision is made once during each control sequencer system clock 106 cycle Each microinstruction or a microprogram specifies the source of the address of the next step of the microprogram. The output of control store 70 includes a control register 71 having i36 bits which make up a microinstruction word. An I x 24 bit mapping PROM 74, which i one of the several sources for a microinstruction address 50, translates operand codes and operand specifiers in the instruction stream from control register 71 or the internal data bus 40 into microinstruction addresses. A
built-in test/Maintenance Controller (MCKEE) 72 is provided in each module of Tao information processing system 60 for gathering built-in test BIT) data status information. Each MCKEE 72 reports the system BIT 73 status information to a system level bit maintenance device which although not shown could reside in the inpu~/output unit 90. Such a system level device determines which module or modules caused a fault eased on an analysis of all failure report an provides a fault indication.
Still referring to FIG. I arithmetic unit 64 comprises a register arithmetic logic unit ROWLEY) I which comprises a register array, including microprogram counter 81, (as shown in FIG. 1) a multifunction ALUM shift and sign extension logic and a variety of data paths. The function performed by the ROWLEY 80 are primarily determined by the MicroPro trammed control unit 62. The ROWLEY 80 is coupled to internal data bus 40 which is coupled to a system bus interface 88.
The ROWLEY is also coupled to a multiplier 78 which is used for extended prevision multiplications and for floating point operations. The embodiment of both an ROWLEY 80 and a multiplier 78 is readily known to one having ordinary skill in the art. The ROWLEY is also coupled to an Associative Registered Arithmetic Logic Unit (AUREOLE) 82 which functions as a memory management unit by associating a virtual address with virtual address bounds and then adding the appropriate relocation amount to the virtual address The AUREOLE 82 may be embodied with two discrete Aurelius wherein one AUREOLE stores the virtual address bounds and the relocation amounts are stored in the register of a second AUREOLE The first AUREOLE
subtracts the incoming virtual address from each of 16 virtual address bounds. While this subtraction is occurring, the second AUREOLE adds the incoming virtual address with each of the 16 relocation amounts. When the first AUREOLE
identifies the first virtual address bound, that is greater than or equal to the incoming virtual address, the entry position is sent to the second AUREOLE which then outputs the 6J' I
appropriate address to the system address bus 85.
Memory unit 66 comprises two 16K x 48 bit random access memories 100 and 102, but can be easily expanded. A memory address controller 96 connects between a system address bus S 85 and the memories 100 and 102; it performs all functions necessary for control of the memories 100 and 102. A first Rippler/Byte Aligned (RIB) 94 connects between the system data bus 87 and memory 100 and a second Rippler/Byte Aligned (ROB I connects between the system data bus 87 and memory 102. The RIB So and 9B are multifunction elements performing data alignment, byte and half word transfers, error detection and correction, Rippler error correction and bus interfacing.
c The Rippler error correction is performed by replacing with its nearest neighbor any defective memory devices in a linear lo array of identical devices, then, replacing that device with its nearest neighbor, etc. The whole process aripplesn down the array of sub elements until the last active device is replaced by the first available space The advantage of this switching method o'er the more conventional direct substitution approach is in its amenability to relatively simple and reliably implemented control algorithms. Dow-tonal details of a Rippler are disclosed in U. S. Patent No. 3l805,039 issued April 16, 1974 and assigned to the same assignee as the present invention.
An input output unit 90 comprises an I/O controller 91 ~%~ I
and an I/0 interface 92. The I/O controller 91 executes I/O instructions and generates appropriate interrupts for controlling various I/O ports. The I/O interface 92 comprises specific interfaces such as standard peripheral equipment, parallel or serial interfaces. In addition, the input/output unit 90 includes a priority interrupt network 84 for handling interrupts, a processor control register 86 for holding information relevant to the current state of the information processing system and a system bus interface 88 for providing system bus control, system bus arbitration in-struction prefetch control and storage and clock distribution and control.
Referring now to FIG. 3, a logic embodiment for the background microprogram counter 24 and the background micro-diagnostic microprogram counter 25 is shown. microprogram counter 24 comprises a 4/1 multiplexer 120 connected to a 13 bit register 124 which stores a microinstruction address.
Al o, a 4~1 multiplexer 122 is kinked to a 3 bit register 12~ for storing a microprogram counter code for detecting addressing error The 5 bit microprogram counter code is generated by code generator 142 as a function of the 13 bit microinstruction address The generated cod it compared in code checker 56, as shown in FIG.. 1 and FIG 4, TV an equivalent code extracted from microcode bit which come into the control sequencer 76 from the control resister 71 in order to check the control store 70 to the control sequencer 76 address patio Microprogram counter 24 also receives an address from the stack address 154 lines and an associated stack code 158 is provided for the microprogram counter code register 126.
The background micro diagnostic microprogram counter 26 comprises a 2/1 multiplexer 132 connected to a 13 bit register 136 for storing a microinstruction address and a 2/1 multi-plexer 134 connected to a 5 bit register 138 for storing a S
bit microprogram counter code. A microinstruction address 50 is incremented by address incremented 140 prior to being stored in register 124 or register 13~. Code generator 142 generates a microprogram counter code associated with a microinstruction address and described hereinafter in regard to FIG. 4, The foreground microprogram counter 24 receives an address via the multi-way branch address lS0 lines, the stack 154 lines or the microinstruction address So lines when grated by an MPC source select 152 signal. The back-ground micro diagnostic microprogram counter 26 receives an address via the microinstruction address 50 lines or the multi-way branch address 150 line when grated by a background branch select 160 signal. When a micro diagnostic abort condition occurs, a DIAGABO~T 44 signal generated by an address jam 48, as shown in FIG. 5, causing control to be transpired to the foreground microprogram counts 24. The go address select 148 signal selects whether a program counter address 144 and its associated program counter code 143 comes from the foreground microprogram counter 24 or the background micro diagnostic microprogram counter 26. The integrated circuits required to implement the logical functions shown in FIG. 3 are known to one of ordinary skill in the art.
Referring now to FIGS. 4, 3 and 10, the failure detection circuits for detecting microinstruction address and data errors in the control sequencer 76 by a prediction/residual code method are shown. A cyclic pen y code it generated by exclusive Owing the data bits within a particular micro-instruction address, in the next address 103 field, the control field 104 and the microinstruction address itself, as shown in FIGS. 9 and 10, and the resulting cyclic parity code is placed in the code 105 field of the microinstruction.
Logic within code checker 56 removes the contributions to this code of the next address 103 and control field 104.
Encoder 107 connected to exclusive OR 10~ removes the next address 1~3 field contribution and encoder 10~ connected to exclusive OR 110 removes the control field 104 contribution, thereby presenting at the output of exclusive OR 110 a residual code which is a check on the current micron-struction address A predicted code for the current micro-instruction address was previously stored in code register 113. Therefore, exclusive OR 111 essentially performs a comparison between the predicted code and the residual code at its inputs and if the outputs of exclusive ox 111 which is connected to zero detector 112 is other than zero, FAIL
54 signal is generated. The previous microinstruction loaded code register 113 with the predicted code for the next address which by definition has to be identical Jo the residual code generated at the output of exclusive OR 110.
The proper loading of code register 113 is controlled by a control sequencer clock 106 signal.
The branch condition multiplexer 22 receives a 13 bit next address 103 from control register 71 and an associated 5 bit code from encoder 107 for properly handling branching situations when the next microinstruction address 50 is not to be soured from one of the microprogram counters 24 and 26. The output address multiplexer 32, as previously described selects the source for the next microinstruction 50 and the associated predicted code is sent to cod register 113.
The prediction/residual code failure detection method verifies that data from the control store pa via control register 71 was read correctly, that no failure occurred in any address lines of the control store 70, thaw there was no single data error in the control store output and that no data path error occurred between the control store 70 and the control sequencer 76~
Referring now to FIG. 5, the micro diagnostic control switch 161 is crown. Two microinstruction signals called switch 163 and INHIBIT 164 from the control store 70-control S the operation of the control switch 161. Both signals have to be asserted to affect a switching operation. One of the signals INHIBIT 164 is used to inhibit the switching of modes (background and foreground). The I2iHIBIT signal is used when executing background diagnostics via the foreground microprogram counter by off-line testing and operability micro diagnostics. The D flip flop 168 generates the micro-diagnostic enable 171 signal and thus initiates action for microprogram counter selection. AND gala 165 allows the toggling of D flip flop 168 if INHIBIT is a logic 0. NOR
gate 166 gates the control sequencer clock foe to the D flip flop 168 via AND gate 167. If an address jam 48 signal is activated when the background mode is enabled, flip flop 168 is set) the DIAGABORT 44 signal becomes active (logic 1) causing the flip flop 168 to be reset, a termination of the background microprogram (background microprogram counter 26 is initialized) and transfer of the control sequencer to the foreground mode prior to execution of an address jam sequence.
Further flexibility is provided by allowing the micro-diagnostic enable 171 to be used as a branch condition and identify whether background micro diagnostic or operability - I -micro diagnostic testing is in progress.
Still referring to FIG 5, this control switch 161 is automatically transferred to foreground operation if an address jam 48 occurs during execution of background micro-diagnostics. This condition generates the DIAGA80RT 44 signal which is used to initialize the background micro-program counter to (0001)16 and force a background micro-diagnostic routine to restart The AND gate 165 output, micro diagnostic enable 171 and the address jam 48 along with TRUE 21 from the branch condition multiplexer 22 and source select 55 from the control register 71 are inputs to a decoder 169 which develops four outputs to control the microprogram ! counters 24 and 26 and multiplexer 28. Background branch select 160 controls loading of the background microdiagno.tic microprogram counter 26, the MPC source select 152 controls the loading of the foreground microprogram counter, and the address select 14~ signal selects either the foreground micro-program counter or background micro diagnostic microprogram counter and associated microprogram counter cod via the multiplexer 28.
Micro diagnostic test microcode routines utilized in conjunction with BIT hardware and a macro-operability jests provide fault detection and assist in Allah ovation to a module hardware level The MicroPro try tests are performed after micro diagnostic tests are used to ascertain ~22~
the fundamental operability of an information processing system. Micro diagnostics can be subdivided into operability micro diagnostics and background micro diagnostics. The operability micro diagnostics support the macro-operability tests and are performed during initial power-up of a system by testing hardware circuitry that would prevent the execution of the first macro-operability instruction if faulty. Operability microdiaynostics and background micro-diagnostics work together towards attaining a high percentage of fault detection and to assist in fault isolation by testing circuitry which is either untestable or inefficient to test using BIT hardware exclusively.
Referring now to FIG. 6, the organization of the micro-diagnostics as a hierarchy structure is shown. Each box in Fig 6 represents a microprogrammed test module and may be either a control or a test module. Control modules consist of two or more call instructions and a return instruction.
A control module will call either a subordinate control module or a test module Test modules explicitly test functional hardware areas of the information processing system 60. Examples of control modules are the executive 178 operability micrsdiagnostics 180 and background micro-diagnostics 181. The background micro diagnostics 181 are comprised entirely of test modules such as OWE 186, control sequencer 187~ floating point 188, registered arithmetic 95~
logic unit 189 and register 190 modules. The micro diagnostics art designed so that operability micro diagnostics 180 and background micro diagnostics 181 share microprogrammed test modules or common microinstruction code as indicated in FIG.
6. A fault 182 module is called by the microprogram when a failure is detected. The object of the fault 182 module is to establish a stable system state (i.e. jump to self) and alert the BIT maintenance controller 72 of the failure.
Each functional test module has a short cycle code specified for that function The code is generated in one module and passed as a parameter to the next module The next module will, upon program entry, test the passed short cycle code value and if wrong, BIT hardware will be notified of a fault The short cycle code is generated by incrementing the passed code with a constant. Short cycle code is tested when performing background micro diagnostics 181 and operability micro diagnostics lay.
A complete operability micro diagnostic test sequence comprises performing all of the test modules shown in FIG. 6 comprising system bus interface 183, priority interrupt network 184, RAM lay, ROM 186, control sequencer 187, floating point 188, and registered arithmetic logic unit 189~ A complete sequence ox background micro diagnostics comprises performing the following test modules. TOM 186, control sequencer 187, Lang point 188 J registered I
arithmetic logic unit 189 and register 190. The ROM 186, control sequencer 187, floating point 188 and registered arithmetic logic unit 189 test modules are the same test modules for both operability micro diagnostics 180 and back-S ground micro diagnostics 181, which minimizes the amount of control swore 70 that is required.
The operability microdiagnos~ics 180 support assembly language macro-operability tests (software tests performed immediately following an initial program load and power-up of an information processing system by testing circuitry that would prevent the execution of the first macro-operability instruction. The operability micro diagnostics 180 will not preserve the previous state of an information processing system, and assumes that the hardware hard core (minimal amount of circuitry required to start the first micro diagnostic test) is operational. The operability micro diagnostic sly build on that hard core by testing additional circuitry until all required ~estinq is completed, they are performed under the control of the fo~egrQund micro-program counter 24. After completion ox the operability micro diagnostics, the assembly language macrQ-operability test is executed The background micro diagnostics 181 are performed during processor idle machine times, The control sequencer 76 of a US microprogrammed control unit 62 comprises two microprogram Jo ~2~4 counters 24 and 26, as previously described, which work simultaneously during execution of assembly language programs. Since the background micro diagnostic tests are executed during idle machine times employing the background microprogram counter 26, these tests are transparent (tummies) to any user programs. The background micro-diagnostics are executed three microinstruction at a time, as illustrated in FIG. 8, to allow more complete testing.
FIG. 8 shows a control store 70 comprising a foreground microprogram for implementing a microinstruction A and comprising micro diagnostic test modules B and C. During the execution of microinstruction An at time tnf two control signals from said microinstruction An cause program control to switch to the background microprogram counter 26 whereby, in this illustration, micro diagnostic test module B is executed three instructions at a time. At the conclusion of the third microinstruction (By) program control is switched back to the foreground microprogram counter 24 and the execution of microinstruction on is completed. The back-ground micro diagnostics 181, due to the nature of their execution, do not change the state of a computer system or an information processing system 60. The intent of background micro diagnostics 181 is to continually exercise functions not tested by on-line BIT and to alert a bit maintenance controller 72, as shown in FIG. 2, upon detection of a fault.
The idle times during which background micro diagnostics 181 are executed include periods where a memory access does not overlap micro code execution or when a processor must wait for another operation to be completed. Also, certain instructions have periods of inactivity (wait state) and additionally, a periodic time-out every millisecond may be used to ensure failsafe operation of background micro-diagnostics Referring now to FIGS. 1 and 2, the method of operation of micro diagnostics is as follows: assume that the foreground microprogram counter 24 is being used to execute a string of microinstruction to implement a machine eye rut or an instruction set architecture (IS) operation which requires a fetch from memory unit 66. The memory fetch is initiated and the processor comprising control unit 62 and arithmetic unit 64 begins waiting for the system data bus 87 to present valid data. Jointly with the initiation of the memory fetch, the IS operation Roy eye transfers control to the background microprogram counter 26 by means of the control switch 161. The control sequencer I is thereby switched to a background mode and a background micro-diagnostic test controlled by the microdiaqnostic microprogram mounter 26 execute three microinstruction Blue By and By, as shown in FIG 8, from one of the test modules shown in FIG. 6. At the conclusion of the execution of the third ~L~2Ç~
microinstruction, the micro diagnostic test generates control signals (SWITCH 163 and INHIBIT 164 to cause a swap micro-program counter action which transfers control back to the foreground microprogram counter 24. This procedure continues until all test modules making up a micro diagnostic test are completed.
Micro diagnostic tests in the background mode do not alter the operational state of the processor and avoid exercising any state which could effect IS execution such as general purpose flags, data registers or overflow). The foreground mode of operation is not aware of the execution of background mode micro diagnostics.
! Referring now to FIG. 7, a typical background micro-diagnostic program sequence is shown comprising control sequencer 187, registered arithmetic logic unit 1~9, floating point 188 and register 190 test modules. The name of a test module indicates the functional area of a system being tested.
Each test module generates a short cycle code SAC When background mode microdiagno tics are enabled and a new functional test module is entered, the short cycle code generated by the previous test module is passed as a parameter to the next module in the execution sequence and checked. If the passed code is determined to be wrong, BIT
hardware is notified of a fault. Short cycle code is tested in both operability end background micro diagnostic lo is.
I
This short cycle code guarantees that a complete micro-diagnostic sequence of test modules is executed and not just a subset of test modules due to a latency failure. The principal reason for performing background micro diagnostics is to reduce failure latency time or the time it takes to discover a failure condition.
This concludes the description of the preferred embodiment. However, many modifications and alterations will be obvious to one of ordinary skill in the art without departing from the spirit and scope of the inventive concept.
Therefore, it is intended that the scope of this invention be limited only by the appended claims.
Claims (25)
1. A processing system for executing a stored primary program comprising:
memory means for storing a secondary program; and means responsive to at least one selected instruction of said primary program for enabling said processing system to execute said stored secondary program during the execution of said selected primary program instruction.
memory means for storing a secondary program; and means responsive to at least one selected instruction of said primary program for enabling said processing system to execute said stored secondary program during the execution of said selected primary program instruction.
2. A processing system as recited in Claim l wherein:
said stored secondary program comprises microprogrammed microdiagnostics.
said stored secondary program comprises microprogrammed microdiagnostics.
3. A processing system as recited in Claim l wherein:
said enabling means comprises a microprogrammed control unit having a control sequencer.
said enabling means comprises a microprogrammed control unit having a control sequencer.
4. A processing system as recited in Claim 3 wherein:
said selected instruction of said primary program is executed by at least one microinstruction of said micro-programmed control unit.
said selected instruction of said primary program is executed by at least one microinstruction of said micro-programmed control unit.
5. A processing system as recited in Claim 3 wherein:
said control sequencer comprises at least two micro-program counters.
said control sequencer comprises at least two micro-program counters.
6. A processing system as recited in Claim 5 wherein:
a first of said two microprogram counters controls the addressing of microinstructions for executing said primary program and a second of said two microprogram counters controls the addressing of microinstructions for performing said secondary program.
a first of said two microprogram counters controls the addressing of microinstructions for executing said primary program and a second of said two microprogram counters controls the addressing of microinstructions for performing said secondary program.
7. An information processing system having a microprogrammed control unit which performs a background microprogram during the operation of a fore-ground program comprising:
memory means for storing a plurality of microinstructions for per-forming said background microprogram and said foreground program; and control sequencer means for independently controlling said fore-ground program operation and said background microprogram including at least two microprogram counters wherein a first microprogram counter participates in performing said foreground program and a second microprogram counter controls said background microprogram.
memory means for storing a plurality of microinstructions for per-forming said background microprogram and said foreground program; and control sequencer means for independently controlling said fore-ground program operation and said background microprogram including at least two microprogram counters wherein a first microprogram counter participates in performing said foreground program and a second microprogram counter controls said background microprogram.
8. The information processing system as recited in Claim 7 wherein:
said background microprogram comprises a portion of said plurality of microinstructions for performing microdiagnostics.
said background microprogram comprises a portion of said plurality of microinstructions for performing microdiagnostics.
9. The information processing system as recited in Claim 7 wherein:
said control sequencer means further comprises control switch means coupled to said first microprogram counter and said second microprogram counter for switching control between said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from one of said microinstructions.
said control sequencer means further comprises control switch means coupled to said first microprogram counter and said second microprogram counter for switching control between said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from one of said microinstructions.
10. The information processing system as recited in Claim 7 wherein:
said background microprogram comprises a plurality of test modules stored in said memory means, each of said test modules comprising means for generating and testing a short cycle code to verify the performance of said test modules.
said background microprogram comprises a plurality of test modules stored in said memory means, each of said test modules comprising means for generating and testing a short cycle code to verify the performance of said test modules.
11. An information processing system having a microprogrammed control unit which performs a background microprogram during the operation of a fore-ground program comprising:
memory means for storing a plurality of microinstructions for per-forming said background microprogram and said foreground program;
control sequencer means for independently controlling said fore-ground program operation and said background microprogram including at least two microprogram counters wherein a first microprogram counter participates in performing said foreground program and a second microprogram counter controls said background microprogram; and coding means coupled to said microprogram counters within said control sequencer means for generating a predicted code to detect an error in a microinstruction address.
memory means for storing a plurality of microinstructions for per-forming said background microprogram and said foreground program;
control sequencer means for independently controlling said fore-ground program operation and said background microprogram including at least two microprogram counters wherein a first microprogram counter participates in performing said foreground program and a second microprogram counter controls said background microprogram; and coding means coupled to said microprogram counters within said control sequencer means for generating a predicted code to detect an error in a microinstruction address.
12. The information processing system as recited in Claim 11 wherein:
said coding means coupled to said microinstruction address further comprises means for determining that a code located in the contents of said microinstruction address, verifies said predicted code for said micro-instruction address.
said coding means coupled to said microinstruction address further comprises means for determining that a code located in the contents of said microinstruction address, verifies said predicted code for said micro-instruction address.
13. The information processing system as recited in Claim 12 wherein:
said coding means further comprises means for generating a fail signal when a code verification error is detected.
said coding means further comprises means for generating a fail signal when a code verification error is detected.
14. An information processing system having a microprogrammed control unit comprising:
memory means for storing a plurality of microinstructions for performing a background microdiagnostic microprogram during the operation of a foreground program;
a first microprogram counter for generating an address of a next microinstruction during the performance of said foreground program;
a second microprogram counter for generating an address of a next microinstruction of said background microdiagnostic microprogram; and a multiplexer means connected to said first microprogram counter and said second microprogram counter for selecting an address of said next microinstruction from either said first microprogram counter of said second microprogram counter in accordance with an address select signal generated by said control unit.
memory means for storing a plurality of microinstructions for performing a background microdiagnostic microprogram during the operation of a foreground program;
a first microprogram counter for generating an address of a next microinstruction during the performance of said foreground program;
a second microprogram counter for generating an address of a next microinstruction of said background microdiagnostic microprogram; and a multiplexer means connected to said first microprogram counter and said second microprogram counter for selecting an address of said next microinstruction from either said first microprogram counter of said second microprogram counter in accordance with an address select signal generated by said control unit.
15. The information processing system as recited in Claim 11 wherein:
said microprogrammed control unit further comprises a means for switching control between said first microprogram counter and said second microprogram counter in accordance with a plurality of switch control sig-nals from one of said microinstructions.
said microprogrammed control unit further comprises a means for switching control between said first microprogram counter and said second microprogram counter in accordance with a plurality of switch control sig-nals from one of said microinstructions.
16. An information processing system having a microprogrammed control unit comprising:
memory means for storing a plurality of microinstructions for per-forming a background microdiagnostic microprogram during the operation of a foreground program;
a first microprogram counter for generating an address of a next microinstruction during the performance of said foreground program;
a second microprogram counter for generating an address of a next microinstruction of said background microdiagnostic microprogram;
a multiplexer means connected to said first microprogram counter and said second microprogram counter for selecting an address of said next microinstruction from either said first microprogram counter of said second microprogram counter in accordance with an address select signal from said memory means;
microprogram stack means connected to said first microprogram counter for performing microprogram interrupt subroutines;
branch condition multiplexer means connected to said first micro-program counter, said second microprogram counter and an output address multiplexer for generating an address of said next microinstruction in accor-dance with branch condition signals from within said information processing system;
said output address multiplexer means receiving an address jam input signal from within said information processing system and coupled to output signals of said multiplexer means, said stack means and said branch condition multiplexer means for selecting a source of said next microinstruc-tion address; and control switch means coupled to said memory means for switching control between said first microprogram counter and said second microprogram counter;
controller means coupled to said memory means, to said output add-ress multiplexer, to said branch condition multiplexer means and said micro-program stack means for decoding function codes from said memory means.
memory means for storing a plurality of microinstructions for per-forming a background microdiagnostic microprogram during the operation of a foreground program;
a first microprogram counter for generating an address of a next microinstruction during the performance of said foreground program;
a second microprogram counter for generating an address of a next microinstruction of said background microdiagnostic microprogram;
a multiplexer means connected to said first microprogram counter and said second microprogram counter for selecting an address of said next microinstruction from either said first microprogram counter of said second microprogram counter in accordance with an address select signal from said memory means;
microprogram stack means connected to said first microprogram counter for performing microprogram interrupt subroutines;
branch condition multiplexer means connected to said first micro-program counter, said second microprogram counter and an output address multiplexer for generating an address of said next microinstruction in accor-dance with branch condition signals from within said information processing system;
said output address multiplexer means receiving an address jam input signal from within said information processing system and coupled to output signals of said multiplexer means, said stack means and said branch condition multiplexer means for selecting a source of said next microinstruc-tion address; and control switch means coupled to said memory means for switching control between said first microprogram counter and said second microprogram counter;
controller means coupled to said memory means, to said output add-ress multiplexer, to said branch condition multiplexer means and said micro-program stack means for decoding function codes from said memory means.
17. An information processing system having a microprogrammed control unit comprising:
memory means for storing a plurality of microinstructions for per-forming microdiagnostic tests and microinstructions;
a first microprogram counter for generating an address of a next microinstruction for performing said microdiagnostic tests or for performing a macro-instruction;
a second microprogram counter for generating an address of a next microinstruction of background microdiagnostic tests being performed during the operation of a foreground macro-instruction, said foreground macro-instruction being under the control of an independent program counter.
memory means for storing a plurality of microinstructions for per-forming microdiagnostic tests and microinstructions;
a first microprogram counter for generating an address of a next microinstruction for performing said microdiagnostic tests or for performing a macro-instruction;
a second microprogram counter for generating an address of a next microinstruction of background microdiagnostic tests being performed during the operation of a foreground macro-instruction, said foreground macro-instruction being under the control of an independent program counter.
18. A microprogrammed control unit comprising:
memory means for storing a plurality of microinstructions for per-forming a background microdiagnostic microprogram during the operation of a foreground program;
control sequencer means for independently controlling said fore-ground program operation and said background micro diagnostic microprogram including at least two microprogram counters wherein a first microprogram counter participates in performing said foreground program and a second microprogram counter controls said background microdiagnostic microprogram.
memory means for storing a plurality of microinstructions for per-forming a background microdiagnostic microprogram during the operation of a foreground program;
control sequencer means for independently controlling said fore-ground program operation and said background micro diagnostic microprogram including at least two microprogram counters wherein a first microprogram counter participates in performing said foreground program and a second microprogram counter controls said background microdiagnostic microprogram.
19. The microprogrammed control unit as recited in claim 18 wherein:
said control sequencer means further comprises means for switching control between said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from one of said microinstructions.
said control sequencer means further comprises means for switching control between said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from one of said microinstructions.
20. The microprogrammed control unit as recited in Claim 18 wherein:
said background microdiagnostic microprogram comprises a plurality of test modules stored in said memory means, each of said test modules com-prising means for generating and testing a short cycle code to verify the performance of said test modules.
said background microdiagnostic microprogram comprises a plurality of test modules stored in said memory means, each of said test modules com-prising means for generating and testing a short cycle code to verify the performance of said test modules.
21. A method for executing a stored primary program in a processing system comprising the steps of:
storing a secondary program;
executing said stored secondary program during the execution of a selected instruction of said primary program by the processing system.
storing a secondary program;
executing said stored secondary program during the execution of a selected instruction of said primary program by the processing system.
22. A method in an information processing system having a microprogram-med control unit for performing a background microprogram during the opera-tion of a foreground program comprising the steps of:
storing a plurality of microinstructions for performing said back-ground microprogram and said foreground program; and controlling independently said foreground program operation and said background microprogram with at least two microprogram counters wherein a first of said microprogram counters participates in performing said fore-ground program and a second of said microprogram counters controls said back-ground microprogram.
storing a plurality of microinstructions for performing said back-ground microprogram and said foreground program; and controlling independently said foreground program operation and said background microprogram with at least two microprogram counters wherein a first of said microprogram counters participates in performing said fore-ground program and a second of said microprogram counters controls said back-ground microprogram.
23. The method as recited in Claim 22 wherein:
the step of controlling independently said foreground program operation and said background microprogram comprises switching control be-tween said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from one of said microinstructions.
the step of controlling independently said foreground program operation and said background microprogram comprises switching control be-tween said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from one of said microinstructions.
24. The method as recited in Claim 22 wherein:
the step of performing a background microprogram comprises perform-ing a plurality of test modules, and generating and testing in each of said test modules a short cycle code to verify the performance of said test modules.
the step of performing a background microprogram comprises perform-ing a plurality of test modules, and generating and testing in each of said test modules a short cycle code to verify the performance of said test modules.
25. A method of performing failure detection in an information proces-sing system having a microprogrammed control unit which performs background microprogram during the operation of a foreground program comprising the steps of:
storing a plurality of microinstructions for performing said back-ground microprogram and said foreground program each of said microinstructions having a first code for verification of an address of each one of said micro-instructions and the contents of said address;
controlling said foreground program and said background microprogram with at least two microprogram counters;
generating a residual code from said first code representative of a code for a current microinstruction address;
generating and storing a second code for said microinstruction address during a previously executed microinstruction; and comparing said residual code to said second code for detecting a failure.
storing a plurality of microinstructions for performing said back-ground microprogram and said foreground program each of said microinstructions having a first code for verification of an address of each one of said micro-instructions and the contents of said address;
controlling said foreground program and said background microprogram with at least two microprogram counters;
generating a residual code from said first code representative of a code for a current microinstruction address;
generating and storing a second code for said microinstruction address during a previously executed microinstruction; and comparing said residual code to said second code for detecting a failure.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US60960284A | 1984-05-11 | 1984-05-11 | |
| US609,602 | 1984-05-11 |
Publications (1)
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|---|---|
| CA1226954A true CA1226954A (en) | 1987-09-15 |
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ID=24441504
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000479667A Expired CA1226954A (en) | 1984-05-11 | 1985-04-22 | Control sequencer with dual microprogram counters for microdiagnostics |
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| JP (1) | JPS60254250A (en) |
| CA (1) | CA1226954A (en) |
| DE (1) | DE3517103A1 (en) |
| GB (1) | GB2158977B (en) |
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|---|---|---|---|---|
| US4839895A (en) * | 1987-01-07 | 1989-06-13 | Nec Corporation | Early failure detection system for multiprocessor system |
| US5117387A (en) * | 1988-08-18 | 1992-05-26 | Delco Electronics Corporation | Microprogrammed timer processor |
| US5068851A (en) * | 1989-08-01 | 1991-11-26 | Digital Equipment Corporation | Apparatus and method for documenting faults in computing modules |
| EP1736995A1 (en) * | 1999-11-15 | 2006-12-27 | Autonetworks Technologies, Ltd. | Check method of temporary storage circuit in electronic control unit |
| JP4310878B2 (en) | 2000-02-10 | 2009-08-12 | ソニー株式会社 | Bus emulation device |
| US7415700B2 (en) | 2003-10-14 | 2008-08-19 | Hewlett-Packard Development Company, L.P. | Runtime quality verification of execution units |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE2238496A1 (en) * | 1972-08-04 | 1974-02-14 | Siemens Ag | METHOD OF TESTING MICRO-PROGRAM CONTROLLED PROCESSORS |
| GB1436428A (en) * | 1972-10-31 | 1976-05-19 | Ibm | Data processing apparatus |
| US3831148A (en) * | 1973-01-02 | 1974-08-20 | Honeywell Inf Systems | Nonexecute test apparatus |
| US3838260A (en) * | 1973-01-22 | 1974-09-24 | Xerox Corp | Microprogrammable control memory diagnostic system |
| DE2350314A1 (en) * | 1973-10-06 | 1975-06-26 | Ibm Deutschland | PROGRAMS FOR PROGRAM ANALYSIS AND PROGRAM MAINTENANCE OF PROGRAMS |
| SU613651A1 (en) * | 1976-12-16 | 1987-03-15 | Предприятие П/Я А-3886 | Memory |
| JPS5614356A (en) * | 1979-07-13 | 1981-02-12 | Toshiba Corp | Diagnostic system |
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- 1985-04-22 CA CA000479667A patent/CA1226954A/en not_active Expired
- 1985-05-08 GB GB08511670A patent/GB2158977B/en not_active Expired
- 1985-05-11 DE DE19853517103 patent/DE3517103A1/en not_active Withdrawn
- 1985-05-11 JP JP60100363A patent/JPS60254250A/en active Pending
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| GB2158977A (en) | 1985-11-20 |
| DE3517103A1 (en) | 1985-11-14 |
| GB8511670D0 (en) | 1985-06-12 |
| GB2158977B (en) | 1988-04-07 |
| JPS60254250A (en) | 1985-12-14 |
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