CA1223079A - Data processor having selective breakpoint capability with minimal overhead - Google Patents

Abstract

A DATA PROCESSOR HAVING SELECTIVE BREAKPOINT
CAPABILITY WITH MINIMAL OVERHEAD

Abstract A data processor which communicates with a peripheral device and which selectively sets breakpoints with minimal overhead is provided. The data processor utilizes an instruction register to store instructions to be executed.
Control means communicate with the peripheral device to selectively set a breakpoint in a software program. When repetitions of the breakpoint are encountered, an exception handler is only executed at the desired breakpoint to minimize overhead. A control portion of the processor selectively receives a breakpoint instruction and stores the breakpoint instruction in the instruction register.

Description

2~3~9 A DATA PROCESSOR HIVING SELECTIVE BREAKPOINT
CAPABILITY WITH MINIMAL ODE

Cross Reference to Related Patent his application is related to United States Patent No. 4,488,288 issued December 11, 1~84 to Crudely et at and assigned to the assignee hereof, and entitled:
"Virtual Memory Data Processor".

Field of the Invention This invention relates generally to data processors, and more particularly, to a data processor having breakpoint instruction capability.

Background of the Invention In a data processor, breakpoints are typically used to debug software errors in computers. A breakpoint is literally a point in a software program where a break in the program is taken and data in memory is read to ascertain the status of the program at that point. From this information, a programmer may determine what is happening in the program at selected points. Initially, breakpoints were realized in processing systems utilizing card reading machines by physically inserting a card which was recognized as an illegal instruction as a predetermined location in the program and causing the program to be terminated and the memory contents written If multiple breakpoints were desired, the illegal instruction card was ~23~

moved by the programmer to another breakpoint and the program run again. Later generations of processors expanded the breakpoint function by using multiple breakpoint instructions which would signal an interrupt status but would not terminate the program as other illegal instructions would. This gave a programmer the ability to perform multiple breakpoints in a single run of the program. However, the ability to selectively execute breakpoints in a program having repetitive subroutines was needed. The capability of selectively using breakpoint instructions was not easily executed in this generation because software was required to control the exact location of breakpoints in programs having multiple repetitive sections. Further, every time a breakpoint instruction was received, an exception was forced to occur regardless of whether the breakpoint was desired or not. The overhead involved with implementing breakpoints by software was large because of the time required for exception handling.
Another generation of processors provided the ability to selectively use breakpoints by utilizing external hardware. When multiple breakpoints were used, the associated hardware increased proportionately. The determination of where breakpoints were taken in a software program was made by closely monitoring the external bus activity and the instructions being executed by the processor. A determination of whether or not to take the breakpoint was made by the external hardware which monitors the number of times a memory location is accessed. After a predetermined number of accesses, the breakpoint is forced to occur. However, the presence of an on-board instruction cache in a data processor prevents proper monitoring since no external bus activity may occur.

Summary of the Invention Accordingly, an object of the present invention is to ~23~

provide a data processor having improved breakpoint instruction capability.
A further object of the present invention is to provide a data processor having improved selective breakpoint instruction capability with minimal overhead.
In carrying out the above and other objects, there is provided, in one form, a data processor adapted to communicate operands with a peripheral device. The data processor has an instruction register for storing an instruction to be executed by the processor. Instruction execution control means execute instructions stored in the instruction register. The instruction execution control means also receive an operand from the peripheral device and selectively store the operand in the instruction register in response to the execution of a breakpoint instruction. The breakpoint instruction may be selectively chosen in a repetitive portion I a program without repetitively effecting an interrupt handler.

Brief Description of the Drawings FIG 1 is a block diagram of a virtual memory data processing system having the virtual memory data processor of the present invention;
FIG. 2 is a block diagram of the virtual memory data processor of Fig l;
FIG 3 is block diagram of the execution unit of the virtual memory data processor of FIG 2;
FIG 4 is a block diagram of the high section of the execution unit of FIG 3;
FIG. 5 is a block diagram of the low section of the execution unit of FIG. 3;
FIG 6 is a block diagram of the data section of the execution unit of FIG 3;
FIG. 7 is a block diagram illustrating the relationship of the field translation unit of the virtual memory data processor of FIG. 2 to other functional units therein;
FIG 8 is a block diagram illustrating a typical breakpoint control circuit of FIG. l; and FIG. 9 is a flow chart of software micro-instructions which implement a breakpoint instruction.

Detailed Description of the Invention Shown in FIG. l is a virtual memory data processing system 10 wherein logical addresses (LADDER) issued by a virtual memory data processor (VMDP) 12 are mapped by a memory management unit (MU) 14 to a corresponding physical address (PADDY) for output on a physical bus (PUS) 16.
Predetermined ones ox the logical addresses may include breakpoint acknowledge cycles in response to a breakpoint instruction which are coupled to a breakpoint control circuit 17. Breakpoint control circuit 17 selectively implements predetermined breakpoints. An output of breakpoint control circuit 17 is coupled to physical bus 16. Simultaneously, the various logical access control signals (LCNTL) provided by VMDP 12 to control the access are converted to appropriately timed physical access control signals (PCNTL) by a modifier unit 18 under the control of MU 14.
In response to a particular range of physical addresses (PADDY), memory 20 will cooperate with an error detection and correction circuit REDACT 22 to exchange data (DATA) with VMDP 12 in synchronization with the physical access control signals (PCNTL) on PUS 16. Upon detecting an error in the data EDAC 22 will either signal a bus error (BURR) or request VMDP 12 to retry (RETRY) the exchange, depending upon the type of error.
In response to a different physical address, mass storage interface 24 will cooperate with VAMP 12 to transfer data to or from mass storage 26. If an error occurs during the transfer, interface 24 may signal a bus error (BURR) or, if appropriate, request a retry RETRY).
In response to yet another physical address, a direct memory access controller (DMAC) 28 will accept data from the VMDP 12 defining a data transfer operation. Upon being released to perform the operation, DMAC 28 Jill use appropriate PCNTL lines to periodically request VMDP 12 to relinquish control of the bus. Upon being granted control of the bus, the DMAC 28 will transfer a block of data within memory 20 or between memory 20 and mass storage 26.
of an error is detected during any such transfer by either the EDAC 22 or mass storage interface 24, DMAC 28 will either abort or retry the transfer, depending upon whether BURR or RETRY was signaled.
In the event that the MU 14 is unable to map a particular logical address (LADDER) into a corresponding physical address (PADDY), the MU 14 will signal an access fault (FAULT). As a checlc for MU 14, and for DMAC 28 as well, a watchdog timer 30 may be provided to signal a bus error (BURR) if no physical device has responded to a physical address (PADDY) within a suitable time period relative to the physical access control signals (PCNTL).
If, during a data access bus cycle, a RETRY is requested, OR gates 32 and 34 will respectively activate the BURR and HALT inputs of VMDP 12. In response to the simultaneous activation of both the BURR and HALT inputs thereof during a VMDP-controlled bus cycle, VMDP 12 will abort the current bus cycle and, upon the termination of the RETRY signal, retry the cycle.
If desired, operation of VMDP 12 may be externally controlled by judicious use of a HALT signal. In response to the activation of only the HALT input thereof via OR
gate 34, VMDP 12 will halt at the end of the current bus ~3~^7~

cycle, and will resume operation only upon the termination of the HALT signal.
In response to the activation of only the BURR input thereof during a processor-controller bus cycle, VMDP 12 will abort the current bus cycle, internally save the-contents of the status register, enter the supervisor state, turn off the trace state if ox, and generate a bus error vector number. VMDP 12 will then stack into a supervisor stack area in memory 20 a block of information which reflects the current internal context of the processor, and then use the vector number to branch to an error handling portion of the supervisor program. This is the operation VMDP 12 performs in response to a bus error input signal, except for a bus error signal provided by breakpoint control circuit 17 in response to a break point acknowledge cycle generated by VMDP 12, indicating that a breakpoint is to be taken. Gus errors received during a breakpoint acknowledge cycle cause VMDP 12 to begin exception processing for an illegal instruction format as described below.
Up to this point, the operation of VMDP 12 is identical to the operation of Motorola's MCKEE
microprocessor. However, VMDP 12 differs from the MCKEE
primarily in the amount of information which is stacked in response to the assertion of BERRY The information stacked by the MCKEE consists of: the saved status register, the current contents of the program counter, the contents of the instruction register which is usually the first word of the currently executing instruction, the logical address which was being accessed by the aborted bus cycle, and the characteristics of the aborted bus cycle, i.e. read/write, instruction/data and function code. In addition to the above information, VMDP 12 is constructed to stack much more information about the internal machine state. If the exception handler is successful in resolving the error, the last instruction thereof will return control of VMDP 12 to the aborted program. During the execution of this instruction, the additional stacked information is retrieved and loaded into the appropriate portions of VMDP
12 to restore the state which existed at the time the buss error occurred.
Under certain circumstances, such as when an access is attempted to a non-existent peripheral, the supervisor may choose to perform the request access but utilize a different resource. If the faulted access was a read, the supervisor can store the accessed information in the appropriate location in the stack. To make it appear to the faulted instruction as if the non-existent peripheral had actually responded, the supervisor can set a flag in the stack indicating that the access has already been performed. Just before resuming execution of the faulted instruction, VMDP 12 can check the flag and, if set, can resume instruction execution as if the access had just been successfully completed. Thus, the faulted program will be unaware that the accessed resource is not actually present.
The preferred operation of VMDP 12 will be described with reference to FIG. 2 which illustrates the internal organization of a microprogrammable embodiment of VMDP 12.
Since the illustrated form of VMDP 12 is very similar to the Motorola MCKEE microprocessor described in detail in the several US. Patents cited hereafter, the common operational aspects will be described rather broadly. Once a general understanding of the internal architecture of VMDP 12 is established, the discussion will focus on the unique aspects which distinguish VMDP 12 from the MCKEE, and enable the former to support virtual memory.
The VMDP 12~ like the ~C68000, is a pipeline, microprogrammed data processor. In a pipeline processor, each instruction is typically fetched during the execution of the preceding instruction, and the interpretation of the fetched instruction usually begins before the end of the preceding instruction. In a microprogrammed data processor, each instruction is executed as a sequence of microinstruction which perform smell pieces of the operation defined by the instruction. If desired, user instructions may be thought of as microinstruction. In the MCKEE and VMDP 12, each microinstruction comprises a micro word which controls microinstruction sequencing and function code generation, and a corresponding nanoword which controls the actual routing of information between functional units and the actuation of special function units within VMDP 12. With this in mind, a typical instruction execution cycle will be described.
At an appropriate time during the execution of each instruction, a prefetch microinstruction will be executed.
The micro word portion thereof will, upon being loaded from micro ROM 36 into micro ROM output latch 38, enable function code buffers 40 to output a function code (FC) portion of the logical address (LADDER) indicating an instruction cycle. Upon being simultaneously loaded from NATO ROM 42 into NATO ROM output latch 44, the corresponding nanoword requests bus controller 46 to perform an instruction fetch bus cycle, and instructs execution unit I to provide the logical address of the first word of the next instruction to address buffers 50 Upon obtaining control of the PUS 16, bus controller 46 will enable address buffers 50 to output the address portion of the logical address (LOUDER. Shortly thereafter, bus controller 46 will provide appropriate data strobes some of the LCNTL signals) to activate memory 20.
When the memory 20 has provided the requested information, bus controller 46 enables instruction register capture (IRK) 52 to input the first word of the next instruction from PUS 16. At a later point in the execution of the current instruction, another microinstruction will be I

executed to transfer the first word o the next instruction from IRK 52 into instruction register-tIR) 54, and to load the next word from memory 20 into IRK 52,. Depending upon the type of instruction in IT 54, the word in IRK 52 may be immediate data, the address of an operand, or the first word of a subsequent instruction.
In response to the execution of a breakpoint instruction, VMDP 12 executes a breakpoint acknowledge cycle and has the ability to selectively update IT 54 from data received during the breakpoint acknowledge bus cycle.
When the breakpoint is not desired to be taken, external breakpoint control hardware provides an instruction opaqued. This data is then used as the instruction to be executed, is loaded into IT 54, and is decoded by an address 1 decoder 56 and an illegal instruction decoder 58 as described below. If the breakpoint is desired to be recognized, the external hardware provides no data, and simply asserts the BERM signal.
Details of a suitable instruction set and the microinstruction sequences thereof are set forth in US.
Patent No. 4,325,121 entitled, "Two Level Control Store for Microprogrammed Data Processor", issued 13 April 1982 to Gutter et at.
As soon as the first word of the next instruction has been loaded into IT 54, address 1 decoder 56 begins decoding certain control fields in the instruction to determine the micro address of the first microinstruction in the initial micro sequence of the particular instruction in IT 54. Simultaneously, illegal instruction decoder 58 will begin examining the format of the instruction in IT
54. If the format is determined to be incorrect, illegal instruction decoder 58 will provide the micro address of the first microinstruction of an illegal instruction micro sequence. In response to the format error, exception logic 60 will force multiplexer 62 to substitute the micro address provided by illegal instruction decoder 58 for the micro address provided by address 1 decoder 56~ Thus, upon execution of the last microinstruction of the currently executing instruction, the micro word portion thereof may enable multiplexer 62 to provide to an appropriate micro address to micro address latch 64, while the nanoword portion thereof enables instruction register decoder (IRK) 66 to load the first word of the next instruction from IT
54. Upon the selected micro address being loaded into micro address latch 64, micro ROM 36 will output a respective micro word to micro ROM output latch 38 and NATO
ROM 42 will output a corresponding nanoword to NATO ROM
output latch 44.
Generally, a portion of each micro word which is loaded into micro ROM output latch 38 specifies the micro address of the next microinstruction to be executed, while another portion determines which of the alternative micro addresses will be selected by multiplexer 62 for input to micro address latch 64. In certain instructions, more than one micro sequence must be executed to accomplish the specified operation. These tasks, such as indirect address resolution, are generally specified using additional control fields within the instruction. The micro addresses of the first microinstruction for these additional micro sequences are developed by address 2/3 decoder 68 using control information in IT 54. In the simpler form of such instructions, the first micro sequence will typically perform some preparatory task and then enable multiplexer 62 to select the micro address of the micro sequence which will perform the actual operation as developed by the address 3 portion of address 2/3 decoder 68. In more complex forms of such instructions, the first micro sequence will perform the first preparatory task and then will enable multiplexer 62 to select the micro address of the next preparatory micro sequence as developed by the address ~223~79 2 portion of address 2/3 decoder 68~ Upon performing this additional preparatory task, the second micro sequence then enables m~ltiplexor 62 to select the micro address of the micro sequence which will perform the actual operation as developed by the address portion of address 2/3 decoder 68. In any event, the last microinstruction in the last micro sequence of each instruction will enable multiplexer 62 to select the micro address of the first microinstruction of the next instruction as developed by address 1 decoder 56. In this manner, execution of each instruction will proceed through an appropriate sequence of microinstruction. A more thorough explanation of the micro address sequence selection mechanism is given in US.
Patent No. 4,342,078 entitled "Instruction Register Sequence Decoder for Microprogrammed Data Processor" issued 27 July 1982 to Tredennick et at.
In contrast to the micro words, the nanowords which are loaded into NATO ROM output latch 44 indirectly control the routing of operands into and, if necessary, between the several registers in the execution unit 48 by exercising control over register control (high) 70 and register control slow and data) 72. In certain circumstances, the nanoword enables field translation unit 74 to extract particular bit fields from the instruction in IRK 66 for input to the execution 48. The nanowords also indirectly control effective address calculations and actual operand calculations within the execution unit 48 by exercising control over All control 76 and ALUM control 78. In appropriate circumstances, the nanowords enable ALUM control 78 to store into status register SO the condition codes which result from each operand calculation by execution unit 48. A more detailed explanation of ALUM control 78 is given in US. Patent No. 4,312,034 entitled "ALUM and Condition Code Control Unit for Data Processor" issued 19 January 1982 to Gutter et at.

, . . .

'79 As can be seen in FIG 3 r the execution unit 48 in VMDP 12, like the execution unit in the MCKEE, comprises a high section AYE, a low section 48B, and a data section 48C, which can be selectively connected to respective segments of address and data buses 80 and 82, respectively.
Since execution unit 48 is so similar to the execution unit of the MCKEE as described in US. Patent No. 4,296,469~
the common functional units will be described only briefly, followed by a more detailed description of the new elements which allow VMDP 12 to support virtual memory.
As shown in FIG. 4, the high section AYE is comprised primarily of a set of nine high address registers AYE
for storing the most significant 16 bits of 32 bit address operands, a set of eight high data registers D0H-D7H for storing the most significant 16 bits of 32 bit data operands, a temporary high address register AT, a temporary high data register DTH, an arithmetic unit high ASH for performing arithmetic calculations on operands provided on the high section of address and data buses 80 and 82, a sign extension circuit 84 for allowing 32 bit operations on 16 bit operands, and the most significant 16 bits of the program counter PCH and address output buffers AHAB. As shown in FIG. 5, the low section 48B is comprised primarily of a set of nine low address registers ALLELE
for storing the least significant 16 bits of 32 bit address operands, an arithmetic unit low AWL for performing arithmetic calculations on operands provided on the low section of address and data buses 80 and 82, a priority encoder register PER used in multi-register move operations, and the least significant 16 bits of the program counter PAL and address output buffers ABEL. JIG.
5 also illustrates the relationship of an FLU register portion of field translation unit 74 ox the low sections of address and data buses 80 and 82. As shown in FIG. 6, the data section 48C is comprised primarily of a set of eight low data registers D0L-D7L for storing 16 bit operands which may be the least significant 16 bits of 32 bit data operands, a decoder register DCR for generating 16 bit operand masks, an arithmetic and logic unit ALUM for performing arithmetic and logical operations on operands provided on the data section of address and data buses 80 and 82, an ALUM buffer register ALUM, an ALUM extension register ALUM for multi word shift operations, and multiplexed data input and output buffers DIN and DOB, respectively.
Thus far, VMDP 12 has been described in terms of the hardware features which are common with the MCKEE. VMDP
12 also responds to error conditions in a manner somewhat similar to the MCKEE. Recall that MU 14 will signal an address error by generating a FAULT signal, while the other peripheral circuits report bus errors by issuing a BURR
signal. In either event, VMDP 12 will receive a BURR signal via OR gate 32. In response to the BURR signal bus controller 46 will notify exception logic 60 of the error and then orderly terminate the faulty bus cycle. Exception logic 60 then provides multiplexer 62 with the micro address of the bus error exception handler micro sequence to be forced into the micro address latch 64. At this point, the MCKEE would simply load the micro address provided by exception logic 60 into micro address latch 64 and control would pass to the exception handler microseguence to stack out the following information:

SAAB Special System Status Word Bus;
AHAB Access address High;
ABEL Access Address Low;
: IRK Instruction Register Decode;
; So Status Register;
PCH Program Counter High; and PAL Program Counter Low.

I

While this information is ordinarily adequate to determine the cause of the error, this information is not sufficient to allow the present state to be restored Atari the error has been resolved. Accordingly, VMDP 12 internally saves additional information about the current state thereof, before loading the micro address of the exception handler micro sequence. To accomplish this, VMDP 12 has several additional registers for capturing the necessary state information, and some additional access paths are provided to certain existing registers. For example, as shown in FIG. 2, VMDP 12 has a micro address capture latch 86 for storing the micro address in the micro address latch 64 at unit 74, a special status word internal (SUE) register 88 is provided as shown in FIG. 7 to save the following:

PRY Trap Privilege Exception Latch (from exception logic 60);
TRY Trap Trace Exception Latch (from exception logic 60);
TO Trace Pending Latch (from SO);
LO Loop Mode Latch (new bit;
HO Hidden-X Status Bit (from ALUM);
Ax Priority Encoder Output Register Selector (from PER); and TON Trap Vector Number Latch (from exception logic 60).

In addition, the special status word bus (SAAB) register 90 in field translation unit 74, which in the MCKEE saved only:

WOW Read/Write (R/W); and FC Function Code for faulted access;
now saves the following additional information:

I
I

IF nanoROM bit NEWARK ( instruction fetch to IRK);
DO nanoROM bit ~DBI (data fetch to DIN);
RUM Xead-Modify-Write cycle;
HUB nanoROM bit NIGH (high byte transfer from DOB or to DIN); and BY byte/word transfer.
Once this additional state information has been latched, VMDP 12 loads the micro address provided by exception logic 60 into micro address latch I and begins executing the exception handler micro sequence. In the exception handler micro sequence of VMDP 12, the initial microinstruction must clear the address calculation and output paths in execution unit 48 so that the stack address may be safely calculated and provided to MU 14.
Accordingly, several additional registers are provided in the execution unit 48 to store the existing address, data and control information: in the high section AYE shown in FIG. 4, three virtual address temporary high registers VATlH-VAT3H are provided to facilitate capture of the output of ASH and the address in AHAB; in the low section 48B shown in FIG. 5, three virtual address temporary low registers VATlL-VAT3L are provided to allow capture of the output of AWL and the address in ABEL; and, in the data section 48C shown in FIG. 6, two virtual data temporary registers VDTl-VDT2 are provided to store the control information in FLU and the data in DOB. Having cleared the execution unit 48, the exception handler calculates the stack address and proceeds to stack the following information:

SO Status Register;
PCH Program Counter High;
PAL Program Counter Low;
VOW Stack Frame Format and Vector Offset;
SAAB Special System Status Word Bus;

; AHAB Access Address High;
ABEL Access Address Low;
DOB Data Output Buffer;
DUB Data Input Buffer;
IRK Instruction Register Capture;
MEAL Micro Address Capture Latch;
ALUM Contents of ALUM;
FLU Field Translate Unit Register;
AT Address Temporary High ALUM FLU Output Latch AWL Address Temporary Low;
ASH All Latch High;
AWL All Latch Low;
DCRL Decoder Latch;
PURL PER Output Register;
SUE Special Status Word Internal IT Instruction Register DTH Data Temporary High;
; DTL Data Temporary Low;
IRK Instruction Register Decode; and ALUM ALUM register.

The exception handler micro sequence then vectors to the error recovery routine in the supervisor program Using the stacked state information, the supervisor program can determine the cause of the fault, and if appropriate, attempt to fix the problem. For example, an access to a logical address which has no corresponding physical address may simply require that a block of program/data be loaded from mass storage 26 into memory 20. Of course, other processing may also be performed before the faulted program is restarted.
Jo return control to a program which has been suspended, the supervisor program in both the McKee and VMDP 12 executed a return from exception (RYE) I

instruction. In the MCKEE, this instruction will be executed only if the exception was of the type which occurred on instruction boundaries. Thus, the micro sequence for this instruction could simply reload the status register SO and program counter PCH--PCL from the stack, and then pass control to the instruction whose address is in the program counter. In VMDP 12, this instruction is also used to return from access faults which typically occur during execution of an instruction.
Accordingly tube initial microinstruction in this micro sequence fetch the VOW word from the stack to determine the stack frame format. If the short format is indicated, the microseq~ence will proceed as in the MCKEE. If, on the other hand, the long format is indicated, several other words are fetched from the stack to assure that the full frame it available in memory If the frame format is neither short nor long, VMDe 12 will assume that the stack frame is either incorrect or was generated by an incompatible type of processor and will transfer control to a stack frame format error exception handler micro sequence. If another fault is generated at this stage, indicating that a portion of the stack frame has been inadvertently swapped out of memory 20, the same access fault handling procedure will be used to retrieve the rest of the stack.
During the micro sequence which stacks the state information, the micro address contained in the micro address capture latch 86 is coupled to the FLU via a portion of the BY bus, as shown in FIG. 7. Simultaneously, revision validator 92 impresses on the available portion of the BY bus a code which uniquely identifies the version of the microcode contained within VMDP 12. This combined word is subsequently transferred into DOB in the data section 48C of the execution unit 48 for output via data buffers 94 to memory 20. During the validation phase of the I

instruction continuation micro sequence, the MEAL word is fetched from thy stack and loaded into both IRK 52 and DIN
in the data section 48C of the execution unit 48. From DIN, MEAL is transferred to FLU and coupled to the BY bus.
Revision validator 92 then compares the version number portion of MEAL to the internal version number. If they are not the same, revision validator 92 will signal branch control unit 96 to transfer control to the stack frame format exception handler micro sequence. Otherwise, revision validator 92 will simply allow the micro sequence to load the micro address portion of MEAL into address 4 latch 98.
Once the stack frame has been determined to be valid, the micro sequence will enter a critical phase where any fault will be considered a double fault end VMDP 12 will terminate processing until externally reset. During this phase, the rest of the information in the stack is fetched and either reloaded into the original locations or into the several temporary registers. For example, the contents of the micro address latch 64 which were captured by the micro address capture latch 86 will be loaded into address 4 latch 98. However, only after the last stack access are the contents of ALLAH and SO restored from the temporary registers. The last microinstruction in this instruction continuation micro sequence restores the contents of AHAB, ABEL, FLU, and DOB, signals bus controller 46 to restart the faulted bus cycle using the information in SAAB 90, and requests multiplexer 62 to select the micro address in address 4 latch 98.
In the preferred form, bus controller 46 will respond to the restart signal provided by the last microinstruction of the instruction continuation micro sequence by examining a rerun bit RR in SAAB 90. If the supervisor has not set the RR bit in the stack, the bus controller 46 will proceed to rerun the faulted bus cycle under control of the other Allah information in SAAB 90, and then signal exception logic 60 when the cycle has been successfully completed If, on the other hand, the supervisor has set the RR bit, the bus controller 46 will not rerun the bus cycle, but will simply signal exception logic 60 that the cycle if, complete. In response to the cycle complete signal, exception logic 60 will enable multiplexer 62 to output the micro address in address 4 latch 98 to micro address latch 64. The faulted instruction will then resume control of VMDP 12 as if the fault had never occurred.
VMDP 12, unlike the MCKEE, is also capable of creating the illusion that the currently executing user program is executing in the supervisor state. This has been achieved by making all instructions which access the supervisor/user bit in status register SO into privileged instructions. Thus, whenever aft attempt is made by the user program to modify or even read the supervisor/user bit, control will automatically revert to the supervisor.
The supervisor will then be able to prepare and return a suitably modified image of SO to the user program The user program, being insulated from the true SO, can be pretend that it is the supervisor. With the help of the true supervisor, this pseudo supervisor can control the execution of other user program. This capability to control accesses to both real and non-existent system resources from user programs, whether true user or pseudo supervisor, enables the user VMDP 12 to create a virtual machine environment.
Up until this point, the functionality of VMDP system 10 has been discussed. Shown in FIG. 8 is a block diagram of breakpoint control circuit 17 which functions to decode the presence of a breakpoint acknowledge cycle which is internally generated by VMDP 12 during execution of a breakpoint instruction. The breakpoint instruction replaces the normal instruction opaqued at the location in a memory where a breakpoint is desired to be set Logical address signals, LADDER, some of which indicate a breakpoint acknowledge cycle, are coupled to an input of a decoder 102. Due to the existence-of an on-board instruction cache containing breakpoint information in VMDP 1:2, the number of times a memory location is physically accessed may not be monitored by hardware external to VMDP 12 for purposes of identifying when a breakpoint is to be taken. An output of decoder 102 couples a breakpoint acknowledge cycle signal to a first input of a counter 104 and a first input of a control circuit 106. A counter read/write select signal is coupled from a second output of decoder 102 to both a second input of counter 104 and a second input of control circuit 106. A third output of decoder 102 provides an opaqued buffer read/write select signal to both a third input of control circuit 106 and to a first input of an opaqued buffer circuit 108. An output of counter 104 representing a signal indicating that a count is completed is coupled to a fourth input of control circuit 106. A
first output of control circuit 106 provides a data acknowledge signal, SACK. A second output of control circuit 106 provides a bus error signal BERRY and a third output of control circuit 106 provides a drive opaqued signal to a second input of opaqued buffer circuit 108.
multidirectional bus 110 is coupled between PUS 16, a third input of opaqued buffer 108 and a third input of counter 104.
In operation, when a breakpoint acknowledge cycle is recognized key decoder 102, an acknowledge cycle signal is coupled to counter 104 and control circuit 106. The decoder breakpoint acknowledge cycle signal is provided by VMDP 12 in the form of a predetermined function code having a value such as "111" and predetermined address bits having predetermined values such as "aye". Counter 104 is set to a predetermined count so that a breakpoint may be I

taken at a predetermined time. As a result, breakpoints may be selectively made after a predetermined number of repetitions of a portion of a program being executed by VMDP 12. If counter 1~4 has not counted to the predetermined count, control circuit 106 provides a data acknowledge signal SACK and a replacement instruction opaqued to VMDP 12 rather than a bus error signal BERRY
VMDP 12 initializes counter 104 and control circuit 106 via decoder 102 and PUS 16. In this way, counter 1~4 determines the number of times a breakpoint will be ignored before being executed. Similarly, VMDP 12 initializes opaqued buffer circuit 108 via PUS 16 and an opaqued buffer read/write select signal generated by decoder 102. An opaqued representing the instruction which is being replaced by the breakpoint instruction is initially written into opaqued buffer 108 in response to the read/write signal.
When control circuit 106 provides a "drive opaqued out"
signal to opaqued buffer 108, buffer 108 reads out the predetermined opaqued to VMDP 12 via PUS 16. The opaqued is associated with the instruction which VMDP 12 would be normally executing in the absence of a breakpoint instruction. After counter 104 has counted to the predetermined count desired for a breakpoint to occur, control circuit 106 provides a bus error signal which is coupled to OR gate 32 of FIG. 1 and effects an interrupt to occur in the manner previously described. An exception handler is effected and the breakpoint is processed. Shown in FIG. 9 is an instruction flow chart illustrating the breakpoint operation in micro-instruction form. In this manner, selective breakpoint operation is achieved without entering an exception handler every time a breakpoint instruction is encountered in repetitive iterations of a program being processed by a data processing system.

Claims (7)

Claims

1. In a data processor adapted to communicate with a peripheral device, the data processor comprising:
an instruction register for storing an instruction for execution by said data processor; and instruction execution control means, for (1) executing instructions stored in the instruction register, and, in response to executing a breakpoint instruction, (2) providing a control signal to said peripheral device;
(3) receiving a first response from said peripheral device; and (4a) either performing a breakpoint, if the first response is of a first type, (4b) or storing a successive instruction in the instruction register, if the first response is of a second type;
the improvement wherein the instruction execution control means also receives a second response from said peripheral device, the instruction execution control means storing said second response in said instruction register as said successive instruction if said first response is of said second type.

2. A method of communicating operands between a data processor and a peripheral device, comprising the steps of:
storing an instruction to be executed by the data processor in an instruction register;
executing instructions stored in the instruction register;
executing a breakpoint instruction as one of the instructions stored in the instruction register;

providing a control signal from the data processor to the peripheral device in response to executing the breakpoint instruction;
receiving a first response from the peripheral device;
performing a breakpoint in response to the first response being of a first type or storing a successive instruction in the instruction register in response to the first response being of a second type; and receiving and storing a second response from the peripheral device as the successive instruction if the first response is of the second type.

3. A data processor having selective breakpoint capability with minimal overhead by communicating operands with a peripheral device, comprising:
register means for storing instructions to be executed by the data processor; and control means for controlling the execution of the stored instructions in the register means, for directing the peripheral device to either send a control signal directing a breakpoint or send a successive instruction in response to executing a predetermined breakpoint instruction, for receiving and storing the successive instruction in the register means as a text instruction to be executed, and for executing the successive instruction.

4. A data processing system comprising the data processor and peripheral device of claim 1, the peripheral device being coupled to the data processing system via a data bus and comprising:
decoder means having an input for receiving address signals from the data processor, a predetermined one of the address signals indicating a breakpoint instruction, and having a first output for providing a breakpoint acknowledge signal, a second output for providing an initialization signal, and a third output for providing a read/write control signal;

counter means having a first input for receiving the breakpoint acknowledge signal, a second input for receiving the initialization signal, and an output for indicating when a predetermined count has been completed thereby selectively indicating when a breakpoint should be taken;
a control circuit having a first input for receiving the breakpoint acknowledge signal, a second input for receiving the initialization signal, a third input coupled to the output of the counter means, a first output for providing the first type of first response, a second output for providing the second type of first response, and a third output for providing a data bus control signal; and buffer means having a first input for receiving the data bus control signal, a second input for receiving the read/write control signal, and an output for providing the second response.

5. The method of claim 2 further comprising the step of:
reexecuting the breakpoint instruction a predetermined plurality of times before performing the breakpoint.

6. The method of claim 3 wherein the predetermined one of the instructions is a breakpoint instruction.

7. A data processor having selective breakpoint capability with minimal overhead by communicating operands with a peripheral device, comprising:
register means for storing instructions to be executed by the data processor; and control means for selecting a predetermined breakpoint and effecting the peripheral device to send a breakpoint instruction at the selected breakpoint, for controlling the execution of the stored instructions in the register means, and for receiving and storing the breakpoint instruction in the register means.