CA1218465A - Communications controller board - Google Patents
Communications controller boardInfo
- Publication number
- CA1218465A CA1218465A CA000474961A CA474961A CA1218465A CA 1218465 A CA1218465 A CA 1218465A CA 000474961 A CA000474961 A CA 000474961A CA 474961 A CA474961 A CA 474961A CA 1218465 A CA1218465 A CA 1218465A
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- CA
- Canada
- Prior art keywords
- controller
- interrupt
- priority
- board
- communications
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
COMMUNICATIONS CONTROLLER BOARD
ABSTRACT OF THE DISCLOSURE
A communications and controller board utilizes a dual channel universal asynchronous receiver/transmitter in combination with a vector interrupt controller and a priority chain control for permitting vector interrupt and priority chain interrupt of a central processing unit by a plurality of input or output units. Proper priority is preserved both according to vector interrupt and priority chain interrupt schemes.
RS-422 drivers and or receivers are connected to the dual channel universal synchronous receiver/transmitter for the driving thereof as are data bus lines.
ABSTRACT OF THE DISCLOSURE
A communications and controller board utilizes a dual channel universal asynchronous receiver/transmitter in combination with a vector interrupt controller and a priority chain control for permitting vector interrupt and priority chain interrupt of a central processing unit by a plurality of input or output units. Proper priority is preserved both according to vector interrupt and priority chain interrupt schemes.
RS-422 drivers and or receivers are connected to the dual channel universal synchronous receiver/transmitter for the driving thereof as are data bus lines.
Description
6~
COMMUNICP~TIONS CONTRûLLER BOAP~D
_ IEL~ AND BACKGROUND OF THE INVENTION
The present invention relates in general to data processing equipment and in particulax to a new and useful communicatiQn controller board which can be used in trans-ferring data and control informa~ion between a boiler cleaning equipment interface which communicates with boiler cleaning equipment, and central computer.
-Large industrial boilers for generating steam utilize heat exchanger tubes ~nd ~urfaces which require periodic cleaning to snaintaîn boiler efficiency.. The most use~ul method of cleaning these 6urfaces is known as ~soot~
blowingn. Sootblowers are controlled to direct high Yelocity ~treams of gas or fluid at the surfaces to cleanse them of soot and ~ther debris. Regular intervals for ~oot blowing operations must be established, bssed on measurements taken from the boiler and algorithms which are utilized in conjunc-tion with these measurements. Computers are u~ilized to pro-cess the data and to generate ~pprop~iate control signals for the various devioes in the sootblowers.
Since several sootblower~ can usually be found in a ~ingle industrial boiler, each having its own control equipment and date collecting equip~ent, priority must be e~tablished in processing the data and the control signals in a single central processing unit.
.~ ' Each individual boiler cleaning e~uipmen~ in~talla-tion is provided wi~h ~ separate boiler cleaning equipment interface which e~ablishes corNmunication between the cleaning equipment and the central computer. ~ plurality of I/O devices ~input or output devices) are connec~ed to the ~oiler cleaning equipment interface (BCEI~ for bringing ~ignals into and out of the in~erface. ~Pse l/O devices can/ for example, be printer~, terminals, ~ensors or control relays. The si~nal to or from each I/O device has a specific priority ~mong the ~arious devices.
For additional informati3n concerning sootblowinq see STE~, 39TH EDITION, BABCOCK ~ND WILCOX CO~SPANY 1978,AT
CHAPTER 15.
.
Two mechanisms are known for maintaining priority among the signals of several I/O devices.
The first of these utilizes a priori~y controller which is connected ~o each I/O device over an individual re-quest line. When a device requires service a ~ignal is sent to the priority controller from the device and, based on priority, an appropriate interrupt request signal is sent over an additional line from the priority controller ~o the central processing it.
In the second method, each I/O device is connected to a separate control card. Each card i~ connected in a priority chain, in series. The highest priori~y I/O device is closest to the central processing unit (CPU). When an I/O
device requires service, a signal is sent from its associated card to the CPU and at the same time all lower priority cards are disconnected. This se~ond technique is found in he in dustrial ~tandard STD BUS equipment.
~ 5 With b~t~ ~f these techniques, universal asynchro-nou~ re~eiver/tr~n~mitter I~ART) boards ~re utilized. A
single ohannel UART has been utilized in soo~blowing equip--ment interfaces ~nd i6 known as ~he Intel 8251. Dual channel UART are ~lso ~vail~ble but have not hitherto been utiliz.ed in s~otblowing equipment interfaces. An example of the dual UART is the Western Digital 2123 which comes in a 40 pin package and has an internal baud rate generator which can produce a data transmi~sion rate of from 50 to 19,200 baud~
This rate is 60ftware ~electable.
SUMMA~Y OF T~IE INVENTION
The present invention comprises a communications control board which is known as an RS-422 board but which is distinguished from standard BUS ~-422 boards in that it can operate both with the priority control method and the priority chain method.
The inventive RST-422 board includes a dual UART
containing two independent internal baud rate generatorS
which are software selectable from 50 to 19,200 ~aud. RS-422 drivers and receivers are utilized with transmitter outputs and receiver input~ for establishing communication between the I/0 devices and the UART. Four transmit and receive interrupts from the UART are sent directly ~o an interrupt controller in the board. The interrupt controller is an eight level vectored interrupt manager. The remaining four interrupt lines of the interrupt controller are connected to RS-232 interrupts, which are of known design. Interrupt cascade lines are ~ent to the edge of the board for cascading multiple RS-422 boards in a master/slave ~cheme. In this way both a vector interrupt met~od corresponding to the priority controller technique and a priority chain method can be utilized in the inventive RS~422 communications controller board.
~2~
To establish the priority chain~ the interrup-t controller is connected to a priority chain controller that also communicates with the edge of the board. Priority chain control gives the central processing unit priority service of its board or other boards in the system, depending on higher or lower priority, depending on the location of the inventive communications controller board on a chassis which supports a plurality of such boards.
Accordingly an object of the present invention is to provide a communications/controller board which can establish communication between a plurality of I/O devices and a central processing unit which utilizes a dual UART
connected to the central processing unit over a data bus line, a plurality of RS-422 drivers and receivers connected between the I/O devices and the UART, a vector interrupt controller connected to the UARTI a priority chain controller connec-ted to the vector interrupt controller with cascade lines connected to the vector interrupt controller and the priority chain controller.
A further object of the invention is to provide an RS-422 communications/controller board which is simple in design rugged in construction and economical to manufacture.
Accordingly, the present invention provides a cornmunications and controller board for connecting a plurality of I/O devices to a central processing unit according to a selected priority for the I/O devices, comprising: a dual channel universal asynchronous receiver/transmitter board having a plurality of transmit and receive interrupt lines; a vector interrupt controller connected to said transmit and receive interrupt lines for establishing priority among signals on said transmit and receive interrupt lines; an RS-422 driver/receiver for connection to each I/O device and each connected to said universal asynchronous receiver/transmitter board for -transmitting and receiving signals between said I/O devices -- 4a --and said board; an in-terrupt cascade line connected to said vector interrupt controller for receiving a signal from other communications and controller boards; a priority chain control connected to said vector interrup-t controller and for connection to a cascade line to permit priority chain control among a plurality of communications and controller boards; and data receive and transmit lines connected to said universal asynchronous receiver/transmit-ter board and to said vector interrupt controller for receiving and -transmit-ting data.
The various features of novelty which characterize the invention are pointed ou-t with particularity in the claims annexed to and forming a part of this disclosure.
For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descrip-tive matter in which a preferred embodiment of the invention is illustrated.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
`"5 Fi~. 1 is ~ block diagram illustra~ing a vectored interrupt ~ystem util;~ing a priority controller;
~ig. 2 i~ a fi~ure similar to ~iy. 1 6howing a priority chain interrupt system;
~ig. 3 i a blocK diagram showing the connection of two communications/controller boards acco~ding to ~he invention, to a ~ingel central processing uniti ~ig. 4 is a block diagram showin~ the internal structure of a communications/controller board according ~o the inVentiQn;
and ~ig. 5 is a block diagram showing a plurali~y of boiler con-trol equipment interfaces ass~ciated wi~h a single central logic unit which incorporates the central processing unit, in association with a boiler diagram and a unit switch panel ~or controlling and illustrating ~he soot cleaning operations at vari~us locations in a boiler.
DESCRIPTION OF THE PREFERRED EMBODIME:NT
.
RRferring to the drawings in particular, Figs. 1 and 2 illus~rate two prior art techniques for establishing communication between a plurality of input or output devicPs and a single central processing unit 10, while maintaining a correct priority ~or the processing of signals to or from the I/O devices.
Fig. 1 8hows the use of a vectored interrupt scheme where a controller 12 i6 connected by eigh~ request lines numbered 1 through 8, to eight I/O units numbered 21 to 28.
The priority controller receives signals from the I/O units a~d estab~ishes communica~ion with the CPu 10 by a line 11 on which is placed an interrupt request. The higher priority I/O
device 5having the lowest number) is utilized first for an interrupt request.
~g. 2 ~h~ws ~n~t~er technique for establi~hing priority~ Aceording ~o this technique ~eparate cards 31 through 34 are respectively connected to the first four I/0 device~ 21 ~hrough 24 respectively. A priority chain i~
establi~hed by the serie~ connection of cards 31 through 34 alsng ~ priority chain 35. ~f a fiignal is receiYed from I/o unit 22, card 32 disconnects all lower priority cards ( cards 33 and 34~ and uses line 35 to place sn interrupt request on central processin~ unit 10.
~ig. 3 illustrates the present invention wherein both the vectored inte~rupt ~nd the priority chain interrupt technique can be utilized.
Two RS-422 communications/controller boards 42 and 43 are connected in series with an additional card 41, to the CPU 10, over a priority chain 35.
Card 41 is connected to a ~ingle I/o device in a manner ~imilar to cards 31 through 34 of Fig. 2. The inventiYe card 42 i~ connected to eight I/O devices which have priorities
COMMUNICP~TIONS CONTRûLLER BOAP~D
_ IEL~ AND BACKGROUND OF THE INVENTION
The present invention relates in general to data processing equipment and in particulax to a new and useful communicatiQn controller board which can be used in trans-ferring data and control informa~ion between a boiler cleaning equipment interface which communicates with boiler cleaning equipment, and central computer.
-Large industrial boilers for generating steam utilize heat exchanger tubes ~nd ~urfaces which require periodic cleaning to snaintaîn boiler efficiency.. The most use~ul method of cleaning these 6urfaces is known as ~soot~
blowingn. Sootblowers are controlled to direct high Yelocity ~treams of gas or fluid at the surfaces to cleanse them of soot and ~ther debris. Regular intervals for ~oot blowing operations must be established, bssed on measurements taken from the boiler and algorithms which are utilized in conjunc-tion with these measurements. Computers are u~ilized to pro-cess the data and to generate ~pprop~iate control signals for the various devioes in the sootblowers.
Since several sootblower~ can usually be found in a ~ingle industrial boiler, each having its own control equipment and date collecting equip~ent, priority must be e~tablished in processing the data and the control signals in a single central processing unit.
.~ ' Each individual boiler cleaning e~uipmen~ in~talla-tion is provided wi~h ~ separate boiler cleaning equipment interface which e~ablishes corNmunication between the cleaning equipment and the central computer. ~ plurality of I/O devices ~input or output devices) are connec~ed to the ~oiler cleaning equipment interface (BCEI~ for bringing ~ignals into and out of the in~erface. ~Pse l/O devices can/ for example, be printer~, terminals, ~ensors or control relays. The si~nal to or from each I/O device has a specific priority ~mong the ~arious devices.
For additional informati3n concerning sootblowinq see STE~, 39TH EDITION, BABCOCK ~ND WILCOX CO~SPANY 1978,AT
CHAPTER 15.
.
Two mechanisms are known for maintaining priority among the signals of several I/O devices.
The first of these utilizes a priori~y controller which is connected ~o each I/O device over an individual re-quest line. When a device requires service a ~ignal is sent to the priority controller from the device and, based on priority, an appropriate interrupt request signal is sent over an additional line from the priority controller ~o the central processing it.
In the second method, each I/O device is connected to a separate control card. Each card i~ connected in a priority chain, in series. The highest priori~y I/O device is closest to the central processing unit (CPU). When an I/O
device requires service, a signal is sent from its associated card to the CPU and at the same time all lower priority cards are disconnected. This se~ond technique is found in he in dustrial ~tandard STD BUS equipment.
~ 5 With b~t~ ~f these techniques, universal asynchro-nou~ re~eiver/tr~n~mitter I~ART) boards ~re utilized. A
single ohannel UART has been utilized in soo~blowing equip--ment interfaces ~nd i6 known as ~he Intel 8251. Dual channel UART are ~lso ~vail~ble but have not hitherto been utiliz.ed in s~otblowing equipment interfaces. An example of the dual UART is the Western Digital 2123 which comes in a 40 pin package and has an internal baud rate generator which can produce a data transmi~sion rate of from 50 to 19,200 baud~
This rate is 60ftware ~electable.
SUMMA~Y OF T~IE INVENTION
The present invention comprises a communications control board which is known as an RS-422 board but which is distinguished from standard BUS ~-422 boards in that it can operate both with the priority control method and the priority chain method.
The inventive RST-422 board includes a dual UART
containing two independent internal baud rate generatorS
which are software selectable from 50 to 19,200 ~aud. RS-422 drivers and receivers are utilized with transmitter outputs and receiver input~ for establishing communication between the I/0 devices and the UART. Four transmit and receive interrupts from the UART are sent directly ~o an interrupt controller in the board. The interrupt controller is an eight level vectored interrupt manager. The remaining four interrupt lines of the interrupt controller are connected to RS-232 interrupts, which are of known design. Interrupt cascade lines are ~ent to the edge of the board for cascading multiple RS-422 boards in a master/slave ~cheme. In this way both a vector interrupt met~od corresponding to the priority controller technique and a priority chain method can be utilized in the inventive RS~422 communications controller board.
~2~
To establish the priority chain~ the interrup-t controller is connected to a priority chain controller that also communicates with the edge of the board. Priority chain control gives the central processing unit priority service of its board or other boards in the system, depending on higher or lower priority, depending on the location of the inventive communications controller board on a chassis which supports a plurality of such boards.
Accordingly an object of the present invention is to provide a communications/controller board which can establish communication between a plurality of I/O devices and a central processing unit which utilizes a dual UART
connected to the central processing unit over a data bus line, a plurality of RS-422 drivers and receivers connected between the I/O devices and the UART, a vector interrupt controller connected to the UARTI a priority chain controller connec-ted to the vector interrupt controller with cascade lines connected to the vector interrupt controller and the priority chain controller.
A further object of the invention is to provide an RS-422 communications/controller board which is simple in design rugged in construction and economical to manufacture.
Accordingly, the present invention provides a cornmunications and controller board for connecting a plurality of I/O devices to a central processing unit according to a selected priority for the I/O devices, comprising: a dual channel universal asynchronous receiver/transmitter board having a plurality of transmit and receive interrupt lines; a vector interrupt controller connected to said transmit and receive interrupt lines for establishing priority among signals on said transmit and receive interrupt lines; an RS-422 driver/receiver for connection to each I/O device and each connected to said universal asynchronous receiver/transmitter board for -transmitting and receiving signals between said I/O devices -- 4a --and said board; an in-terrupt cascade line connected to said vector interrupt controller for receiving a signal from other communications and controller boards; a priority chain control connected to said vector interrup-t controller and for connection to a cascade line to permit priority chain control among a plurality of communications and controller boards; and data receive and transmit lines connected to said universal asynchronous receiver/transmit-ter board and to said vector interrupt controller for receiving and -transmit-ting data.
The various features of novelty which characterize the invention are pointed ou-t with particularity in the claims annexed to and forming a part of this disclosure.
For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descrip-tive matter in which a preferred embodiment of the invention is illustrated.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
`"5 Fi~. 1 is ~ block diagram illustra~ing a vectored interrupt ~ystem util;~ing a priority controller;
~ig. 2 i~ a fi~ure similar to ~iy. 1 6howing a priority chain interrupt system;
~ig. 3 i a blocK diagram showing the connection of two communications/controller boards acco~ding to ~he invention, to a ~ingel central processing uniti ~ig. 4 is a block diagram showin~ the internal structure of a communications/controller board according ~o the inVentiQn;
and ~ig. 5 is a block diagram showing a plurali~y of boiler con-trol equipment interfaces ass~ciated wi~h a single central logic unit which incorporates the central processing unit, in association with a boiler diagram and a unit switch panel ~or controlling and illustrating ~he soot cleaning operations at vari~us locations in a boiler.
DESCRIPTION OF THE PREFERRED EMBODIME:NT
.
RRferring to the drawings in particular, Figs. 1 and 2 illus~rate two prior art techniques for establishing communication between a plurality of input or output devicPs and a single central processing unit 10, while maintaining a correct priority ~or the processing of signals to or from the I/O devices.
Fig. 1 8hows the use of a vectored interrupt scheme where a controller 12 i6 connected by eigh~ request lines numbered 1 through 8, to eight I/O units numbered 21 to 28.
The priority controller receives signals from the I/O units a~d estab~ishes communica~ion with the CPu 10 by a line 11 on which is placed an interrupt request. The higher priority I/O
device 5having the lowest number) is utilized first for an interrupt request.
~g. 2 ~h~ws ~n~t~er technique for establi~hing priority~ Aceording ~o this technique ~eparate cards 31 through 34 are respectively connected to the first four I/0 device~ 21 ~hrough 24 respectively. A priority chain i~
establi~hed by the serie~ connection of cards 31 through 34 alsng ~ priority chain 35. ~f a fiignal is receiYed from I/o unit 22, card 32 disconnects all lower priority cards ( cards 33 and 34~ and uses line 35 to place sn interrupt request on central processin~ unit 10.
~ig. 3 illustrates the present invention wherein both the vectored inte~rupt ~nd the priority chain interrupt technique can be utilized.
Two RS-422 communications/controller boards 42 and 43 are connected in series with an additional card 41, to the CPU 10, over a priority chain 35.
Card 41 is connected to a ~ingle I/o device in a manner ~imilar to cards 31 through 34 of Fig. 2. The inventiYe card 42 i~ connected to eight I/O devices which have priorities
2 through 9 and card 43 is connected to eight other I/0 devices having priorities 10 throuqh 17. Cards 42 and 43 thus can act either as one of the cards 31 through 34 of Fig. 2 or the priority card 12 of Fig. 1.
Fig. 4 shows, in a block diagram, the internal structure of card 42. Card 43 ~s substantially the same.
As shown in ~ig. 2, a dual UART 52 which may for example be a Western Digital 2123 is connected to a vector interrupt c~ntroller 56 by four transmit ~nd r.eceive inter-rupt lines 58. Transmit and receive interrupts can be sent directly from the UART directly to the interrup~ controller over these lines. The vector interrupt controller has f~ur ~igional interrupt lines w~ic:h ar~ connected to ~S-232 l~terrupt~ ~ 60. Interrupt casc~de lines 62 ~re connec~ed between t~e ~ector interrupt controller and the edge of the RS-422 card ~2. This provides l~e c~rd with the abitlîty Of ca~c~ing mul~iple ~S-~22 ~oards ln a master/sl~ve ~cheme.
Thi6 c~scading method ~ completed by a priority chain control 64 which is u~iliz~d to disconnec~ lower priority c~rds. Priority chain con~rol 64 is connected to vector interrupt controller 56 and, by an additional communio~tion line 66 to ~he edye of the board. Lines 62 and 66 ~re thus used as connections for the cascade line 35 which is illu-strated in ~ig. 3.
Data is transmitted to and from the UART 52 and ~he vector interrupt controller 56 ~y an address bus 68 which ~s oonnected through an address decoding ~nit 70 to the UART 52 and the vector interrupt controller 56. Data can also be tr~nsmitted to and from these circuit parts on a data bus 72.
Transmitter outpu~s and receiver inputs are connected tc RS-422 drivers and receivers 54 and are also brought to the edge of the board for optional communication fonmat~ on a line 74. Drivers and receivers 54 sre also oonnectea to the UART 52 over a line 76.
.
According to the present invention, lines 60 can be utilized for the vectored interrupts and lines 62,6~ can be utili~ed for the priority chain interrupts~ Up to eight inventive communication~/controller boards fii~ilar to 42 can be connected for operation with a fiingel CPU.
~i~. 5 ~hows a plur~lity of boiler control equip-m~nt interaces 81, 82 and 83 which each incorporate a card ~imilar to communication~con~roller ~oard 42. ~he central logic unit 84 incorporates t~e CPU 19 and als~ includes memory cards, ~nd RS-232 communications card, ~nd E2PR~M card~
~ 5 a ~deo control card and a TTL I/O card. ~n ~ssociation with ~he video control ~ard ~ Isystem monitor card is pr~-~ided and ~ a C~T (cathode :eay tube) is connected for v~6ual di~pl~y~.
S The central logic unit 84 also includes an ~S-~22 communications control card ~s do the interfaces 81 thr~ugh 83.
A boiler diagram B6 includes a plur~lity of light emitting diodes at various locations in the diagram which can be driven by the central l~gic unit to illustrate the present condition of the boiler.
Unit switch panel 88 is connected both to the diayram and to the central logic unit for manual control thereof.
lS The central logic unit 84, in an example of the invention, is provided with a Prolog number B~lS-H card rack to which are connected the CPU card 10 which may for example be an Intersil number 3110/3111 CPU card. Memory is provided by a Prolog number 7705 memory expansion card and can option-ally include a Prolog number 7304RS232 communications card.
A Solar Winds System number 3702 is used as the E2PROM card and a Matrox STD-Alpha video controller card is provided.
A Prolog number 7605 TTL I/O card i~ used. The CRT m~y ~e a motorola 12 inch number DS3000-655.
While a ~pecific embodiment of the invention has been shown and described in detail to illustrate the appli-cation of the principles of the invention, it will be under-sto~d that the invention may-be embodied otherwi~e without departing from 6uch principles.
Fig. 4 shows, in a block diagram, the internal structure of card 42. Card 43 ~s substantially the same.
As shown in ~ig. 2, a dual UART 52 which may for example be a Western Digital 2123 is connected to a vector interrupt c~ntroller 56 by four transmit ~nd r.eceive inter-rupt lines 58. Transmit and receive interrupts can be sent directly from the UART directly to the interrup~ controller over these lines. The vector interrupt controller has f~ur ~igional interrupt lines w~ic:h ar~ connected to ~S-232 l~terrupt~ ~ 60. Interrupt casc~de lines 62 ~re connec~ed between t~e ~ector interrupt controller and the edge of the RS-422 card ~2. This provides l~e c~rd with the abitlîty Of ca~c~ing mul~iple ~S-~22 ~oards ln a master/sl~ve ~cheme.
Thi6 c~scading method ~ completed by a priority chain control 64 which is u~iliz~d to disconnec~ lower priority c~rds. Priority chain con~rol 64 is connected to vector interrupt controller 56 and, by an additional communio~tion line 66 to ~he edye of the board. Lines 62 and 66 ~re thus used as connections for the cascade line 35 which is illu-strated in ~ig. 3.
Data is transmitted to and from the UART 52 and ~he vector interrupt controller 56 ~y an address bus 68 which ~s oonnected through an address decoding ~nit 70 to the UART 52 and the vector interrupt controller 56. Data can also be tr~nsmitted to and from these circuit parts on a data bus 72.
Transmitter outpu~s and receiver inputs are connected tc RS-422 drivers and receivers 54 and are also brought to the edge of the board for optional communication fonmat~ on a line 74. Drivers and receivers 54 sre also oonnectea to the UART 52 over a line 76.
.
According to the present invention, lines 60 can be utilized for the vectored interrupts and lines 62,6~ can be utili~ed for the priority chain interrupts~ Up to eight inventive communication~/controller boards fii~ilar to 42 can be connected for operation with a fiingel CPU.
~i~. 5 ~hows a plur~lity of boiler control equip-m~nt interaces 81, 82 and 83 which each incorporate a card ~imilar to communication~con~roller ~oard 42. ~he central logic unit 84 incorporates t~e CPU 19 and als~ includes memory cards, ~nd RS-232 communications card, ~nd E2PR~M card~
~ 5 a ~deo control card and a TTL I/O card. ~n ~ssociation with ~he video control ~ard ~ Isystem monitor card is pr~-~ided and ~ a C~T (cathode :eay tube) is connected for v~6ual di~pl~y~.
S The central logic unit 84 also includes an ~S-~22 communications control card ~s do the interfaces 81 thr~ugh 83.
A boiler diagram B6 includes a plur~lity of light emitting diodes at various locations in the diagram which can be driven by the central l~gic unit to illustrate the present condition of the boiler.
Unit switch panel 88 is connected both to the diayram and to the central logic unit for manual control thereof.
lS The central logic unit 84, in an example of the invention, is provided with a Prolog number B~lS-H card rack to which are connected the CPU card 10 which may for example be an Intersil number 3110/3111 CPU card. Memory is provided by a Prolog number 7705 memory expansion card and can option-ally include a Prolog number 7304RS232 communications card.
A Solar Winds System number 3702 is used as the E2PROM card and a Matrox STD-Alpha video controller card is provided.
A Prolog number 7605 TTL I/O card i~ used. The CRT m~y ~e a motorola 12 inch number DS3000-655.
While a ~pecific embodiment of the invention has been shown and described in detail to illustrate the appli-cation of the principles of the invention, it will be under-sto~d that the invention may-be embodied otherwi~e without departing from 6uch principles.
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A communications and controller board for connecting a plurality of I/O devices to a central pro-cessing unit according to a selected priority for the I/O
devices, comprising:
a dual channel universal asynchronous receiver/
transmitter board having a plurality of transmit and receive interrupt lines;
a vector interrupt controller connected to said transmit and receive interrupt lines for establishing priority among signals on said transmit and receive interrupt lines;
an RS-422 driver/receiver for connection to each I/O device and each connected to said universal asynchronous receiver/transmitter board for transmitting and receiving signals between said I/O devices and said board;
an interrupt cascade line connected to said vector interrupt controller for receiving a signal from other communications and controller boards;
a priority chain control connected to said vector interrupt controller and for connection to a cascade line to permit priority chain control among a plurality of communications and controller boards; and data receive and transmit lines connected to said universal asynchronous receiver/transmitter board and to said vector interrupt controller for receiving and transmitting data.
devices, comprising:
a dual channel universal asynchronous receiver/
transmitter board having a plurality of transmit and receive interrupt lines;
a vector interrupt controller connected to said transmit and receive interrupt lines for establishing priority among signals on said transmit and receive interrupt lines;
an RS-422 driver/receiver for connection to each I/O device and each connected to said universal asynchronous receiver/transmitter board for transmitting and receiving signals between said I/O devices and said board;
an interrupt cascade line connected to said vector interrupt controller for receiving a signal from other communications and controller boards;
a priority chain control connected to said vector interrupt controller and for connection to a cascade line to permit priority chain control among a plurality of communications and controller boards; and data receive and transmit lines connected to said universal asynchronous receiver/transmitter board and to said vector interrupt controller for receiving and transmitting data.
2. A communications and controller board according to claim 1 including a transmit/receive line connected between said receiver/transmitter board and each driver/receiver for establishing communication with said receiver/transmitter board.
3. A communications and controller board according to claim 2 including an address decoder connected in said data line for receiving address information to address data locations in said receiver/transmitter board and said vector interrupt controller.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US60570584A | 1984-04-30 | 1984-04-30 | |
| US605,705 | 1984-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1218465A true CA1218465A (en) | 1987-02-24 |
Family
ID=24424837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000474961A Expired CA1218465A (en) | 1984-04-30 | 1985-02-22 | Communications controller board |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1218465A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0426081A2 (en) * | 1989-10-30 | 1991-05-08 | Kabushiki Kaisha Toshiba | Programmable controller having interrupt controller for determining priority for interrupt requests from a plurality of I/O devices and generating interrupt vector |
| US7328295B2 (en) * | 2002-12-19 | 2008-02-05 | Arm Limited | Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources |
-
1985
- 1985-02-22 CA CA000474961A patent/CA1218465A/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0426081A2 (en) * | 1989-10-30 | 1991-05-08 | Kabushiki Kaisha Toshiba | Programmable controller having interrupt controller for determining priority for interrupt requests from a plurality of I/O devices and generating interrupt vector |
| EP0426081A3 (en) * | 1989-10-30 | 1991-12-18 | Kabushiki Kaisha Toshiba | Programmable controller having interrupt controller for determining priority for interrupt requests from a plurality of i/o devices and generating interrupt vector |
| US5430879A (en) * | 1989-10-30 | 1995-07-04 | Kabushiki Kaisha Toshiba | Programmable controller having a means to accept a plurality of I/O devices mountable in arbitrary slots |
| US7328295B2 (en) * | 2002-12-19 | 2008-02-05 | Arm Limited | Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources |
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